Band gap reference circuit under low supply voltage

Abstract

Proposed is a band gap reference circuit under a low supply voltage capable of generating a band gap reference voltage even under a low supply voltage by using a plurality of bias voltages separately generated and a current source using these bias voltages without using a diode connected structure used in the related art while not being affected by limitations in the operating voltage of a bipolar transistor. The band gap reference circuit under a low supply voltage includes a voltage reference main circuit configured to generate a first node voltage and a second node voltage in response to a first bias voltage and a band gap reference voltage, and a transimpedance amplifier configured to generate the band gap reference voltage by amplifying a difference between the first node voltage and the second node voltage using the first bias voltage, a second bias voltage, and a third bias voltage.

Claims

1. A band gap reference circuit under a low supply voltage comprising: a voltage reference main circuit configured to generate a first node voltage and a second node voltage in response to a first bias voltage and a band gap reference voltage; and a transimpedance amplifier configured to generate the band gap reference voltage by amplifying a difference between the first node voltage and the second node voltage using the first bias voltage, a second bias voltage, and a third bias voltage, wherein the voltage reference main circuit comprises: a first MOS transistor including one terminal connected to a power supply voltage, another terminal connected to a first node that generates the first node voltage, and a gate terminal to which the first bias voltage is applied; a second MOS transistor including one terminal connected to the power supply voltage, another terminal connected to a second node that generates the second node voltage, and a gate terminal to which the first bias voltage is applied; a first bipolar transistor including one terminal connected to the first node and a base terminal to which the band gap reference voltage is applied; a second bipolar transistor including one terminal connected to the second node, another terminal connected to a ground voltage, and a base terminal to which the band gap reference voltage is applied; and a first resistor including one terminal connected to another terminal of the first bipolar transistor and another terminal connected to the ground voltage.

2. The band gap reference circuit under a low supply voltage of claim 1, further comprising: a second resistor including one terminal commonly connected to the other terminal of the first resistor and the another terminal of the second bipolar transistor, and another terminal connected to the ground voltage.

3. The band gap reference circuit under a low supply voltage of claim 1, wherein the transimpedance amplifier comprises: a bias stage configured to generate a fourth node voltage by using the second bias voltage, the third bias voltage, the first node voltage, and the second node voltage; and an inter amplifying stage configured to generate the band gap reference voltage by amplifying the fourth node voltage using the first bias voltage.

4. The band gap reference circuit under a low supply voltage of claim 3, wherein the bias stage comprises: a third MOS transistor including one terminal connected to the first node that generates the first node voltage, another terminal connected to a fourth node that generates the fourth node voltage, and a gate terminal to which the second bias voltage is applied; a fourth MOS transistor including one terminal connected to the second node that generates the second node voltage and a gate terminal to which the second bias voltage is applied; a fifth MOS transistor including one terminal connected to the fourth node and a gate terminal to which the third bias voltage is applied; a sixth MOS transistor including one terminal connected to another terminal of the fourth MOS transistor and a gate terminal to which the third bias voltage is applied; a seventh MOS transistor including one terminal connected to another terminal of the fifth MOS transistor, another terminal connected to the ground voltage, and a gate terminal connected to a common terminal between the fourth MOS transistor and the sixth MOS transistor; and an eighth MOS transistor including one terminal connected to another terminal of the sixth MOS transistor, another terminal connected to the ground voltage, and a gate terminal connected to the gate terminal of the seventh MOS transistor.

5. The band gap reference circuit under a low supply voltage of claim 3, wherein the bias stage comprises: a third MOS transistor including one terminal connected to the first node that generates the first node voltage, another terminal connected to a fourth node that generates the fourth node voltage, and a gate terminal to which the second bias voltage is applied; a fourth MOS transistor including one terminal connected to the second node that generates the second node voltage and a gate terminal to which the second bias voltage is applied; a seventh MOS transistor including one terminal connected to the fourth node, another terminal connected to the ground voltage, and a gate terminal to which the third bias voltage is applied; and an eighth MOS transistor including one terminal connected to another terminal of the fourth MOS transistor, another terminal connected to the ground voltage, and a gate terminal to which the third bias voltage is applied.

6. The band gap reference circuit under a low supply voltage of claim 3, wherein the inter amplifying stage comprises: a first amplifier configured to amplify the fourth node voltage; and a second amplifier configured to generate the band gap reference voltage by amplifying an output of the first amplifier.

7. The band gap reference circuit under a low supply voltage of claim 6, wherein the first amplifier comprises: a ninth MOS transistor including one terminal connected to the power supply voltage and a gate terminal to which the first bias voltage is applied; and a tenth MOS transistor including one terminal connected to another terminal of the ninth MOS transistor, another terminal connected to the ground voltage, and a gate terminal to which the fourth node voltage is applied.

8. The band gap reference circuit under a low supply voltage of claim 7, wherein the second amplifier comprises: an eleventh MOS transistor including one terminal connected to the power supply voltage, another terminal that generates the band gap reference voltage, and a gate terminal to which the first bias voltage is applied; and a twelfth MOS transistor including one terminal that generates the band gap reference voltage, another terminal connected to the ground voltage, and a gate terminal connected to a common terminal between the ninth MOS transistor and the tenth MOS transistor.

9. The band gap reference circuit under a low supply voltage of claim 8, wherein the inter amplifying stage comprises: a ninth MOS transistor including one terminal connected to the power supply voltage and another terminal that generates the band gap reference voltage; and a tenth MOS transistor including one terminal that generates the band gap reference voltage, another terminal connected to the ground voltage, and a gate terminal to which the fourth node voltage is applied.

10. A band gap reference circuit under a low supply voltage comprising: a voltage reference main circuit configured to generate a first node voltage and a second node voltage in response to a first bias voltage and a band gap reference voltage; a bias stage configured to generate a fourth node voltage by using a second bias voltage, a third bias voltage, the first node voltage, and the second node voltage; and an inter amplifying stage configured to generate the band gap reference voltage by amplifying the fourth node voltage using the first bias voltage, wherein the voltage reference main circuit comprises: a first MOS transistor including one terminal connected to a power supply voltage, another terminal connected to a first node that generates the first node voltage, and a gate terminal to which the first bias voltage is applied; a second MOS transistor including one terminal connected to the power supply voltage, another terminal connected to a second node that generates the second node voltage, and a gate terminal to which the first bias voltage is applied; a first bipolar transistor including one terminal connected to the first node and a base terminal to which the band gap reference voltage is applied; a second bipolar transistor including one terminal connected to the second node, another terminal connected to a ground voltage, and a base terminal to which the band gap reference voltage is applied; and a first resistor including one terminal connected to another terminal of the first bipolar transistor and another terminal connected to the ground voltage.

11. The band gap reference circuit under a low supply voltage of claim 10, further comprising: a second resistor including one terminal commonly connected to the another terminal of the first resistor and the another terminal of the second bipolar transistor, and another terminal connected to the ground voltage.

12. The band gap reference circuit under a low supply voltage of claim 10, wherein the bias stage comprises: a third MOS transistor including one terminal connected to the first node that generates the first node voltage, another terminal connected to a fourth node that generates the fourth node voltage, and a gate terminal to which the second bias voltage is applied; a fourth MOS transistor including one terminal connected to the second node that generates the second node voltage and a gate terminal to which the second bias voltage is applied; a fifth MOS transistor including one terminal connected to the fourth node and a gate terminal to which the third bias voltage is applied; a sixth MOS transistor including one terminal connected to another terminal of the fourth MOS transistor and a gate terminal to which the third bias voltage is applied; a seventh MOS transistor including one terminal connected to another terminal of the fifth MOS transistor, another terminal connected to the ground voltage, and a gate terminal connected to a common terminal between the fourth MOS transistor and the sixth MOS transistor; and an eighth MOS transistor including one terminal connected to another terminal of the sixth MOS transistor, another terminal connected to the ground voltage, and a gate terminal connected to the gate terminal of the seventh MOS transistor.

13. The band gap reference circuit under a low supply voltage of claim 10, wherein the bias stage comprises: a third MOS transistor including one terminal connected to the first node that generates the first node voltage, another terminal connected to a fourth node that generates the fourth node voltage, and a gate terminal to which the second bias voltage is applied; a fourth MOS transistor including one terminal connected to the second node that generates the second node voltage and a gate terminal to which the second bias voltage is applied; a seventh MOS transistor including one terminal connected to the fourth node, another terminal connected to the ground voltage, and a gate terminal to which the third bias voltage is applied; and an eighth MOS transistor including one terminal connected to another terminal of the fourth MOS transistor, another terminal connected to the ground voltage, and a gate terminal to which the third bias voltage is applied.

14. The band gap reference circuit under a low supply voltage of claim 10, wherein the inter amplifying stage comprises: a first amplifier configured to amplify the fourth node voltage; and a second amplifier configured to generate the band gap reference voltage by amplifying an output of the first amplifier.

15. The band gap reference circuit under a low supply voltage of claim 14, wherein the first amplifier comprises: a ninth MOS transistor including one terminal connected to the power supply voltage and a gate terminal to which the first bias voltage is applied; and a tenth MOS transistor including one terminal connected to another terminal of the ninth MOS transistor, another terminal connected to the ground voltage, and a gate terminal to which the fourth node voltage is applied.

16. The band gap reference circuit under a low supply voltage of claim 15, wherein the second amplifier comprises: an eleventh MOS transistor including one terminal connected to the power supply voltage, another terminal that generates the band gap reference voltage, and a gate terminal to which the first bias voltage is applied; and a twelfth MOS transistor including one terminal that generates the band gap reference voltage, another terminal connected to the ground voltage, and a gate terminal connected to a common terminal between the ninth MOS transistor and the tenth MOS transistor.

17. The band gap reference circuit under a low supply voltage of claim 10, wherein the inter amplifying stage comprises: a ninth MOS transistor including one terminal connected to the power supply voltage and another terminal that generates the band gap reference voltage; and a tenth MOS transistor including one terminal that generates the band gap reference voltage, another terminal connected to the ground voltage, and a gate terminal to which the fourth node voltage is applied.

18. The band gap reference circuit under a low supply voltage of claim 10, wherein voltage levels of the power supply voltage, the first bias voltage, the second bias voltage, the third bias voltage are 1.8 V (volts), 0.86 V, 0.52 V, and 1.34 V, respectively.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a diagram illustrating an example of a band gap reference circuit in the related art.

(2) FIG. 2 is a diagram illustrating an embodiment of a band gap reference circuit under a low supply voltage according to the present disclosure.

(3) FIG. 3 is a diagram illustrating an embodiment of an internal configuration of a band gap reference circuit under a low supply voltage according to the present disclosure.

(4) FIG. 4 is a diagram illustrating an embodiment of a bias stage constituting a transimpedance amplifier.

(5) FIG. 5 is a diagram illustrating another embodiment of a bias stage constituting a transimpedance amplifier.

(6) FIG. 6 is a diagram illustrating a specific embodiment of an inter amplifying stage.

(7) FIG. 7 is a diagram illustrating a specific embodiment of an inter amplifying stage.

(8) FIG. 8 is a diagram illustrating a specific embodiment of a band gap reference circuit under a low supply voltage according to the present disclosure.

(9) FIG. 9 is a diagram illustrating another specific embodiment of a band gap reference circuit under a low supply voltage according to the present disclosure.

DETAILED DESCRIPTION

(10) In order to fully understand the present disclosure, advantages in operation of the present disclosure, and objects achieved by carrying out the present disclosure, the accompanying drawings for explaining exemplary examples of the present disclosure and the contents described with reference to the accompanying drawings need to be referred to.

(11) Hereinafter, preferred embodiments of the present disclosure are described in detail with reference to the accompanying drawings. The same reference numerals among the reference numerals in each drawing indicate the same members.

(12) FIG. 2 is a diagram illustrating an embodiment of a band gap reference circuit 200 under a low supply voltage according to the present disclosure.

(13) Referring to FIG. 2, the band gap reference circuit 200 under a low supply voltage according to the present disclosure includes a band gap reference main circuit unit Voltage Reference Main Circuit 210 and a transimpedance amplifier 250.

(14) The Voltage Reference Main Circuit 210 generates a first node voltage V.sub.N1 and a second node voltage V.sub.N2 in response to a first bias voltage V.sub.BIAS1 and a band gap reference voltage V.sub.REF.

(15) The transimpedance amplifier 250 includes a bias stage Bias Stage 220 and an inter amplifying stage Inter Amplifying Stage 230 that generate the band gap reference voltage V.sub.REF by amplifying the first node voltage V.sub.N1 and the second node voltage V.sub.N2 using the first bias voltage V.sub.BIAS1, a second bias voltage V.sub.BIAS2, and a third bias voltage V.sub.BIAS3.

(16) The first bias voltage V.sub.BIAS1 to the third bias voltage V.sub.BIAS3 are voltages generated externally and applied to the band gap reference circuit 200 under a low supply voltage according to the present disclosure.

(17) For example, assuming that the voltage level of a power supply voltage V.sub.DD is 1.8 V (Volts), the voltage levels of the first bias voltage V.sub.BIAS1 to the third bias voltage V.sub.BIAS3 can be set to 0.86 V (Volts), 0.52 V, and 1.34 V, respectively.

(18) FIG. 3 is a diagram illustrating an embodiment of an internal configuration of the band gap reference circuit under a low supply voltage according to the present disclosure.

(19) Referring to FIG. 3, the Voltage Reference Main Circuit 210 includes a first MOS transistor M1, a second MOS transistor M2, a first bipolar transistor B1, a second bipolar transistor B2, a first resistor R1, and a second resistor R2, and the transimpedance amplifier 250 is expressed in the form of a differential amplifier.

(20) The first MOS transistor M1 has one terminal connected to the power supply voltage V.sub.DD, another terminal connected to a first node N1, and a gate terminal to which the first bias voltage V.sub.BIAS1 is applied. The second MOS transistor M2 has one terminal connected to the power supply voltage V.sub.DD, another terminal connected to a second node N2, and a gate terminal to which the first bias voltage V.sub.BIAS1 is applied. In FIG. 3, the voltage level of the first node N1 is defined as V.sub.N1 and the voltage level of the second node N2 is defined as V.sub.N2.

(21) The first bipolar transistor B1 has one terminal connected to the first node N1, and a base terminal to which the band gap reference voltage V.sub.REF is applied. The second bipolar transistor B2 has one terminal connected to the second node N2, and a base terminal to which the band gap reference voltage V.sub.REF is applied.

(22) The first resistor R1 has one terminal connected to another terminal of the first bipolar transistor B1. The second resistor R2 has one terminal commonly connected to the other terminal of the first resistor R1 and another terminal of the second bipolar transistor B2, and the other terminal connected to a ground voltage GND.

(23) Referring to FIG. 3, it can be seen that the transimpedance amplifier 250 generates the band gap reference voltage V.sub.REF by amplifying the first node voltage V.sub.N1 and the second node voltage V.sub.N2 using the first bias voltage V.sub.BIAS1, the second bias voltage V.sub.BIAS2, and the third bias voltage V.sub.BIAS3.

(24) Referring to FIG. 3, in order to generate the band gap reference voltage V.sub.REF insensitive to temperature changes from the two bipolar transistors B1 and B2, currents flowing through the two MOS transistors M1 and M2 need to be equal to each other by making the voltage levels of the two node voltages V.sub.N1 and V.sub.N2 equal to each other, and to this end, the present disclosure proposes the use of the transimpedance amplifier 250.

(25) That is, the transimpedance amplifier 250 generates the band gap reference voltage V.sub.REF by amplifying the difference between the two input voltages V.sub.N1 and V.sub.N2, and the band gap reference voltage V.sub.REF controls currents flowing through the two bipolar transistors B1 and B2, so that the two node voltages V.sub.N1 and V.sub.N2 are made equal to each other as a result.

(26) Referring to FIG. 2, the transimpedance amplifier 250 includes the Bias Stage 220 and the Inter Amplifying Stage 230, and actual configurations of the Bias Stage 220 and the Inter Amplifying Stage 230 will be described below. In the following description, the Bias Stage 220 and the Inter Amplifying Stage 230 according to embodiments will be distinguished using reference sign -. For example, reference signs of the bias stage 220 according to two embodiments are 220-1 and 220-2, respectively.

(27) FIG. 4 is a diagram illustrating an embodiment of the bias stage constituting the transimpedance amplifier.

(28) Referring to FIG. 4, the bias stage 220-1 generates a fourth node voltage V.sub.N4 by using the second bias voltage V.sub.BIAS2, the third bias voltage V.sub.BIAS3, the first node voltage V.sub.N1, and the second node voltage V.sub.N2, and includes a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, and an eighth MOS transistor M8.

(29) The third MOS transistor M3 has one terminal connected to the first node N1, another terminal connected to a fourth node N4, and a gate terminal to which the second bias voltage V.sub.BIAS2 is applied.

(30) The fourth MOS transistor M4 has one terminal connected to the second node N2 and a gate terminal to which the second bias voltage V.sub.BIAS2 is applied.

(31) The fifth MOS transistor M5 has one terminal connected to the fourth node N4, and a gate terminal to which the third bias voltage V.sub.BIAS3 is applied.

(32) The sixth MOS transistor M6 has one terminal connected to another terminal of the fourth MOS transistor M4, and a gate terminal to which the third bias voltage V.sub.BIAS3 is applied.

(33) The seventh MOS transistor M7 has one terminal connected to another terminal of the fifth MOS transistor M5, another terminal connected to the ground voltage GND, and a gate terminal connected to a common terminal between the fourth MOS transistor M4 and the sixth MOS transistor M6.

(34) The eighth MOS transistor M8 has one terminal connected to another terminal of the sixth MOS transistor M6, another terminal connected to the ground voltage GND, and a gate terminal connected to the gate terminal of the seventh MOS transistor M7.

(35) In the above description, a voltage level of the fourth node N4 is indicated by V.sub.N4, the fourth node and the voltage level of the fourth node are the same as the explanation logic for the first node N1 and the second node N2, and the same applies in the following description.

(36) FIG. 5 is a diagram illustrating another embodiment of the bias stage constituting the transimpedance amplifier.

(37) Referring to FIG. 5, the bias stage 220-2 generates the fourth node voltage V.sub.N4 by using the second bias voltage V.sub.BIAS2 and the third bias voltage V.sub.BIAS3, and includes the third MOS transistor M3, the fourth MOS transistor M4, the seventh MOS transistor M7, and the eighth MOS transistor M8.

(38) The third MOS transistor M3 has one terminal connected to the first node N1, another terminal connected to the fourth node N4, and a gate terminal to which the second bias voltage V.sub.BIAS2 is applied.

(39) The fourth MOS transistor M4 has one terminal connected to the second node N2 and a gate terminal to which the second bias voltage V.sub.BIAS2 is applied.

(40) The seventh MOS transistor M7 has one terminal connected to the fourth node N4, another terminal connected to the ground voltage GND, and a gate terminal to which the third bias voltage V.sub.BIAS3 is applied.

(41) The eighth MOS transistor M8 has one terminal connected to another terminal of the fourth MOS transistor M4, another terminal connected to the ground voltage GND, and a gate terminal to which the third bias voltage V.sub.BIAS3 is applied.

(42) The third MOS transistor M3 and the fourth MOS transistor M4 are P-type MOS transistors, the fifth MOS transistor M5 to the eighth MOS transistor M8 are N-type MOS transistors, and the same applies in the following description.

(43) In FIGS. 4 and 5, the fourth node N4 generates the fourth node voltage V.sub.N4 in the same manner.

(44) FIG. 6 is a diagram illustrating a specific embodiment of the inter amplifying stage.

(45) Referring to FIG. 6, the Inter Amplifying Stage 230-1 generates the band gap reference voltage V.sub.REF by amplifying the applied fourth node voltage V.sub.N4, and to this end, includes two amplifiers INV1 and INV2 serially connected to each other.

(46) The first amplifier INV1 includes a ninth MOS transistor M9 having one terminal connected to the power supply voltage V.sub.DD and a gate terminal to which the first bias voltage V.sub.BIAS1 is applied, and a tenth MOS transistor M10 having one terminal connected to another terminal of the ninth MOS transistor M9, another terminal connected to the ground voltage GND, and a gate terminal to which the fourth node voltage V.sub.N4 is applied.

(47) The second amplifier INV2 includes an eleventh MOS transistor M11 having one terminal connected to the power supply voltage V.sub.DD, a gate terminal to which the first bias voltage V.sub.BIAS1 is applied, and a twelfth MOS transistor M12 having one terminal connected to another terminal of the eleventh MOS transistor M11, another terminal connected to the ground voltage GND, and a gate terminal connected to a common terminal between the ninth MOS transistor M9 being an output terminal of the first amplifier INV1 and the tenth MOS transistor M10.

(48) The band gap reference voltage V.sub.REF is output to a common terminal between the eleventh MOS transistor M11 and the twelfth MOS transistor M12.

(49) FIG. 7 is a diagram illustrating a specific embodiment of the inter amplifying stage.

(50) Referring to FIG. 7, the Inter Amplifying Stage 230-2 generates the band gap reference voltage V.sub.REF by amplifying the applied fourth node voltage V.sub.N4, and to this end, includes one amplifier INV1.

(51) The first amplifier INV1 includes a ninth MOS transistor M9 having one terminal connected to the power supply voltage V.sub.DD, another terminal that generates the band gap reference voltage V.sub.REF, and a gate terminal to which the first bias voltage V.sub.BIAS1 is applied, and a tenth MOS transistor M10 having one terminal that generates the band gap reference voltage V.sub.REF, another terminal connected to the ground voltage GND, and a gate terminal to which the fourth node voltage V.sub.N4 is applied.

(52) The two amplifiers INV1 and INV2 included in the Inter Amplifying Stage 230 have the same structure as an inverter, and one of the electrical characteristics of the inverter may be the amplification of an input signal.

(53) In the structures of the inverters illustrated in FIGS. 6 and 7, the ninth MOS transistor M9 and the eleventh MOS transistor M11 serve as loads, respectively.

(54) FIG. 8 is a diagram illustrating a specific embodiment of the band gap reference circuit under a low supply voltage according to the present disclosure.

(55) FIG. 9 is a diagram illustrating another specific embodiment of the band gap reference circuit under a low supply voltage according to the present disclosure.

(56) Referring to FIG. 8, the band gap reference circuit 200 under a low supply voltage according to the present disclosure includes a main circuit unit 210 and a transimpedance amplifier 250, and the transimpedance amplifier 250 includes the bias stage 220-1 illustrated in FIG. 4 and the Inter Amplifying Stage 230-1 illustrated in FIG. 6.

(57) Referring to FIG. 9, the band gap reference circuit 200 under a low supply voltage according to the present disclosure includes a main circuit unit 210 and a transimpedance amplifier 250, and the transimpedance amplifier 250 includes the bias stage 220-2 illustrated in FIG. 5 and the Inter Amplifying Stage 230-1 illustrated in FIG. 6.

(58) Although the technical spirit of the present disclosure has been described together with the accompanying drawings, this is an illustrative example of a preferred embodiment of the present disclosure, but does not limit the present disclosure. In addition, it is clear that various modifications and imitations can be made by anyone skilled in the art to which the present disclosure belongs without departing from the scope of the technical spirit of the present disclosure.