INTEGRATED CIRCUIT AND ELECTRONIC DEVICE

Abstract

An integrated circuit and an electronic device, and provides an integrated circuit having better area efficiency. The integrated circuit may be a resistive random access memory, which includes a plurality of resistive memory cells arranged in row and column directions; each resistive memory cell includes a resistive switching unit and a switch unit coupled to the resistive switching unit; the resistive switching units in the column direction are respectively coupled to corresponding source lines; the source lines include first source lines and second source lines; and the first source lines and the second source lines are located on different interconnect layers.

Claims

1-19. (canceled)

20. An integrated circuit, comprising: a plurality of integrated circuit units and a plurality of source lines, wherein the plurality of source lines comprise first source lines and second source lines located on different layers, the first source lines and the second source lines are located on different interconnect layers, and the integrated circuit units are coupled to the first source lines or the second source lines.

21. The integrated circuit according to claim 20, wherein the integrated circuit is a memory, which comprises a plurality of storage units and a plurality of source lines, wherein the plurality of source lines comprise first source lines and second source lines located on different layers, the first source lines and the second source lines are located on different interconnect layers, and the storage units are coupled to the first source lines or the second source lines.

22. The integrated circuit according to claim 21, wherein the memory is a resistive random access memory, the storage units are a plurality of resistive memory cells arranged in row and column directions, each resistive memory cell comprises a resistive switching unit and a switch unit coupled to the resistive switching unit, the source lines comprise first source lines and second source lines, and the first source lines and the second source lines are located on different interconnect layers.

23. The integrated circuit according to claim 22, wherein the first source lines are located on a first interconnect layer, and the second source lines are located on a second interconnect layer above the first interconnect layer.

24. The integrated circuit according to claim 20, wherein a projection of at least one of the first source lines at least partially overlaps the projection of the corresponding second source line in a vertical direction.

25. The integrated circuit according to claim 24, wherein the first source line and the second source line, of which the projections at least partially overlap with each other in the vertical direction, are respectively coupled to the storage units located on different sides of the first source line and the second source line.

26. The integrated circuit according to claim 20, wherein the source lines are perpendicular to word lines in a spatial direction, and the source lines are parallel to bit lines in the spatial direction.

27. The integrated circuit according to claim 21, wherein the source lines are perpendicular to word lines in a spatial direction, and the source lines are parallel to bit lines in the spatial direction.

28. The integrated circuit according to claim 22, wherein the source lines are perpendicular to word lines in a spatial direction, and the source lines are parallel to bit lines in the spatial direction.

29. The integrated circuit according to claim 23, wherein the source lines are perpendicular to word lines in a spatial direction, and the source lines are parallel to bit lines in the spatial direction.

30. The integrated circuit according to claim 20, wherein the bit lines are located on a third interconnect layer above a second interconnect layer.

31. The integrated circuit according to claim 21, wherein the bit lines are located on a third interconnect layer above a second interconnect layer.

32. The integrated circuit according to claim 22, wherein the bit lines are located on a third interconnect layer above a second interconnect layer.

33. The integrated circuit according to claim 23, wherein bit lines are located on a third interconnect layer above the second interconnect layer.

34. The integrated circuit according to claim 20, wherein the first source lines are electrically connected to a substrate through N groups of contact plugs and N-1 groups of bottom connecting platforms, and the second source lines are electrically connected to the substrate through M groups of contact plugs and M-1 groups of bottom connecting platforms, wherein M is greater than N.

35. The integrated circuit according to claim 21, wherein the first source lines are electrically connected to a substrate through N groups of contact plugs and N-1 groups of bottom connecting platforms, and the second source lines are electrically connected to the substrate through M groups of contact plugs and M-1 groups of bottom connecting platforms, wherein M is greater than N.

36. The integrated circuit according to claim 22, wherein the first source lines are electrically connected to a substrate through N groups of contact plugs and N-1 groups of bottom connecting platforms, and the second source lines are electrically connected to the substrate through M groups of contact plugs and M-1 groups of bottom connecting platforms, wherein M is greater than N.

37. The integrated circuit according to claim 23, wherein the first source lines are electrically connected to a substrate through N groups of contact plugs and N-1 groups of bottom connecting platforms, and the second source lines are electrically connected to the substrate through M groups of contact plugs and M-1 groups of bottom connecting platforms, wherein M is greater than N.

38. An electronic device, comprising the integrated circuit according to claim 20.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG. 1 is a plan view of part of the structure of a resistive random access memory. FIG. 2 is a plan view of part of the structure of a resistive random access memory in accordance with an embodiment of the present invention. FIG. 3A is a cross-sectional view of a resistive random access memory in the direction of A-A′ in accordance with an embodiment of the present invention.

[0018] FIG. 3B is a cross-sectional view of a resistive random access memory in the direction of B-B′ in accordance with an embodiment of the present invention.

[0019] FIG. 3C is a cross-sectional view of a resistive random access memory in the direction of C-C′ in accordance with an embodiment of the present invention.

[0020] FIG. 3D is a cross-sectional view of a resistive random access memory in the direction of D-D′ in accordance with an embodiment of the present invention.

REFERENCE NUMERALS

[0021] 100: substrate [0022] 101, 102, 103, 104, 105: insulating layer [0023] 108, 109, 110, 111, 120, 208, 209, 210, 211, 220, 222: contact plug [0024] 112(M1), 113(M2), 212(M1), 213(M2): bottom connecting platform [0025] 106, 107, 206, 207: resistive switching unit [0026] SL0, SL0′, SL1, SL2: source line [0027] WL0, WL0′, WL1, WL2: word line [0028] BL0, BL0′, BL: bit line

DETAILED DESCRIPTION

[0029] To make the objectives, features, and advantages of the present invention clearer and easier to understand, the following describes the technical solutions in embodiments of the present invention clearly and completely in conjunction with the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are merely some of the embodiments of the present invention, not all of the embodiments. On the basis of the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without inventive efforts shall fall within the scope of protection of the present invention.

[0030] An embodiment of the present invention provides an integrated circuit, including a plurality of integrated circuit units and a plurality of source lines, where the plurality of source lines include first source lines and second source lines located on different layers, the first source lines and the second source lines are located on different interconnect layers, and the integrated circuit units are coupled to the first source lines or the second source lines.

[0031] The first source lines are located on a first interconnect layer, and the second source lines are located on a second interconnect layer above the first interconnect layer.

[0032] Another embodiment of the present invention provides a memory, including a plurality of storage units and a plurality of source lines, where the plurality of source lines include first source lines and second source lines located on different layers, the first source lines and the second source lines are located on different interconnect layers, and the storage units are coupled to the first source lines or the second source lines.

[0033] The first source lines are located on a first interconnect layer, and the second source lines are located on a second interconnect layer above the first interconnect layer; and the first source lines and the second source lines, of which the projections at least partially overlap with each other in the vertical direction, are respectively coupled to the storage units located on different sides of the first source lines and the second source lines.

[0034] Another embodiment of the present invention provides a resistive random access memory. FIG. 2 is a plan view of part of the structure of a resistive random access memory in accordance with an embodiment of the present invention. FIG. 3A is a cross-sectional view along section line A-A′ in FIG. 2. FIG. 3B is a cross-sectional view along section line B-B′ in FIG. 2. FIG. 3C is a cross-sectional view along section line C-C′ in FIG. 2. FIG. 3D is a cross-sectional view along section line D-D′ in FIG. 2.

[0035] FIG. 2 is a schematic plan view of part of the structure of a resistive random access memory in accordance with an embodiment of the present invention. A memory array has a multi-layer wiring structure on a silicon substrate. In this embodiment, metal layers and control gates are provided on the substrate. The control gate may be one of a high K metal gate, a Fin Field Effect Transistor (FiNFET), or a conductive polysilicon layer. Bit lines (BLs) are formed in the direction orthogonal to word lines (WLs). In order to more clearly show the positions of source lines and resistive switching units, the BLs are not shown in FIG. 2. The BLs are located in a third interconnect layer above a second interconnect layer. The BLs are made of metal such as aluminum (Al) or copper (Cu).

[0036] Source lines SL1/SL2 are formed parallel to the BLs in the spatial direction, and the source lines SL1/SL2 are perpendicular to the WLs in the spatial direction. In this embodiment, the source lines SL1 are located in a first interconnect layer and are arranged through the same metal layer 1 (M1) as bottom connecting platforms 112. The source lines SL2 are located in the second interconnect layer and are arranged through the same metal layer (M2) as bottom connecting platforms 113. The resistive switching units are located on an insulating layer between the second interconnect layer and the third interconnect layer.

[0037] The resistive switching unit in this embodiment may be any one or a combination of several of a Resistive Random Access Memory (RRAM), a Magnetic Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM), or a Phase-Change Random Access Memory (PRAM).

[0038] FIG. 3A, FIG. 3B, FIG. 3C, and FIG. 3D show cross-sectional views of a region of an array shown in FIG. 2 along section lines A-A′, B-B′, C-C′, D-D′, respectively.

[0039] In FIG. 3A, for example, an insulating layer 101 is formed on a surface of a substrate 100 to define an active area of an access transistor, and the insulating layer 101 is made of a silicon oxide film or the like. On the substrate 100, the source lines SL1 are located on an insulating layer 102, are arranged through the metal layer 1 (M1), and are coupled to the columns where resistive switching units 106 are located. The metal layer 1 may be made of metal such as Al or Cu. The source lines SL1 are perpendicular to the WLs in the spatial direction and parallel to the BLs in the spatial direction. Shown in the figure are connection portions between the source lines SL1 and contact plugs, and therefore, the spatial relationships cannot be directly observed. Contact holes are formed in the interlayer insulating layer 101, contact plugs 120 are formed, and the source lines SL1 are electrically connected to the surface of the substrate 100 through the contact plugs 120. The resistive switching units 106 are formed on the insulating layer 104 and are connected to the metal layer 2 through contact plugs 110 on the insulating layer 104. The BLs are arranged through the metal layer 3 (M3), and are connected to the resistive switching units 106 through the contact plugs 111.

[0040] As shown in FIG. 3B, the insulating area 101 is formed on the surface of the substrate 100 to define the active area of the access transistor. On the substrate 100, the source lines SL2 are arranged through the metal layer 2 (M2) located above the metal layer 1 (M1), and the source lines SL2 are coupled to the columns where resistive switching units 206 are located. The metal layer 2 may be made of metal such as Al or Cu. The source lines SL2 are perpendicular to the WLs in the spatial direction and parallel to the BLs in the spatial direction. Similarly, the source lines SL2 are electrically connected to the surface of the substrate 100 through contact plugs 220 and 222 in two contact holes, formed in an interlayer insulating film such as a silicon oxide film, and a bottom connecting platform 221, respectively. On the source lines SL2, the BLs are arranged through the metal layer 3 (M3).

[0041] FIG. 3C shows a cross-sectional view in the direction of C-C′. It can be seen that the source lines SL1 and the source lines SL2 are on different metal layers. The source lines SL1 and the source lines SL2 are coupled to storage units on different sides, and the projections of the source lines overlap with each other in the vertical direction. Shown in the figure is the connection portions between the source lines SL1 and source lines SL2 and the contact plugs, and the source lines SL1 and the source lines SL2 themselves are parallel to the BLs in the spatial direction. The source lines SL1 are electrically connected to the surface of the substrate 100 through the contact plugs 120, and the source lines SL2 are electrically connected to the surface of the substrate 100 through the contact plugs 220, the bottom connecting platforms 221, and the contact plugs 222.

[0042] FIG. 3D shows a cross-sectional view in the direction of D-D′. The source lines SL1 are located on the first interconnect layer and are formed through the metal layer 1 (M1); and the source lines SL2 are located on the second interconnect layer and are formed through the metal layer 2 (M2). The metal layer 2 (M2) is located above the metal layer 1 (M1). The source lines SL1 are coupled to the first resistive switching units 106, and the source lines SL2 are coupled to the second resistive switching units 206. What can be seen in the figure is the cross-sections of the source line SL1 and the source line SL2, of which the projections at least partially overlap with each other in the vertical direction, and the source line SL1 and the source line SL2 are parallel to the BLs in the spatial direction.

[0043] Another embodiment of the present invention is an electronic device using the integrated circuit in accordance with the mentioned embodiments. The integrated circuit includes a plurality of integrated circuit units and a plurality of source lines, where the plurality of source lines include first source lines and second source lines located on different layers, the first source lines and the second source lines are located on different interconnect layers, and the integrated circuit units are coupled to the first source lines or the second source lines.

[0044] According to the description, the descriptions of the reference terms “an embodiment”, “some embodiments”, “an example”, “a specific example”, “some examples,” and the like mean that specific features, structures, materials, or characteristics described in combination with the embodiment(s) or example(s) are included in at least one embodiment or example of the present invention. Besides, the specific features, structures, materials, or characteristics described may be combined in proper manners in any one or more embodiments or examples. In addition, a person skilled in the art may integrate or combine different embodiments or examples described in the description and features of different embodiments or examples as long as they are not contradictory to each other.

[0045] In addition, terms “first” and “second” are used merely for the purpose of description, and shall not be construed as indicating or implying relative importance or implying the quantity of indicated technical features. Therefore, features defined by “first” or “second” explicitly or implicitly indicate that at least one of the features is included. In the descriptions of the present invention, unless otherwise explicitly specified, “a plurality of” means two or more.

[0046] The above are only specific implementations of the present invention, but the scope of protection of the present invention is not limited to this. Any person skilled in the art can easily conceive of changes or substitutions within the technical scope disclosed in the present invention, which shall all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.