HETEROGENEOUS STRUCTURES AND PROCESSING METHODS

Abstract

An example of a method of making a heterogeneous semiconductor structure, includes providing a first substrate including a first material; providing a second substrate including a printable processable coupon, wherein the coupon includes a second material different from the first material; and printing the coupon to the first substrate. The method can includes processing the coupon on the first substrate to form an integrated circuit. An example of a heterogeneous structure includes a substrate including a first material and one or more non-native coupons disposed on the substrate, the coupon including a second material different from the first material. The second material can be or comprise an epitaxial material, such as a compound semiconductor material. The first material can be or comprise an elemental semiconductor, such as silicon.

Claims

1. A method of making a heterogeneous structure, the method comprising: providing a first substrate comprising a first material; providing a second substrate comprising a printable processable coupon, wherein the coupon comprises a second material different from the first material; and printing the coupon to the first substrate.

2. The method of claim 1, wherein the first substrate is a semiconductor substrate comprising a substrate circuit and the method comprises electrically connecting the substrate circuit to an integrated circuit formed in or on the coupon.

3. The method of claim 1, wherein the coupon comprises epitaxial material.

4. The method of claim 3, wherein the epitaxial material is unprocessed during the printing.

5. The method of claim 1, comprising pattern-wise covering the first substrate with a protection layer and subsequently processing the coupon separately from the first substrate.

6. The method of claim 1, comprising pattern-wise covering the coupon with a protection layer and subsequently processing the first substrate separately from the coupon.

7. The method of claim 1, wherein the first substrate is process-capable at a first resolution and the second substrate is process capable at a second resolution different from the first resolution and the method comprises processing the coupon at the first resolution.

8. The method of claim 7, wherein the first resolution is higher than the second resolution.

9. The method of claim 1, wherein the first substrate is an elemental semiconductor substrate.

10. The method of claim 1, wherein the second substrate is a compound semiconductor substrate.

11. The method of claim 1, wherein the coupon is a first coupon and the integrated circuit is a first integrated circuit, and the method comprises: providing a third substrate comprising a printable processable second coupon, wherein the second coupon comprises a third material different from the first material and different from the second material; and printing the second coupon to the first substrate.

12. The method of claim 11, wherein the second coupon comprises epitaxial material.

13. The method of claim 12, wherein the epitaxial material is unprocessed during the printing.

14. The method of claim 11, wherein the first substrate is process-capable at a first resolution and the third substrate is process capable at a third resolution different from the first resolution and wherein the second coupon is processed at the first resolution.

15. The method of claim 14, wherein the second substrate is process capable at a second resolution different from the first resolution and different from the third resolution.

16. The method of claim 14, wherein the first resolution is higher than the third resolution.

17. The method of claim 11, comprising pattern-wise coating the first substrate with a process-protective coating and processing the first coupon and the second coupon separately from the first substrate.

18. The method of claim 11, comprising pattern-wise coating the first substrate and the first coupon with a process-protective coating and processing the second coupon separately from the first substrate and the first coupon.

19. (canceled)

20. The method of claim 11, wherein the first substrate is a semiconductor substrate comprising a substrate circuit and the method comprises electrically connecting the substrate circuit to the second integrated circuit.

21. The method of claim 11, comprising patterning the first substrate and the second coupon in a common step.

22. The method of claim 1, comprising patterning the first substrate and the coupon in a common step.

23. (canceled)

24. The method of claim 1, wherein the coupon comprises a broken or separated tether after the coupon is printed to the first substrate.

25-45. (canceled)

46. The method of claim 1, comprising processing the coupon on the first substrate to form an integrated circuit.

47. The method of claim 11, comprising processing the second coupon to form a second integrated circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Drawings are presented herein for illustration purposes, not for limitation. Drawings are not necessarily drawn to scale. The foregoing and other objects, aspects, features, and advantages of the disclosure will become more apparent and may be better understood by referring to the following description taken in conjunction with the accompanying drawings, in which:

[0034] FIGS. 1-8 illustrate methods of forming a heterogeneous structure that includes integrated circuits formed in or on coupons that are electrically connected to a substrate circuit, according to illustrative embodiments of the present disclosure; and

[0035] FIG. 9-11 illustrate methods of forming a source wafer starting from a heterogeneous structure according to FIG. 5, according to illustrative embodiments of the present disclosure.

DETAILED DESCRIPTION OF CERTAIN EMBODIMENTS

[0036] It is contemplated that systems, devices, methods, and processes of the disclosure encompass variations and adaptations developed using information from the embodiments described herein. Adaptation and/or modification of the systems, devices, methods, and processes described herein may be performed by those of ordinary skill in the relevant art.

[0037] Throughout the description, where articles, devices, and systems are described as having, including, or comprising specific components, or where processes and methods are described as having, including, or comprising specific steps, it is contemplated that, additionally, there are articles, devices, and systems according to certain embodiments of the present disclosure that consist essentially of, or consist of, the recited components, and that there are processes and methods according to certain embodiments of the present disclosure that consist essentially of, or consist of, the recited processing steps.

[0038] It should be understood that the order of steps or order for performing certain action is immaterial so long as operability is not lost. Moreover, two or more steps or actions may be conducted simultaneously.

[0039] FIG. 1 illustrates a step of providing a substrate 10 (e.g., a wafer) (e.g., a silicon wafer). FIG. 2 illustrates a step of micro-transfer printing coupons 20 onto substrate 10 with an elastomer stamp 40 including posts 42. FIG. 3 illustrates coupons 20 disposed on substrate 10, where coupons 20 include a material different from a material included in substrate 10. For example, coupons 20 include a compound semiconductor material (e.g., processable at a second resolution) and substrate 10 includes an elemental semiconductor (e.g., silicon) (e.g., processable at a first resolution higher than the second resolution). FIG. 4 illustrates covering (e.g., coating) substrate 10 with protection layer 30 leaving portions of coupons 20 exposed for processing. FIG. 5 illustrates forming integrated circuits 22 in or on coupons 20. FIG. 6 illustrates protection layer 30 having been removed to expose substrate 10 again and covering (e.g., coating) coupons 20 with a new protection layer 30 leaving portions of substrate 10 exposed for processing. FIG. 7 illustrates forming substrate circuit 12 (e.g., an integrated circuit) in or on substrate 10. FIG. 8 illustrates protection layer 30 having been removed from coupons 20 and electrically connecting substrate circuit 12 in or on substrate 10 to integrated circuits 22 in or on coupons 20 using electrical connections 50. Dielectric layer 52 is used to prevent unwanted electrical contact between portions of coupon 20 and electrical connections 50.

[0040] FIG. 9 illustrates a heterogeneous structure that includes printable processed coupons 20. In this way, coupons 20 can be printed to substrate 10 and processed using a process (e.g., at a resolution) amenable to processing for substrate 10 (e.g., a silicon process for a 300 nm silicon wafer) before being printed to a destination substrate (e.g., thereby enabling higher resolution processing). Anchors 16 and coupon component tethers 18 are formed with coupons 20 being disposed entirely over sacrificial portions 14. FIG. 10 illustrates etching (e.g., wet or dry etching) sacrificial portions 14 so that coupons 20 are suspended by coupon component tethers 18 over substrate 10 defining gap 15. FIG. 11 illustrates stamp 40 picking up processed coupons 20 to micro-transfer print them to a destination substrate. Printing such processed coupons 20 would break (e.g., fracture) or separate coupon component tethers 18.

[0041] In some embodiments, an heterogeneous structure that includes coupon(s) 20 electrically connected to substrate circuit 12 by electrical connections 50 (e.g., according to FIG. 8) is or is processed to be a source wafer for heterogeneous structure(s), for example that can be printed (e.g., micro-transfer printed), for example in a method analogous to one shown in FIGS. 9-11.

[0042] Various embodiments of structures and methods were described herein that included (e.g., were made by) printing coupons. Printing may include or be micro-transfer printing. As used herein, micro-transfer-printing involves using a transfer device (e.g., an elastomeric stamp, such as a polydimethylsiloxane (PDMS) stamp) to transfer a coupon using controlled adhesion. For example, an exemplary transfer device can use kinetic or shear-assisted control of adhesion between a transfer device and a coupon. It is contemplated that, in certain embodiments, where a method is described as including micro-transfer-printing a coupon, other analogous embodiments exist using a different transfer method. In methods according to certain embodiments, a vacuum tool, electrostatic tool or other transfer device is used to print a coupon.

[0043] Examples of micro-transfer printing processes suitable for printing coupons onto substrates are described in U.S. Pat. No. 8,722,458 entitled Optical Systems Fabricated by Printing-Based Assembly, U.S. Pat. No. 9,362,113 entitled Engineered Substrates for Semiconductor Epitaxy and Methods of Fabricating the Same, U.S. Pat. No. 9,358,775 entitled Apparatus and Methods for Micro-Transfer-Printing, U.S. patent application Ser. No. 14/822,868, filed on Aug. 10, 2015, entitled Compound Micro-Assembly Strategies and Devices, and U.S. Pat. No. 9,704,821 entitled Stamp with Structured Posts, each of which is hereby incorporated by reference herein in its entirety.

[0044] Certain embodiments of the present disclosure were described above. It is, however, expressly noted that the present disclosure is not limited to those embodiments, but rather the intention is that additions and modifications to what was expressly described in the present disclosure are also included within the scope of the disclosure. Moreover, it is to be understood that the features of the various embodiments described in the present disclosure were not mutually exclusive and can exist in various combinations and permutations, even if such combinations or permutations were not made express, without departing from the spirit and scope of the disclosure. Having described certain implementations of heterogeneous wafer structures, heterogeneous semiconductor structures, methods of their fabrication, and methods of their use, it will now become apparent to one of skill in the art that other implementations incorporating the concepts of the disclosure may be used. Therefore, the disclosure should not be limited to certain implementations, but rather should be limited only by the spirit and scope of the following claims.

PARTS LIST

[0045] 10 substrate/wafer [0046] 12 substrate circuit [0047] 14 sacrificial portion [0048] 15 gap [0049] 16 anchor [0050] 18 coupon component tether [0051] 20 coupon/epitaxial layer [0052] 22 integrated circuit [0053] 24 tether/broken or separated tether [0054] 30 protection layer [0055] 40 transfer device/stamp [0056] 42 post/stamp post [0057] 50 electrical connection/wire/trace/interconnect [0058] 52 dielectric/dielectric layer [0059] 99 heterogeneous structure/heterogeneous wafer/source wafer