SYSTEMS AND METHODS FOR REALIZING HIGH-SPEED LOW-POWER WIRELINE TRANSCEIVERS

Abstract

A method for creating and transmitting an encoded data stream comprises receiving a data stream that includes a number M of same-rate data streams x.sub.1, x.sub.2, . . . , x.sub.M, where each data stream in the M same-rate data streams has an ordered number of bits with each bit having a period of T.sub.sym and a clock pulse signal that includes a plurality of pulses where a time duration of each pulse in the plurality of pulses corresponds to T.sub.sym/M. A number M of pulse signals is generated, and an encoded data stream is created by multiplying a value of one bit of each data stream in the ordered number M of data streams by a value of a corresponding of a pulse signal in the ordered number M of orthogonal pulse signals to provide M results, and summing the M results. Once summed, the encoded data stream can be transmitted.

Claims

1. A method for creating and transmitting an encoded data stream comprising: receiving a data stream denoted as x(n) comprising a number M of same-rate data streams x.sub.1, x.sub.2, . . . , x.sub.M, each data stream in the M same-rate data streams having an ordered number of bits, each bit having a period of T.sub.sym; and a clock pulse signal including a plurality of pulses where a time duration of each pulse in the plurality of pulses corresponds to T.sub.sym/M; generating a number M of orthogonal pulse signals, each pulse signal in the M orthogonal pulse signals having an ordered number of pulses, from the clock pulse signal of the received data stream creating, from the data stream, an encoded data stream comprising an ordered number of bits, being generated by multiplying each data stream in the M same-rate data streams by a corresponding pulse signal in the ordered number M of orthogonal pulse signals to provide M results, summing the M results; and transmitting the encoded data stream.

2. The method of claim 1, where each pulse in each pulse signal in the M orthogonal pulse signals has a logical value of only 1 or +1.

3. The method of claim 2, where any pulse signal in the M of orthogonal pulse signals is orthogonal to any other pulse signal in the M of orthogonal pulse signals within a period of T.sub.sym.

4. The method of claim 3, where each bit in the encoded data stream is represented by the equation: $y\left(n\right)={.Math.}_{k=1}^M{x}_k\left(r\right)p_k\left(n\right),$ y(n) is the value of an encoded nth bit; x.sub.k(r) is the value of an unencoded rth bit in the kth data stream; x.sub.k(r)=x(Mr+k1); and p.sub.k(n) is the value of the nth pulse in the kth modulating pulse signal, and has a logical level of only 1 or +1 for each value of n.

5. The method of claim 4, further comprising: receiving the encoded data stream; extracting the M orthogonal pulse signals from the received encoded data stream; and decoding the unencoded rth bit within an rth symbol period of the M data streams, concurrently, through multiplying the received encoded data stream at the input of a decoder by the M orthogonal clock pulse signals, where a kth clock pulse signal corresponds to a kth data stream, k varying from 1 to M, and integrating the results over the rth symbol period such that $x_k\left(r\right)={}_{{\mathrm{rT}}_{\mathrm{sym}}}^{\left(r+1\right)T_{\mathrm{sym}}}z\left(t\right)p_k\left(t\right)\mathrm{dt},$ where z(t) denotes the received encoded data stream at the decoder's input.

6. The method of claim 5, where the received encoded data stream includes at least one encoded symbol, and where extracting the M orthogonal pulse signals comprises: generating the M orthogonal pulse signals on the receiver side; and aligning at least one of a rising or a falling edge of at least one pulse signal in the generated orthogonal pulse signals with the at least one rising or falling edge of the pulse signal embedded in the received encoded symbols within a predetermined reception period.

7. The method of claim 6, where M=2, and where the generated orthogonal pulse signals are designated, p.sub.1 and p.sub.2, and where each bit in the encoded data stream has a value given by the equation y(n)=x.sub.even(r)p.sub.1(n)+x.sub.odd(r)p.sub.2(n) where x.sub.even(r)=x(2r) and x.sub.odd(r)=x(2r+1) over one symbol period T.sub.sym.

8. The method of claim 7, further comprising: extracting the two orthogonal pulse signals, p.sub.1 and p.sub.2, from the received encoded data stream; and decoding the unencoded rth bit of x.sub.even by multiplying the received encoded data stream at the decoder's input by clock pulse signal p.sub.1, and concurrently decoding the unencoded rth bit of x.sub.odd by multiplying the received encoded data stream at the decoder's input by clock pulse signal p.sub.2, and integrating the results over the rth symbol period such that $x_{\mathrm{even}}\left(r\right)={}_{{\mathrm{rT}}_{\mathrm{sym}}}^{\left(r+1\right)T_{\mathrm{sym}}}z\left(t\right)p_1\left(t\right)\mathrm{dt}\mathrm{and}{x}_{\mathrm{odd}}\left(r\right)={}_{{\mathrm{rT}}_{\mathrm{sym}}}^{\left(r+1\right)T_{\mathrm{sym}}}z\left(t\right)p_2\left(t\right)\mathrm{dt},$ where z(t) denotes the received encoded data stream at the decoder's input; and outputting the decoded data streams x.sub.even and x.sub.odd to reproduce unencoded data stream x(n).

9. A method of encoding data comprising: receiving a digital data stream that includes a plurality of even and odd numbered bits, where the digital data stream has a bit period of one half the symbol period T.sub.sym; splitting the digital data stream into a first bit data stream and a second bit data stream, where the first bit data stream and the second bit data stream each has a bit period of one symbol period T.sub.sym, and where each bit in the first bit data stream and the second bit data stream has a voltage value of either zero or one; assigning a voltage value of 1 to each bit in the first bit data stream and the second bit data stream that has a voltage value of zero; generating a first periodic clock pulse signal and a second periodic clock pulse signal with alternating values of 1 and +1, each over one symbol period, and where the first periodic clock pulse signal with a period of 2T.sub.sym is orthogonal to the second periodic clock pulse signal with a period of 2T.sub.sym, within a symbol period T.sub.sym; multiplying the first bit data stream by the first modulating clock pulse signal creating a first product; multiplying the second bit data stream by the second modulating clock pulse signal creating a second product; summing the first and second product; to create an encoded data stream; and transmitting the encoded data stream.

10. The method of claim 9, further comprising: decoding the encoded data stream using an inverse operation to the encoding to create a decoded data stream; and outputting the decoded data stream.

11. The method of claim 10, further comprising extracting two orthogonal pulse signals from the received encoded data stream.

12. The method of claim 11, where the extracting of two orthogonal pulse signals comprises: generating two orthogonal pulse signals on the receiver side; and aligning at least one of a rising or falling edge of at least one pulse signal in the generated orthogonal pulse signals with the at least one rising or falling edge of the pulse signal embedded in the received encoded symbols within a predetermined reception period.

13. An apparatus for method for creating and transmitting an encoded data stream comprising: an encoder including demultiplexer circuitry to: receive an aggregate transmission of a data stream x(n), the data stream including: a number M of same-rate data streams, each data stream in the M same-rate data streams having an ordered number of bits; and a clock pulse signal including a plurality of pulses where each pulse in the plurality of pulses corresponds to one bit in the aggregated data stream; output the M data streams, each data stream in the M data streams having a data rate M times lower than that of the aggregated data stream; the encoder further including circuitry to generate, using the M data streams output by the demultiplexer, a high speed encoded data stream having an ordered number of bits being generated by multiplying a data stream in the ordered number M of same-rate data streams by a corresponding clock pulse signal in the ordered number M of orthogonal clock pulse signals to provide M results, and summing the M results; the encoder further including circuitry to transmit the encoded data stream.

14. The apparatus of claim 13, where each pulse of the clock pulse signals has a logical value of only 1 or +1.

15. The apparatus of claim 14, where any two modulating clock pulse signals are orthogonal to one another within a symbol period (T.sub.sym).

16. The apparatus of claim 15, where each bit in the encoded data stream is represented by the equation: $y\left(n\right)={.Math.}_{k=1}^M{x}_k\left(r\right)p_k\left(n\right),$ where y(n) is the value of an encoded nth bit; x.sub.k(r) is the value of an unencoded rth bit in the kth data stream; x.sub.k(r)=x(Mr+k1); and p.sub.k(n) is the value of the nth pulse in the kth modulating pulse signal, and has a logical level of only 1 or +1 for each value of n.

17. The apparatus of claim 16, where M=2, and where each bit in the encoded data stream has a value given by the equation y(n)=x.sub.even(r)p.sub.1(n)+x.sub.odd(r)p.sub.2(n), where x.sub.even(r)=x(2r) and x.sub.odd(r)=x(2r+1), and x.sub.even(r) is the value of the rth bit in a first data stream, and x.sub.odd(r) is the value of the rth bit in a second data stream.

18. An apparatus for decoding an encoded data stream comprising: decoder circuitry to: receive the encoded data stream, the encoded data stream comprising M orthogonal clock pulse signals p.sub.k, k varying from 1 to M; extract the M orthogonal clock pulse signals p.sub.k from the received encoded data stream; and decode an rth bit of the M data streams x.sub.1, x.sub.2, . . . , and x.sub.M, concurrently, performed by multiplying the received encoded data stream at the decoder's input, z(t), by p.sub.1, p.sub.2, . . . , and p.sub.M, respectively, and integrating the results over an rth symbol period T.sub.sym; $x_k\left(r\right)={}_{{\mathrm{rT}}_{\mathrm{sym}}}^{\left(r+1\right)T_{\mathrm{sym}}}z\left(t\right)p_k\left(t\right)\mathrm{dt}.$

19. The apparatus of claim 18, where said extracting the M orthogonal clock pulse signals comprises: generating M orthogonal clock pulse signals, each clock pulse signal having a rising edge and a falling edge; and aligning at least one of a rising or falling edge of at least one pulse signal in the generated M orthogonal pulse signals with at least one of a rising or falling edge of a pulse signal embedded in the received encoded symbols within a predetermined reception period.

20. The apparatus of claim 19, where M=2, and where the decoder includes circuitry to: extract the two orthogonal clock pulse signals, p.sub.1 and p.sub.2, from the received encoded data stream; and decode the rth bit of x.sub.even and x.sub.odd, concurrently, by multiplying the received encoded data stream at the decoder's input, z, by clock pulse signal p.sub.1, to detect x.sub.even, and p.sub.2, to detect x.sub.odd, and integrating the results over the rth symbol period T.sub.sym satisfying the equations $x_{\mathrm{even}}\left(r\right)={}_{{\mathrm{rT}}_{\mathrm{sym}}}^{\left(r+1\right)T_{\mathrm{sym}}}z\left(t\right)p_1\left(t\right)\mathrm{dt}\mathrm{and}$ $x_{\mathrm{odd}}\left(r\right)={}_{{\mathrm{rT}}_{\mathrm{sym}}}^{\left(r+1\right)T_{\mathrm{sym}}}z\left(t\right)p_2\left(t\right)\mathrm{dt},$ and output the decoded data streams x.sub.even and x.sub.odd to reproduce unencoded data stream x(n).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

[0017] FIG. 1 is a block diagram of certain components of a wireline transceiver.

[0018] FIG. 2 is a diagram of an example of known NRZ and an example of known PAM-4 signaling.

[0019] FIG. 3 is a high-level block diagram of a transceiver, according to an embodiment.

[0020] FIG. 4 is a graphical representation of the voltage levels of the transmitted stream, y(n), and how they change with each transition of clock pulse signals, p.sub.1 and p.sub.2, according to an embodiment.

[0021] FIG. 5 is a graphical representation of defined time points, according to an embodiment.

[0022] FIG. 6 is a graphical comparative representation of a bitstream comparing known PAM-4 encoding scheme to an embodiment of the invention for a certain value of bits.

[0023] FIG. 7 is a graphical comparative representation of the power spectrum of the proposed signaling scheme shown and compared with known signaling methods, according to an embodiment.

[0024] FIG. 8 is a detailed block diagram of the transmitter architecture, according to an embodiment.

[0025] FIG. 9 is a block diagram of decoder architecture, according to an embodiment.

[0026] FIG. 10 is a detailed block diagram of the entire receiver architecture, according to an embodiment.

[0027] FIG. 11 is a flow chart of a method for encrypting and decrypting a data stream, according to an embodiment.

DETAILED DESCRIPTION

[0028] As described above, systems and methods for a signaling scheme are disclosed that can be used in wired communication in a way that provides low-complexity and low-power realization of wired transceivers. Embodiments can enable the transmission of data at high rates while reducing the power consumption of wired transceivers and improving signal reception quality, particularly in terms of low sensitivity to noise and jitter.

[0029] Embodiments of the invention use clock pulse signals that are orthogonal within the time duration (period) of one unit of information (referred to as a symbol), T.sub.sym, for pulse amplitude modulation. In an embodiment, the incoming data stream, x, with a bit period of

[00001]$\frac{T_{\mathrm{sym}}}{M}$

is split into a number M of same-rate data streams, x.sub.k where k{1,2, . . . , M}, with a bit period of T.sub.sym. These M data streams are then multiplied by orthogonal clock pulse signals {p.sub.1, p.sub.2, . . . , p.sub.M}, and the resulting multiplied signals are then added to generate the encoded data stream y. The general equation for the complete encoded data stream can be represented by the following equation:

[00002]$\begin{array}{cc}y\left(t\right)={.Math.}_{k=1}^M{x}_k\left(t\right)p_k\left(t\right),& \left(\mathrm{Equation}\left(1\right)\right)\end{array}$ [0030] where t denotes time. Considering the discrete-values nature of the data streams x.sub.k, clock pulse signals p.sub.k, and the encoded data stream y, Equation (1) can be rewritten as the following equation:

[00003]$\begin{array}{cc}y\left(n\right)=\underset{k=1}{\overset{M}{.Math.}}{x}_k\left(r\right)p_k\left(n\right),& \left(\mathrm{Equation}\left(2\right)\right)\end{array}$$\begin{array}{ccc}n,r\left\{0,1,2,.Math.\right\},& k\left\{1,2,.Math.,M\right\},& r=.Math.\frac{n}{M}.Math.\end{array}$

[0031] In Equation (2), n denotes the bit number for the encoded data stream y and the pulse number for the orthogonal modulating clock pulse signals p.sub.k. Moreover, r represents the bit number for the data stream x.sub.k and is equal to the integer part of

[00004]$\left(\frac{n}{M}\right).$

y(n) is the value of the nth bit of the encoded data stream, p.sub.k(n) is the value of the nth pulse of the kth modulating clock pulse signal, and x.sub.k(r) is the value of the rth bit of the data stream x.sub.k which is equal to x(Mr+k1). The bit period of encoded data stream y and the time duration of each pulse for the orthogonal modulating clock pulse signals p.sub.k equal

[00005]$\frac{T_{\mathrm{sym}}}{M}.$

[0032] In Equation (1), the modulating clock pulse signals, denoted as p.sub.k, have logical levels 1 or +1 and are orthogonal within a symbol period (T.sub.sym), satisfying Equation (3), below.

[00006]$\begin{array}{cc}{}_{t_0}^{t_0+T_{\mathrm{sym}}}{p}_j\left(t\right)p_k\left(t\right)\mathrm{dt}=0,& \left(\mathrm{Equation}\left(3\right)\right)\end{array}$$j,k\left\{1,2,.Math.,M\right\},jk,p_k\left\{-1,+1\right\}$

[0033] Considering that Equation (2) is a linear sum of M signals x.sub.kp.sub.k, where p.sub.k and x.sub.k have logical levels 1 or +1, the output of this equation has M+1 voltage levels {M, M+2, M+4, . . . , M4, M2, M}. Due to the orthogonality of p.sub.1, p.sub.2, . . . , and p.sub.M, the data streams x.sub.1, x.sub.2, . . . , and x.sub.M can be concurrently decoded on the receiver side by multiplying the received signal by p.sub.1, p.sub.2, . . . , and p.sub.M, respectively, and integrating the result over one T.sub.sym.

[0034] The block diagram for a wired transceiver that implements the signaling of equation (2) is shown in FIG. 3. Within the encoder block 301, using a demultiplexer circuitry 305, the digital data x(n) with a bit period of T.sub.sym/M is divided into M data streams, {x.sub.1, x.sub.2, . . . , x.sub.M} each with a bit period of one T.sub.sym. The data streams {x.sub.1, x.sub.2, . . . , x.sub.M} are then multiplied, using a set of multipliers 306, by clock pulse signals {p.sub.1, p.sub.2, . . . , p.sub.M} which are orthogonal within one T.sub.sym (as shown in equation (3)). The resulting products are then summed, using an adder 307, to generate the encoded data stream y(n), as specified in Equation (2).

[0035] Within the decoder block 302, the data streams x.sub.1, x.sub.2, . . . , x.sub.M are concurrently obtained by multiplying the signal input to the decoder, z(t) which can also be represented by its discrete-value form z(n), by p.sub.1, p.sub.2, . . . , p.sub.M, respectively 308, integrating the results over one T.sub.sym 309, and passing the integrators' outputs through slicers 310, as represented by the following equation:

[00007]$\begin{array}{cc}{x}_k\left(r\right)={}_{{\mathrm{rT}}_{\mathrm{sym}}}^{\left(r+1\right)T_{\mathrm{sym}}}z\left(t\right)p_k\left(t\right)\mathrm{dt}& \left(\mathrm{Equation}\left(4\right)\right)\end{array}$$k\left\{1,2,.Math.,M\right\}$

This yields a throughput of M bits per one T.sub.sym considering that k varies from 1 to M in equation (4).

[0036] In the special case where M=2, the proposed signaling simplifies as follows

[00008]$\begin{array}{cc}y\left(n\right)=x_{\mathrm{even}}\left(r\right)p_1\left(n\right)+x_{\mathrm{odd}}\left(r\right)p_2\left(n\right)& \left(\mathrm{Equation}\left(5\right)\right)\end{array}$

[0037] Within the encoder block 303, using a demultiplexer 311, the digital data x(n) with a bit period of 0.5T.sub.sym is divided into two data streams, x.sub.even(r)=x(2r) and x.sub.odd(r)=x(2r+1), each with a bit period of one T.sub.sym. The data streams x.sub.even and x.sub.odd are then multiplied, using multipliers 312, by orthogonal clock pulse signals p.sub.1 and p.sub.2, and the resulting products are then summed, using an adder 313, to generate the encoded data stream y(n), which is given by Equation (5).

[0038] In Equation (5), the orthogonal modulating clock pulse signals p.sub.1 and p.sub.2, as well as the data streams x.sub.even and x.sub.odd, have logical levels 1 or +1. Thus, the data stream y(n) has three voltage levels, as depicted in FIG. 4. As shown in FIG. 4, the voltage levels of y(n) change with each transition of p.sub.1 and p.sub.2. In an embodiment, the transitions, which are independent of the data in y(n), enable a high-quality clock and data recovery (CDR) at the receiver. Thus, in an embodiment, a CDR can be implemented with lower structural complexity and better quality compared to CDRs for known methods PAM-4 and PAM-3.

[0039] In an embodiment, as can be seen in FIG. 4 at 401, each transmitted symbol has a footprint of a rising or falling edge of the clock pulse. At 402, a graphical representation of an embodiment is shown on the transmission side. In this example, the bit stream for x(n) is 0001001011, and a voltage value of 1 is assigned to each bit that has a voltage value of zero;

[0040] FIG. 5 is a representation of defined time points referred to as CDR lock points, according to an embodiment. These are the moments in time when the receiver's CDR (Clock and Data Recovery) must lock onto and extract the clock edges. As can be seen by the presence of such a footprint from the rising or falling clock edges (see the clock pulse signal p.sub.2 in FIG. 5) in each transmitted symbol at the receiver side, the receiver always has knowledge of the clock pulse's state, regardless of the transmitted data type or value.

[0041] One skilled in the art will appreciate that, in the proposed signaling method, good jitter tracking capability of the forwarded clock architecture is preserved with no need for an additional cable/wire interface, as the clock edges are embedded within the units of data. The presence of clock pulse in each transmitted symbol leads to improved efficiency and performance of clock and data recovery (CDR) circuits at the receiver.

[0042] As shown in FIG. 6, which is a graphical representation of the transmission of bitstream 0000000000 for NRZ (601), PAM-4 (602), and an embodiment of the proposed signaling method (603), in signaling systems such as NRZ and PAM signaling, the clock pulse is not necessarily present in every symbol, and the type and value of the transmitted data determine the presence or absence of the clock pulse edge in the transmitted symbol. For example, in unencoded/unscrambled NRZ signaling 601 or PAM-4 signaling 602, if the transmitter sends a constant data value for a period of time (e.g., 10T.sub.sym) such as sending the logical 0 value 10 times, the output voltage on the transmitter side remains constant during these 10T.sub.sym and does not change. Therefore, the receiver has no information about the transmitter's clock pulse during the interval for a period of 10T.sub.sym, and if a sudden change in the clock pulse edge occurs, the receiver cannot track such a sudden change, which can lead to errors at the receiver side. In an embodiment shown in 603, however, if the transmitter sends constant data for a certain period (e.g., sending the logical 0 value 10 times), a rising or falling edge of the clock pulse can be represented in each symbol. Such rising or falling edges of the clock pulse are indicated with dots (604). Therefore, the receiver can easily and efficiently track the clock pulse status on the transmitter's side and prepare itself for any sudden changes. As a result, the jitter tracking is enhanced on the receiver side and errors caused by jitter on the clock pulse edge are significantly reduced.

[0043] In an embodiment, shown in FIG. 3 at 304, the signals p.sub.1 and p.sub.2 are orthogonal in one symbol period, T.sub.sym; thus,

[00009]${}_{t_0}^{t_0+T_{\mathrm{sym}}}{p}_1{p}_2\mathrm{dt}=0.$

Exploiting this orthogonality, x.sub.odd and x.sub.even can be concurrently derived, within the decoder 304, by multiplying the received signal at the decoder's input by p.sub.2 and p.sub.1, respectively (314), integrating the results over one T.sub.sym (315), and passing the output signals through slicers (316). Thus, x.sub.even(r) and x.sub.odd(r) which are the values of two consecutive bits of the data stream x can be concurrently decoded within one T.sub.sym, and the presented signaling scheme provides a throughput of 2 bits/symbol.

[0044] FIG. 7 shows the power spectrum of the proposed signaling scheme (for M=2) compared with other signaling methods, each with a data rate of D, according to an embodiment. Taking the Nyquist frequency into account, disclosed embodiments may have relatively similar spectral efficiencies to, for example, PAM-3 (which is better than NRZ) while maintaining a throughput equal to PAM-4. Thus, compared to PAM-3, disclosed embodiments achieve higher throughput with relatively similar spectral efficiency. Compared to PAM-4, disclosed embodiments are less sensitive to Inter-Symbol Interference (ISI) and Data-Dependent Jitter, resulting in a better Signal-to-Noise Ratio (SNR). The primary reason for this improvement is the lower number of voltage levels that typically are required in the signal encoded pursuant to current embodiments as compared to signals encoded with PAM-4.

[0045] Furthermore, as evident from FIG. 7, within the Nyquist frequency range (indicated by circles 701), the decrease in the power of frequency components with increasing frequency in the proposed signaling (indicated by the arrow 702) is less pronounced compared to other signaling methods. Accordingly, in an embodiment, distortion of a signal transmitted through a telecommunication channel (that attenuates high frequencies) will be lower. As a result, the required equalization scheme at the receiver of the proposed signaling is less complex than other signaling methods.

[0046] One skilled in the art will further appreciate that, in comparison, for example, to the ENRZ signaling method, the proposed signaling also demonstrates a significantly lower sensitivity to inter-wire skew.

[0047] Without loss of generality, methods and architectures for implementing embodiments of the signaling with two modulating clock pulse signals are explained in the embodiments that follow. All the discussions and methods can be equally applied to a general case of using M orthogonal modulating clock pulse signals, as represented in FIG. 3. With regard to FIG. 3, within the encoder (303), the data streams x.sub.even and x.sub.odd are multiplied, respectively, by the clock pulse signals p.sub.1 and p.sub.2, and the resulting signals are then added. Considering the logical levels of these signals (which can be 1 or +1), the required multiplication operation can be simply realized by changing the polarity of x.sub.even and x.sub.odd on each rising/falling edge of p.sub.1 and p.sub.2. This polarity change can be achieved using standard multiplexers. In the block diagram of the proposed transmitter structure in FIG. 8, a 4-to-2 multiplexer (MUX.sub.1) 801 splits the input differential bitstream with an aggregate data rate of D=2/T.sub.sym into differential data streams x.sub.even and x.sub.odd with bit rates of D/2. These data streams are then multiplied by orthogonal clock pulse signals p.sub.1 and p.sub.2 using multiplexers MUX.sub.2 and MUX.sub.3 (802), respectively. The detailed implementation of these multiplexers is shown in 803. The outputs of MUX.sub.2 and MUX.sub.3 are fed into source series-terminated (SST) drivers 804 which provide a proper voltage swing at the transmitter's output. SST drivers' outputs are connected together by circuitry 805 which fulfills the required addition operation in Equation 5. In an embodiment, the required output matching is satisfied by circuitry 806 along with 805.

[0048] FIG. 9 illustrates a receiver decoder 901, according to an embodiment. In this structure, the input signal z enters a transconductance stage 902, denoted by G.sub.m0, which converts its input voltage signal into a current signal with a specific amplitude. This output current is switched by modulating clock pulse signal p.sub.1 (or p.sub.2), thus performing the required multiplying operation 903. The output signal of this multiplier is first fed into a switched-capacitor type integrator 904 and then into a slicer 905. With an appropriate timing for the switching pulses, as graphically represented in 906, the proposed decoder allows for multiplying the received encoded signal by p.sub.1 (or p.sub.2) and integrating the result on the capacitor C.sub.I over the time interval p.sub.integ (which, in an embodiment, has a 0.5T.sub.sym integration window).

[0049] In the utilized timing scheme, the output signal of the integrator is held on the capacitor C.sub.S for a duration of 0.25T.sub.sym, serving as a track & hold function. After each cycle of operation, the integrator and sampler are reset to clear the memory of capacitors C.sub.I and C.sub.S. The pulse widths of the control signals p.sub.integ, S, and R in (906), should be set to 0.5T.sub.sym, 0.25T.sub.sym, and 0.25T.sub.sym, respectively, for the system to operate properly.

[0050] A complete receiver architecture is presented in FIG. 10, according to an embodiment. The signal input to the receiver is first passed through a matching network 1001 and fed into a continuous-time linear equalizer (CTLE) 1002, which partially compensates for the channel response effects. The CTLE's output signal is then split into two different paths that enable decoding of x.sub.even and x.sub.odd data streams through the decoders 1003 discussed above. To mitigate the effects of intersymbol interference (ISI) caused by the channel, each path employs a Decision Feedback Equalizer (DFE) with a single tap 1004. The DFE within each path is realized by a transconductance stage, G.sub.m2, converting the recovered x.sub.even (or x.sub.odd) voltage signal to a current signal with a proper weight and feeding the current signal back to the input of the switched capacitor block for post-cursor removal. In the proposed configuration, the cross DFEs 1005 realized by transconductance stages G.sub.m1 are also considered to compensate for the interference effects of each path on the other path (i.e., cross-talk between x.sub.odd and x.sub.even) that is caused by the channel response and non-idealities on the receiver side (such as orthogonality mismatch between p.sub.1 and p.sub.2 and duty cycle distortion of p.sub.integ).

[0051] FIG. 11 is a flow chart of a method for encrypting and decrypting a data stream, according to an embodiment. At 1101, a data stream x(n) is received, the data stream comprising a number M of same-rate data streams. Each data stream in the M same-rate data streams has an ordered number of bits, each with a period of T.sub.sym which is M times larger than the bit period of x(n). The data stream received in 1101 also includes a clock pulse signal that is made up of a plurality of pulses, where each pulse in the plurality of pulses has a time duration (pulse width) of T.sub.sym/M.

[0052] At 1102, M clock pulse signals are generated from the clock pulse signal received in the received data stream, each clock pulse signal in the M clock pulse signals having a number of pulses. In an embodiment, each pulse in each clock pulse signal has a logical level of 1 or +1. In an embodiment, any two clock pulse signals are orthogonal to one another within a time duration of T.sub.sym.

[0053] At 1103, an encoded data stream is created by multiplying the value of the rth bit of each data stream in the ordered number M of same-rate data streams by the value of the nth pulse of a corresponding pulse signal in the ordered number M of orthogonal clock pulse signals and adding the M results. Once the encoding is done, the encoded data stream is transmitted at 1104. In an embodiment, each bit in the encoded data stream is represented by the equation

[00010]$y\left(n\right)={.Math.}_{k=1}^M{x}_k\left(r\right)p_k\left(n\right),$

where r, representing the bit number for x.sub.k which is kth data stream in the M same-rate data streams, is equal to the integer part of

[00011]$\left(\frac{n}{M}\right),$

and x.sub.k(r) is equal to x(Mr+k1). y(n) is the value of an encoded nth bit, x.sub.k(r) is the value of an unencoded rth bit in the x.sub.k data stream, and p.sub.k(n) is the value of the nth pulse in the kth modulating clock pulse signal in the M modulating clock pulse signals, and has a logical level of 1 or +1.

[0054] Once data is encoded and transmitted as an encoded data stream, it is received at a receiver at 1105 and is equalized to compensate for the loss of the wired link at 1106.

[0055] Subsequently, M orthogonal clock pulse signals are extracted from the equalized data at 1107. At 1108, the data streams x.sub.k, k varying from 1 to M, are decoded using the equation

[00012]$x_k\left(r\right)={}_{{\mathrm{rT}}_{\mathrm{sym}}}^{\left(r+1\right)T_{\mathrm{sym}}}z\left(t\right)p_k\left(t\right)\mathrm{dt}.$

Once the data streams x.sub.1, x.sub.2, . . . , and x.sub.M are decoded, the resulting data stream x(n) comprising these M decoded data streams, can be output at 1109.

[0056] Modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the disclosure. For example, the components of the systems and apparatuses may be integrated or separated. Moreover, the operations of the systems and apparatuses disclosed herein may be performed by more, fewer, or other components and the methods described may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. As used in this document, each refers to each member of a set or each member of a subset of a set.