DEVICES AND METHODS FOR ESTIMATING LOCALIZATION LENGTHS

Abstract

Devices and methods for estimating localization lengths in hybrid superconductor-semiconductor quantum (HSSQ) devices are described. A method for estimating localization lengths in an HSSQ device comprising a set of plunger gates formed in a first layer of the HSSQ device and a set of top gates formed, above the set of plunger gates, in a second layer of the HSSQ device, includes obtaining measurements of nonlocal conductance values associated with the HSSQ device. The at least one junction associated with the HSSQ device attenuates one or more of the measured nonlocal conductance values associated with the HSSQ device. The method further includes normalizing the measured nonlocal conductance values to remove an effect of the attenuation caused by the at least one junction and extracting localization lengths based on the normalized nonlocal conductance values. The method further includes, using a processor, estimating the localization lengths for the HSSQ device.

Claims

1. A method for estimating localization lengths in a hybrid superconductor-semiconductor quantum (HSSQ) device, wherein the HSSQ device comprises a set of plunger gates formed in a first layer of the HSSQ device and a set of top gates formed, above the set of plunger gates, in a second layer of the HSSQ device, the method comprising: obtaining measurements of nonlocal conductance values associated with the HSSQ device, wherein at least one junction associated with the HSSQ device attenuates one or more of the measured nonlocal conductance values associated with the HSSQ device; normalizing the measured nonlocal conductance values to remove an effect of the attenuation caused by the at least one junction and extracting localization lengths based on the normalized nonlocal conductance values associated with the HSSQ device; and using a processor, estimating the localization lengths for the HSSQ device by a joint prior distribution enforcing smoothness over a function of gate voltages and the extracted localization lengths for the HSSQ device.

2. The method of claim 1, wherein the normalizing the measured nonlocal conductance values to remove an effect of the attenuation caused by the at least one junction comprises normalizing each of the measured nonlocal conductance values by a square root of a product of respective local conductance values.

3. The method of claim 1, wherein the measurements of the nonlocal conductance values associated with the HSSQ device are obtained by measuring nonlocal conductance values of sections of a superconducting wire associated with the HSSQ device by selectively supplying voltages to one or more of the set of plunger gates and the set of top gates, respectively.

4. The method of claim 1, further comprising constructing a statistical model based on an implicit description of the measurements of the nonlocal conductance values.

5. The method of claim 4, wherein the statistical model comprises estimates of likelihood that are used to extract localization lengths at each of the gate voltages independently.

6. The method of claim 1, wherein the joint prior distribution is constructed by starting with independent local priors, in which a distribution over the extracted localization lengths is assumed to be a product of the independent local priors, and adding one or more of a set of constraints onto the joint prior distribution such that a rate of change of the function is restricted to a specified maximum value.

7. The method of claim 6, wherein the independent local priors include a marginal prior with respect to values of the extracted localization lengths, a smoothness prior with respect to correlation among the values of the extracted localization lengths, and a mean free path prior with respect to values of neighboring extracted localization lengths.

8. A method for estimating localization lengths in a hybrid superconductor-semiconductor quantum (HSSQ) device, wherein the HSSQ device comprises a set of plunger gates formed in a first layer of the HSSQ device and a set of top gates formed, above the set of plunger gates, in a second layer of the HSSQ device, the method comprising: measuring nonlocal conductance values of sections of a superconducting wire associated with the HSSQ device by selectively supplying voltages to one or more of the set of plunger gates and the set of top gates, respectively; normalizing the measured nonlocal conductance values to remove an effect of the attenuation caused by the at least one junction and extracting localization lengths based on the normalized nonlocal conductance values associated with the HSSQ device; and using a processor, estimating the localization lengths for the HSSQ device by a joint prior distribution enforcing smoothness over a function of gate voltages and the extracted localization lengths for the HSSQ device.

9. The method of claim 8, wherein the normalizing the measured nonlocal conductance values to remove an effect of the attenuation caused by the at least one junction comprises normalizing each of the measured nonlocal conductance values by a square root of a product of respective local conductance values.

10. The method of claim 8, further comprising constructing a statistical model based on an implicit description of the measurements of the nonlocal conductance values.

11. The method of claim 10, wherein the statistical model comprises estimates of likelihood that are used to extract localization lengths at each of the gate voltages independently.

12. The method of claim 8 wherein the joint prior distribution is constructed by starting with independent local priors, in which a distribution over the extracted localization lengths is assumed to be a product of the independent local priors, and adding one or more of a set of constraints onto the joint prior distribution such that a rate of change of the function is restricted to a specified maximum value.

13. The method of claim 12, wherein the independent local priors include a marginal prior with respect to values of the extracted localization lengths, a smoothness prior with respect to correlation among the values of the extracted localization lengths, and a mean free path prior with respect to values of neighboring extracted localization lengths.

14. A method for characterizing a level of disorder in a hybrid superconductor-semiconductor quantum (HSSQ) device, wherein the HSSQ device comprises a set of plunger gates formed in a first layer of the HSSQ device and a set of top gates formed, above the set of plunger gates, in a second layer of the HSSQ device, the method comprising: obtaining measurements of nonlocal conductance values associated with the HSSQ device, wherein at least one junction associated with the HSSQ device attenuates one or more of the measured nonlocal conductance values associated with the HSSQ device; normalizing the measured nonlocal conductance values to remove an effect of the attenuation caused by the at least one junction and extracting localization lengths based on the normalized nonlocal conductance values associated with the HSSQ device; using a processor, based on the extracted localization lengths, estimating the localization lengths for the HSSQ device; and using the processor, based on the estimated localization lengths, characterizing the level of disorder in the HSSQ device.

15. The method of claim 14, wherein the normalizing the measured nonlocal conductance values to remove an effect of the attenuation caused by the at least one junction comprises normalizing each of the measured nonlocal conductance values by a square root of a product of respective local conductance values.

16. The method of claim 14, wherein the measurements of the nonlocal conductance values associated with the HSSQ device are obtained by measuring nonlocal conductance values of sections of a superconducting wire associated with the HSSQ device by selectively supplying voltages to one or more of the set of plunger gates and the set of top gates, respectively.

17. The method of claim 14, wherein estimating the localization lengths for the HSSQ device comprises estimating by a joint prior distribution enforcing smoothness over a function of gate voltages and the normalized localization lengths for the HSSQ device.

18. The method of claim 17, further comprising constructing a statistical model based on an implicit description of the measurements of the nonlocal conductance values, and wherein the statistical model comprises estimates of likelihood that are used to extract localization lengths at each of the gate voltages independently.

19. The method of claim 17, wherein the joint prior distribution is constructed by starting with independent local priors, in which a distribution over the extracted localization lengths is assumed to be a product of the independent local priors, and adding one or more of a set of constraints onto the joint prior distribution such that a rate of change of the function is restricted to a specified maximum value.

20. The method of claim 19, wherein the independent local priors include a marginal prior with respect to values of the extracted localization lengths, a smoothness prior with respect to correlation among the values of the extracted localization lengths, and a mean free path prior with respect to values of neighboring extracted localization lengths.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present disclosure is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

[0013] FIG. 1 is a block diagram of a computing system for estimating localization lengths in hybrid superconductor-semiconductor quantum devices in accordance with one example;

[0014] FIG. 2 is a schematic diagram of an example hybrid superconductor-semiconductor quantum device with multiple gate-defined sections of different lengths for measuring nonlocal conductance values;

[0015] FIG. 3 shows plots of the measured nonlocal conductance values versus the plunger voltage and the bias voltage for different physical length segments in accordance with one example;

[0016] FIG. 4 is a graph of the extracted localization lengths as a function of the plunger voltage in accordance with one example;

[0017] FIG. 5 is a graph of extracted localization lengths and a graph of the log of the extracted localization lengths in accordance with one example;

[0018] FIG. 6 is a graph created with synthetic data to illustrate the effect of the mean path prior smoothing in accordance with one example;

[0019] FIG. 7 shows a graph illustrating the validation losses for log values of the constraint parameter used as part of the smoothing in accordance with one example;

[0020] FIG. 8 is a graph illustrating the estimated localization length using the Max a Posteriori (MAP) function versus the plunger voltage scan using a selected value for the constraint parameter in accordance with one example;

[0021] FIG. 9 is a flow chart of a method for estimating localization lengths in hybrid superconductor-semiconductor quantum devices in accordance with one example;

[0022] FIG. 10 is a graph comparing the smoothed and the validated localization lengths with the localization lengths obtained from a physics-based simulator in accordance with one example;

[0023] FIG. 11 is a graph comparing the localization lengths obtained using an independent Max a Posteriori (MAP) function (without the smoothing and validation) with the localization lengths obtained from a physics-based simulator in accordance with one example;

[0024] FIG. 12 is a flow chart of a method for characterizing a level of disorder in hybrid superconductor-semiconductor quantum devices in accordance with one example;

[0025] FIG. 13 is a diagram of another example hybrid superconductor-semiconductor quantum device with multiple junctions and gates for extracting localization lengths;

[0026] FIG. 14 is an expanded view of a section of the hybrid superconductor-semiconductor quantum device of FIG. 13;

[0027] FIG. 15 is a schematic diagram of a device layout of the hybrid superconductor-semiconductor quantum device of FIG. 13 with multiple gate-defined sections of different lengths (L.sub.1, L.sub.2, L.sub.3, L.sub.4, and L.sub.5) for measuring nonlocal conductance values;

[0028] FIG. 16 is a cross-section view of a portion along a junction associated with the hybrid superconductor-semiconductor quantum device of FIG. 13;

[0029] FIG. 17 is a flow chart of a method for estimating localization lengths in using the hybrid superconductor-semiconductor quantum (HSSQ) device of FIG. 13 in accordance with one example;

[0030] FIG. 18 is a graph illustrating the scaling of the normalized nonlocal conductance for specific values of the local conductance in view of the different lengths of the superconducting wire in accordance with one example;

[0031] FIG. 19 is a graph illustrating the scaling of the normalized nonlocal conductance for specific values of the local conductance in view of the different lengths of the superconducting wire in accordance with one example; and

[0032] FIG. 20 is a flow chart of a method for characterizing a level of disorder in the HSSQ device of FIG. 13 in accordance with one example.

DETAILED DESCRIPTION

[0033] Examples of the present disclosure relate to devices, methods, and systems for estimating localization lengths in hybrid superconductor-semiconductor quantum devices. As noted earlier, hybrid superconductor-semiconductor quantum devices with superconducting wires can have segments with one of two phases: a trivial phase or a topological phase. Such topological hybrid superconductor-semiconductor quantum devices are optimized to produce a large topological gap. To achieve the large topological gap, the semiconductor stack in such devices needs to produce a large spin-orbit coupling in the confined two-dimensional gas (2DEG). Disorder in the bulk of such superconducting wires suppresses the topological gap and increases the coherence length. This, in turn, leads to a minimum length requirement for the superconducting wire to perform well as a part of a qubit that depends on the composition/geometry of the stack of layers used to form the wire and the disorder level.

[0034] In such quantum devices, localization length (LL) is a parameter that determines the statistical dependence of conductance on the length of the device. In principle, the measurement of the conductance for a set of device lengths should enable estimation of the LL. In practice, the measurements of conductance are corrupted by noise. The devices and methods described herein can be used for accurately estimating localization lengths in hybrid superconductor-semiconductor quantum devices.

[0035] FIG. 1 is a block diagram of a computing system 100 for estimating localization lengths in hybrid superconductor-semiconductor quantum devices in accordance with one example. Computing system 100 includes a processor 110, a memory 120, input/output devices 140, display 150, and network interfaces 160 interconnected via bus system 102. Memory 120 may include measurement and interface code 122, data 124 (including measurement data, synthetic data, or other types of data used as part of the methods described herein), and calculation code 126. Measurement and interface code 122 may include program instructions that, when executed by processor 110, allow computing system 100 to enable the performance of the methods described herein, including the various aspects of the methods described with respect to FIGS. 2-12. In addition, measurement and interface code 122 may include libraries or other code for allowing processor 110 to display relevant information on display 150. Measurement and interface code 122 may also allow input/output devices 140 to receive or transmit information associated with the methods described herein. As an example, computing system 100 may access data concerning hybrid superconductor-semiconductor quantum devices via input/output devices 140 with the help of the execution of the measurement and interface code 122. Measurement and interface code 122 may also operate in conjunction with an experimental set up to allow a user to control the various knobs (e.g., plunger voltage or other voltages) associated with the measurement of the local conductance values.

[0036] Calculation code 126 may include instructions for executing steps described with respect to the various methods described herein. As an example, calculation code 126 may include software libraries and other code for extracting localization lengths, estimating the localization lengths, including smoothing, and cross-validating as described later. Although FIG. 1 shows a certain number of components of computing system 100 arranged in a certain way, additional or fewer components arranged differently may also be used. In addition, although memory 120 shows certain blocks of code, the functionality provided by this code may be combined or distributed. In addition, the various blocks of code may be stored in non-transitory computer-readable media, such as non-volatile media and/or volatile media. Non-volatile media include, for example, a hard disk, a solid state drive, a magnetic disk or tape, an optical disk or tape, a flash memory, an EPROM, NVRAM, PRAM, or other such media, or networked versions of such media. Volatile media include, for example, dynamic memory, such as DRAM, SRAM, a cache, or other such media.

[0037] FIG. 2 is a diagram of a device layout 210 of a hybrid superconductor-semiconductor quantum device with multiple gate-defined sections of different lengths for measuring nonlocal conductance values. FIG. 2 further shows a measurement configuration 250 to measure conductance of one of the sections of different lengths. Device layout 210 shows parent superconductor 212 under both plunger gates 232, 234, 236, and 238 and junction gates 242, 244, 246, and 248. Parent superconductor 212 is coupled to a parent superconductor contact 222. Device layout 210 shows three gate-defined sections with lengths of L.sub.1, L.sub.2, and L.sub.3. The superconductor is underneath plunger gates and junction gates. Sources (S1, S2, S3, and S4) are configured to contact the semiconductor quantum well via contacts 214, 216, 218, and 220. Coupling to parent superconductor 212 is controlled by junction gates 242, 244, 246, and 248. Device layout 210 corresponds to a physical representation of the hybrid superconductor-semiconductor quantum device. The physical representation of the hybrid superconductor-semiconductor quantum device may be a device under test or any other device formed on a single integrated circuit using semiconductor/superconductor fabrication techniques.

[0038] The measurement configuration 250 is configured to measure conductance of a single section. The junction gates for the section under measurement are set to a positive voltage to contact the semiconductor. For this device layout 210, by measuring the conductance values between sources S3 and S4, the conductance values for one length of the wire (e.g., L=1 m) are obtained. The plunger gate of this section will be varied during the measurement and all other gates are set to highly negative voltages to deplete all unwanted semiconductor states. The nonlocal conductance is then measured with the nanowire (the superconductor) grounded. This measurement is then repeated for all sections of the nanowire. As an example, by measuring the conductance values between sources S2 and S3, the conductance values for another length of the wire (e.g., L=2 m) are obtained. Similarly, by measuring the conductance values between sources S2 and S4, the conductance values for another length of the wire (e.g., L=3.5 m) are obtained. By measuring the conductance values between sources S1 and S3, the conductance for another length of the wire (e.g., L=6.5 m) are obtained. Finally, by measuring the conductance values between sources S1 and S4, the conductance values for another length of the wire (e.g., L=8 m) are obtained.

[0039] The plunger gates and the junction gates described herein may be supplied voltages via voltage waveforms generated by a control system (not shown) associated with the hybrid superconductor-semiconductor quantum device. Such a control system may include oscillators, switches, finite state machines, and a memory. As an example, the memory may be implemented as one or more multi-bit registers for allowing scan-patterns and pulse-patterns to be stored. Although FIG. 2 shows a certain device layout 210 and a corresponding measurement configuration 250, other device layouts and measurement configurations can also be used to measure nonlocal conductance values. In addition, although FIG. 2 describes the measurement of the conductance values for wires with lengths between 1 m to 8 m, the measurement of conductance values for devices having other layouts with different physical length wire-sections can also be performed.

[0040] FIG. 3 shows plots 300 of the measured nonlocal conductance values versus the plunger voltage and the bias voltage for different physical length segments in accordance with one example. Hybrid superconductor-semiconductor quantum devices can be implemented using superconductor-semiconductor nanowires with a sufficiently long localization length, as required for a topological phase. Plots 300 are derived from the experimental hybrid mobility device (device layout shown in FIG. 2) which can be viewed as a variation of a hybrid superconductor-semiconductor quantum device that has multiple segments of different lengths. Using the experimental hybrid mobility device, one can measure the nonlocal conductance (G.sub.RL) for different physical lengths (L), and then extract the electron localization length (l.sub.loc) in the semiconductor. Plots 300 show the experimentally measured nonlocal conductance across sections of lengths L=1 m, 2 m, 3 m, 4 m, 6 m, and 8 m in the same wire versus the plunger voltage (V.sub.plunger [V]) and the bias voltage (V.sub.bias [mV]) for the different length values. At around V.sub.plunger=1.185 V, the nonlocal conductance of the 1 m wire becomes larger than 0.05 e.sup.2/h. The onset of nonlocal conductance appearing around this gate voltage (V.sub.plunger=1.185 V) for multiple wire lengths suggests that this signifies the onset of the first sub-band (indicated by the dotted line in FIG. 3). These lengths are chosen as examples in this measurement and are not intended to limit the application of the systems and methods described herein to devices with different wire lengths.

[0041] FIG. 4 is a graph 400 of the extracted localization lengths (l.sub.loc) as a function of the plunger voltage (V.sub.plunger). The localization lengths are extracted by averaging the nonlocal conductance over a small bias window (e.g., 20 eV). The localization length is then extracted by fitting the data to the expected value of the typical conductance ((G.sub.RL/G.sub.RRG.sub.LL)=A exp(2 L/l.sub.loc)), where G.sub.RR and G.sub.LL are the local conductance values, and it is assumed that the nonlocal conductance decays with the increase in length L.

[0042] In certain devices, the junctions can attenuate the nonlocal conductance signal, which complicates the relationship between the extracted localization lengths and the nonlocal conductance. The complication arises from the fact that the part of nonlocal conductance signal is affected not only by the disorder in the transport in the semiconductor nanowire, but also by the attenuation caused by the junction itself. The attenuation caused by the junction itself has a random component to it. To remove the effect of the junction attenuation, in one example, the nonlocal conductance signal is normalized by the square root of the product of the local conductance values (N=G.sub.RRG.sub.LL). The attenuation of the signal due to the junctions is equal to the attenuation of the nonlocal conductance. By defining a new quantity B=G.sub.nonlocal/N, which is invariant to changes in the junction transparency, the localization lengths can be estimated as described further. The normalization may be performed selectively depending upon whether the junction is open or closed. This is because the effect of the attenuation caused by the junction varies depending upon whether the junction is closed or open. Broadly speaking, the opening of a junction reduces the attenuation caused by the junction, whereas the closing of the junction increases the attenuation caused by the junction. Thus, in one example, the normalization may be performed when the measurements are being performed with a closed junction, but no normalization may be performed when the measurements are being performed with an open junction.

[0043] With continued reference to FIG. 4, the fit parameters can be obtained by linear fit of ln(G.sub.RL) vs. L with R.sup.2 describing the quality of the fit. Graph 400 shows the extracted localization lengths (l.sub.loc) as a function of the plunger voltage (V.sub.plunger) with the quality of the fit R.sup.2 on the right side of graph 400. Alternatively, as part of generating graph 400, during fitting the data to the expected value of the conductance, conductance ((G.sub.RL)=A exp(2 L/l.sub.loc)) can also be used.

[0044] As shown in graph 400 of FIG. 4, the extracted localization lengths (l.sub.loc) have a high variance. This variance can be explained, in part, by the statistical error caused by the small set of observations (device lengths L) available at each of the plunger voltage (V.sub.plunger) values. In addition, some of this variance may be since the signal is exponentially suppressed in L because for long devices, the estimated localization length (l.sub.loc, which is also referred to as l in the equations described further) is dominated by noise. Thus, in one example, the measured conductance can be modeled as y=e.sup.+, where is represented as

[00001]$\left(\frac{-2L}{l},\frac{4L}{l}\right)$

and is represented as (0, .sup.2). FIG. 5 shows a graph 510 of extracted localization lengths and a graph 520 of log of the extracted localization lengths.

[0045] The measurement of the nonlocal conductance for different device lengths should enable the estimation of the localization length (LL). In practice, the measurements of the nonlocal conductance are corrupted by noise. To address these limitations, the statistical model specifying the relation of the measured nonlocal conductance values and the device lengths is provided implicitly (e.g., as a stochastic generative model). For many types of statistical estimation (e.g., maximum likelihood and Bayesian), one needs access to the likelihood function. In this case, however, there is no functional form available for the likelihood approach.

[0046] To address this issue, an algorithm based on numerical integration to compute high-precision estimates of the likelihood is used. Models of the hybrid superconductor-semiconductor quantum device in both the open and closed regimes, with the difference between the two cases predicated on differences in the generative models, are described. For the open regime, the true device conductance is modelled as a log-normal variate whose underlying mean and variance parameters vary linearly in device length at a rate inverse to the localization length. While in the closed regime, an additional step of multiplication by a random phase factor is hypothesized. In both cases, Gaussian measurement noise is added to the true conductance during measurement.

[0047] As described above, the likelihood alone can be used to extract the localization length at each device gate setting independently, by finding the values that maximize the log likelihood. While this approach, with the measured conductance model described earlier, provides useful information quite rapidly, it still yields estimates with some imprecision. This is because the number of device lengths with which to perform measurements is small and it still impacts the likelihood-based extraction of localization lengths. To address this issue, the present disclosure further describes a joint prior distribution over the localization lengths. As part of the equations with respect to the description related to the smoothing of the extracted localization length, the localization length is abbreviated as l (lowercase L).

[0048] To mitigate the issue of the large parameter variance when performing independent localization length estimation, a prior distribution enforcing uniform smoothness over the gate voltage vs the localization length function is described. In conjunction with the likelihood computation described earlier, a Bayesian Max a Posteriori (MAP) estimate is used to recover the localization lengths with improved accuracy. In one example, the prior distribution enforcing uniform smoothness over the gate voltage vs the localization length function is derived from two types of local prior knowledge concerning the extracted localization length estimates. The local prior knowledge includes bounds on the parameter values and relates to the prior marginal density whose shape represents prior knowledge. In one example, the joint prior distribution relates to the knowledge that the localization length varies smoothly with the change in the plunger voltage (V.sub.plunger) values. The joint prior knowledge also has a structural assumption that assumes that the smoothing level is a bias-variance tradeoff.

[0049] The joint prior distribution is constructed by starting with the independent prior, in which the distribution over localization lengths is assumed to be a product over the marginal localization length priors and adding a set of absolute value constraints onto the joint prior support such that the rate of change, or a second derivative of the function, is restricted to some specifiable maximum value. Each absolute value constraint is translated into two linear inequality constraints, and for a given level of smoothing, the Bayesian Max a Posteriori (MAP) estimate is obtained using a constrained optimization algorithm.

[0050] Table 1 below summarizes the Bayesian method and the MAP estimation.

TABLE-US-00001 TABLE 1 Prior (l, .sup.2) = (l)(.sup.2), Likelihood f(y|l, ) = .sub.i=1.sup.K(y.sub.i|l.sub.i, .sub.i.sup.2 Bayesian inference Posterior density: (l, .sup.2|y) (l, .sup.2)f(y|l, ) Posterior mean: [l, .sup.2|y] Max a Posteriori (MAP): arg max.sub.l,.sub.2 log(l, .sup.2) + logf(y|l, )

[0051] The goal of the Bayesian method shown in Table 1 is to infer the localization length and the noise variance, which are assumed to be independent of each other. In other words, the priors for the two together can be expressed with the product of the two individually. The posterior density in Table 1 is proportional to this product. Moreover, the distributions for both the localization length and the noise are assumed to be high dimensional because for every one of the plunger voltage values there are extracted localization length values, which relate to the dimension of the problem. To obtain the likelihood of a prior, one can either take the posterior mean estimation (shown in Table 1 above) or take the Max a Posteriori (MAP) estimation (also shown in Table 1 above).

[0052] One example of a derivation of likelihood that can be used as part of the Bayesian method of Table 1 is shown in Table 2 below. The integral shown in equation 1 (Eq. 1) below can be computed using the numerical quadrature integration methods.

TABLE-US-00002 TABLE 2 [00002]$\begin{array}{cc}\left(yl,{}^2,L,V\right)=\frac{1}{4}\sqrt{\frac{l}{L{}^2}}{}_{}^{}{e}^{h\left(y,t\right)}\mathrm{dt}& \left(\mathrm{Eq}.1\right)\end{array}$ [00003]$\begin{array}{cc}h\left(y,t\right)=-\frac{1}{2{}^2}{\left(\exp \left(t\right)-y\right)}^2-\frac{l}{8L}{\left(t+\frac{2L}{l}\right)}^2& \left(\mathrm{Eq}.2\right)\end{array}$

[0053] Numerical computation of the log likelihood requires numerical integration at each observed data point (conductance). When performing Bayesian MAP estimation, these integrations must be performed at each step in the optimization routine maximizing the posterior log probability. While this is reasonable in some cases, for example the open regime model, it can become prohibitively expensive for the closed regime where the log likelihood involves double integration. To mitigate this issue, an interpolation table of log likelihood values is computed offline for an experimental setting of interest (e.g., the range of device lengths, and the hypothesized ranges of localization length and noise variance). The table of log likelihoods is computed using the expensive numerical integration methods, but once completed it can be used to produce fast and accurate estimates of the log likelihood of an observation at any parameter setting using, for example, cubic or quintic interpolation. As an example, the computed table of log likelihoods can be stored in memory 120 of computing system 100 of FIG. 1 described earlier. Calculation code 126 can be modified to use the cubic or quintic interpolation instead of the more expensive numerical integration methods. Advantageously, when used in the localization length MAP routine, this strategy can accelerate the estimation by many orders of magnitude over the direct computation of the integrals shown in Eq. 1 of Table 2 above.

[0054] As explained earlier, the prior distribution enforcing uniform smoothness over the gate voltage vs the localization length function is derived from two types of local prior knowledge concerning the extracted localization length estimates. The first type of local prior knowledge relates to the bounds on the parameter values. Table 3 below shows one example of applying a marginal prior, which relates to the fact that the localization length for every one of the parameters being estimated is the same.

TABLE-US-00003 TABLE 3 Assume for all i, .sub.i(l.sub.i) = p(l.sub.i) [00004]${}_i\left({}_i^2\right)=q\left({}_i^2\right)$ Log-uniform (or reciprocal) prior: logl.sub.i~ [a, b] or equivalently: [00005]$p\left(l_i\right)\frac{1}{l_i}\mathrm{for}{l}_i\left[e^a,e^b\right]$ Independent MAP estimates: [00006]${\stackrel{}{l}}_i,{\stackrel{}{}}_i^2=\arg {\max }_{l_i,{}_i^2}\log p\left(l_i\right)+\log q\left({}_i^2\right)+\log f\left(y_i|l_i,{}_i^2\right)$

[0055] In addition to the marginal prior described above with respect to Table 3, one can also apply a smoothness prior on the localization length, as shown below in Table 4.

TABLE-US-00004 TABLE 4 Stationary model: (l.sub.i) = .sub.l.sub.i dl.sub.i = p(l.sub.i) However, the lengths are correlated: (l) .sub.i p(l.sub.i)

[0056] Despite using a marginal prior that relates to the fact that the localization length for every one of the parameters being estimated is the same value (e.g., Table 3) and using the smoothness prior (e.g., Table 4) described earlier, the localization length estimates can still be improved by the application of the mean free path prior.

[0057] Table 5 shows various aspects associated with the application of the mean free path prior.

TABLE-US-00005 TABLE 5 Mean free path prior: [00007]$\left(l\right)\underset{i}{.Math.}p\left(l_i\right)\mathrm{subject}\mathrm{to}$ l.sub.i [s, t] |l.sub.i+1 2l.sub.i + l.sub.i1| c.sub.2(Eq. 1) Smoothness over log localization lengths can also be enforced using the following prior: |logl.sub.i+1 2logl.sub.i + logl.sub.i1| c.sub.2

[0058] The mean free path prior described in Table 5 is based on the observation that if one evaluates any two neighboring localization lengths with respect to the plunger voltage scan (described earlier), and if one compares the localization length (l.sub.i) for the i.sup.th point, the localization length (l.sub.i+1) for the (i+1).sup.th point, and the localization length (l.sub.i1) for the (i1).sup.th point, and then calculates an absolute value of the linear function (Eq. 1 of Table 5), then that absolute value has to be less than or equal to a specified value for the parameter c.sub.2 in Table 5. In other words, the argument of the absolute value constraints an approximation to the second derivative. The mean free path prior can also be viewed as providing a constraint imposed by a convex polytope. The effect of the mean free path prior is similar to a smoothing spline function, but stronger. The constraints described above with respect to Table 5 impose a uniform bound on the smoothness of the localization length estimates. A larger value for the parameter c.sub.2 implies less smoothing. For a given value of the parameter c.sub.2, one can solve the full Max a Posteriori (MAP) problem using a constrained optimization software.

[0059] While the maximum likelihood estimation of localization lengths has certain advantages over the exponential fitting method, the localization length estimates are still noisy. Advantageously, the use of the priors over the likelihood not only allows one to calculate the parameter estimates in isolation, and in a different way, but also lets one use different priors to get better localization length estimates.

[0060] FIG. 6 is a graph 600 created with synthetic data to illustrate the effect of the mean path prior smoothing. The synthetic data relates to localization lengths versus the plunger voltage using log normal data with added noise. The various curves in graph 600 are then generated by applying the Max a Posteriori (MAP) function with the priors discussed earlier, including the mean free path prior with different values for the parameter c.sub.2. Graph 600 shows that smaller values for the parameter c.sub.2 result in more smoothing. In other words, as one starts to make the parameter c.sub.2 progressively smaller, imposing higher smoothness, the estimated localization lengths begin to look like a quadratic function of the plunger voltage (V.sub.plunger) values.

[0061] In one example, the value of the parameter c.sub.2 described with respect to the mean free path prior can be selected using 2-fold cross-validation, as shown in Table 6 below. The appropriate level of smoothing is automatically determined by cross-validation. In other words, for any smoothing level, a subset of the data is used to estimate the localization lengths, while a complementary subset is used to check the fit, and the smoothing level yielding the best validation fit is selected. Table 6 shows an example of the 2-fold cross-validation process using an even set of data comprising even values of the estimated localization lengths and an odd set of data comprising odd values of the estimated localization lengths. The validation loss is defined as the average of the losses from the two complementary sets of data (the even set of data and the odd set of data).

TABLE-US-00006 TABLE 6 Cross-validation .sub.e = {(y.sub.ij, V.sub.i)|i S.sub.e} .sub.o = {(y.sub.ij, V.sub.i)|i S.sub.o} [00008]${\hat{l}}_e,{\stackrel{}{}}_e^2=\arg {\max }_{l,{}^2}\left[\log f\left(l,{}^2.Math.{𝒟}_e,c_2\right)\right]$ [00009]${\hat{l}}_o,{\stackrel{}{}}_o^2=\arg {\max }_{l,{}^2}\left[\log f\left(l,{}^2.Math.{𝒟}_o,c_2\right)\right]$ Validation loss: [00010]${}^{val}=\frac{{}^{va{l}_o}+{}^{va{l}_e}}{2}$

[0062] The validation losses can be calculated by performing the localization length estimation for different log values of the parameter c.sub.2 using the even data alone and then performing the localization length estimation for different log values of the parameter c.sub.2 using the odd data alone. FIG. 7 shows a graph 700 illustrating the validation losses for log values of the constraint parameter (c.sub.2) for even data alone and for odd data alone. Curve 710 formed by the series of dots shows the average validation loss. The parameter value c.sub.2 that results in the minimum average validation loss is selected for use with the mean free path prior described earlier.

[0063] FIG. 8 is a graph 800 illustrating the estimated localization length using the Max a Posteriori (MAP) function versus the plunger voltage scan using the selected parameter value c.sub.2. As shown in graph 800, the localization lengths extracted with the Max a Posteriori (MAP) function with the priors, including the mean free path prior with the selected parameter value c.sub.2, produces highly accurate estimated localization lengths as a function of the plunger voltage (V.sub.plunger) values.

[0064] FIG. 9 is a flow chart 900 of a method for estimating localization lengths in hybrid superconductor-semiconductor quantum devices in accordance with one example. The steps associated with this method may be performed using instructions (e.g., the various code blocks) stored in memory 120 of computing system 100 of FIG. 1. Step 910 includes constructing a statistical model for extracting localization lengths based on an implicit description of measurements associated with a physical representation of the hybrid superconductor-semiconductor quantum device. FIGS. 2-4, and the related description, provide additional details for obtaining measured nonlocal conductance values and then using these obtained values to construct a statistical model for the extracted localization lengths. As explained earlier, in one example, the measurements associated with the physical representation of the hybrid superconductor-semiconductor quantum device comprise physical measurements of conductance for a set of device lengths. Other techniques can also be used to construct a statistical model for extracting localization lengths based on an implicit description of the measurements associated with a physical representation of the hybrid superconductor-semiconductor quantum device.

[0065] Step 920 includes estimating the localization lengths in the hybrid superconductor-semiconductor quantum device by a joint prior distribution enforcing uniform smoothness over a function of gate voltages and extracted localization lengths for the hybrid superconductor-semiconductor quantum device. As explained earlier, the joint prior distribution is constructed by starting with independent local priors, in which a distribution over the localization lengths is assumed to be a product of the independent local priors, and adding one or more of a set of constraints onto the joint prior distribution such that a rate of change of the function is restricted to a specified maximum value. As explained earlier the appropriate level of the uniform smoothness may be determined by cross-validating complementary subsets of data (e.g., even vs. odd localization lengths) related to the extracted localization lengths.

[0066] FIG. 10 is a graph 1000 comparing the smoothed and the validated localization lengths with the localization lengths obtained from a physics-based simulator. Envelope 1010 relates to a factor 2 uncertainty. Curve 1020 shows the localization lengths derived from the physics-based simulator. Curve 1030 shows the smoothed and the validated localization lengths obtained using the methods described herein.

[0067] FIG. 11 is a graph 1100 comparing the localization lengths obtained using an independent Max a Posteriori (MAP) function (without the smoothing and validation) with the localization lengths obtained from a physics-based simulator. Envelop 1110 relates to a factor 2 uncertainty. Curve 1120 shows the localization lengths derived from the physics-based simulator. The uneven distribution 1130 corresponds to the localization lengths obtained using an independent Max a Posteriori (MAP) function (without the smoothing and validation). As shown in FIG. 11, the localization length estimates obtained without the smoothing and validation compare poorly with the localization lengths derived from the physics-based simulator. Notably, the localization lengths obtained using the Max a Posteriori (MAP) function (without the smoothing and validation) are not smooth and are different from the localization lengths derived from the physics-based simulator.

[0068] FIG. 12 is a flow chart 1200 of a method for characterizing a level of disorder in hybrid superconductor-semiconductor quantum devices in accordance with one example. The steps associated with this method may be performed using instructions (e.g., the various code blocks) stored in memory 120 of computing system 100 of FIG. 1. Step 1210 includes constructing a statistical model for extracting localization lengths based on an implicit description of measurements associated with a physical representation of the hybrid superconductor-semiconductor quantum device. FIGS. 2-4, and the related description, provide additional details for obtaining measured nonlocal conductance values and then using these obtained values to construct a statistical model for the extracted localization lengths. As explained earlier, in one example, the measurements associated with the physical representation of the hybrid superconductor-semiconductor quantum device comprise physical measurements of conductance for a set of device lengths. Other techniques can also be used to construct a statistical model for extracting localization lengths based on an implicit description of the measurements associated with a physical representation of the hybrid superconductor-semiconductor quantum device.

[0069] Step 1220 includes estimating the localization lengths in the hybrid superconductor-semiconductor quantum device by a joint prior distribution enforcing smoothness over a function of gate voltages and localization lengths for the hybrid superconductor-semiconductor quantum device. As explained earlier, the joint prior distribution is constructed by starting with independent local priors, in which a distribution over the localization lengths is assumed to be a product of the independent local priors, and adding one or more of a set of constraints onto the joint prior distribution such that a rate of change of the function is restricted to a specified maximum value. As explained earlier the appropriate level of the uniform smoothness may be determined by cross-validating complementary subsets of data (e.g., even vs. odd localization lengths) related to the extracted localization lengths.

[0070] Step 1230 comprises characterizing a level of disorder in the hybrid superconductor-semiconductor quantum device using the estimated localization lengths. As noted earlier, the disorder in the bulk of superconducting wires associated with the hybrid superconductor-semiconductor quantum devices suppresses the topological gap and increases the coherence length. This, in turn, leads to a minimum length requirement for the superconducting wire to perform well as a part of a qubit that depends on the composition/geometry of the stack of layers used to form the wire and the disorder level. In the topological phase, the coherence length corresponds to the localization length of a Majorana zero mode (MZM). In the topological phase, when the disorder is very weak, the localization length approaches the localization length of a perfectly clean system, which has no states below the clean topological gap, apart from the MZMs. Increased disorder elongates the localization length in the topological phase and shortens it in the trivial phase. In sum, the estimated localization lengths derived from step 1220 can be used to characterize the level of disorder in the hybrid superconductor-semiconductor quantum device. As an example, calculation code 126 stored in memory 120 of computing system 100 may be used to characterize the level of disorder based on the estimated localization lengths.

[0071] For the device layout 210 of FIG. 2, the junctions are optimized to be as transparent as possible, such that the role that they play in the transport of electrons is predictable. This allows one to assume that all (or most) of the variation in the nonlocal conductance values for such devices is due to the disorder in the wire. However, in some stack designs, operating the junctions in this regime leads to a reduction in the fidelity of the methods used for estimating localization lengths. One such complication is a very large local conductance, which makes the method more susceptible to measurement uncertainties. In addition, devices and methods are required that can be operated with the junctions in either the open regime or in a tunneling regime. As an example, methods for estimating localization lengths using devices with a layout and operation similar to devices with MZM qubits are described.

[0072] MZM qubits require rapidly configuring couplings between different pairs of MZMs for qubit operations and measurement. As used herein, the term qubit refers to any quantum system that can be in a superposition of two quantum states, 0 and 1. Conventionally, such coupling paths have been controlled by electrostatic gates that apply a voltage pulse to change the junction between MZMs from a tunneling configuration to a fully pinched-off configuration. Such gates may generally cover a small area and may thus have small lever arms to the semiconducting region underneath. As a result, these voltage pulses can require large amplitudes. Applying fast voltage swings having large amplitudes complicates control of the qubit and leads to an increase in the qubit temperature, resulting in a larger qubit error probability. This is because error processes in MZM qubits are exponentially suppressed in the energy scales of the topological gap and charging energy E.sub.C over the temperature T.

[0073] To address such issues, certain qubit devices use smaller junctions with chains of quantum dots so that the couplings between MZMs can be controlled by the detuning of the quantum dots from their resonance point with the qubit island. The detuning of the quantum dot can be controlled by changing the voltage applied to plunger gates associated with the quantum dots without changing any voltages associated with the cutter gates. Since tuning the quantum dot on-resonance or off-resonance only requires changing the electron number by one, the amplitude of these voltage pulses can have orders of magnitude smaller voltage swings than those required to open and pinch off a gate. The reduction in the amplitude of the voltage pulses may reduce the need for compensating pulses on nearby gates and result in a significant reduction in how much the qubit heats up when operated.

[0074] In such qubit devices, the junctions can be formed by having a quantum dot that can couple to MZMs or adjacent quantum dots through electrostatic gates set to fixed or nearly-fixed voltages, then tuning other gates to resonance (e.g., a configuration where there is negligible energetic penalty for an additional electron to tunnel from an adjacent dot or topological wire into the quantum dot in question) increases the probability of single-electron transport through that junction. Tuning the quantum dots off-resonance (e.g., a regime where tunneling an electron onto the dot incurs significant energy penalty, also referred to the dot being in a Coulomb valley) decreases the probability of single-electron transport through the junction. When the charging energy of the quantum dot is sufficiently large, the difference in tunneling through the junction when the dot is resonant or in a Coulomb valley can be sufficient for operating the MZM qubit. Since the plunger gates for operating the quantum dots can have larger lever arms and the on-resonance and off-resonance corresponds to changing the occupation of the dot by a single electron, the voltage pulse needed for this type of operation will generally be orders of magnitude smaller than that needed to open and close traditional junctions.

[0075] In addition to such qubit devices, other devices may also have junctions that can attenuate the nonlocal conductance signal, which complicates the relationship between the extracted localization lengths and the nonlocal conductance. As explained earlier, the localization lengths are extracted based on the relationship between the decay of the signal across different lengths of the wire. The decay of the signal is a function of the resistance of the wire and any resistance that is contributed by the junction itself. In devices where the resistance contributed by the junction is negligible, the attenuation caused by the junction can be ignored. However, in any device that has junctions that can contribute to the resistance of the bulk of the wire during the extraction of the localization lengths, then the attenuation caused by one or more junctions needs to be addressed as part of extracting the localization lengths for that device.

[0076] As an example, FIG. 13 shows a diagram of another example hybrid superconductor-semiconductor quantum device 1300 with multiple junctions and gates for extracting localization lengths. Hybrid superconductor-semiconductor quantum device 1300 is configured and fabricated to be operated with the junctions that are similar to the junctions in devices with MZM qubits or other devices with junctions that can attenuate the nonlocal conductance values. As described earlier, the localization lengths are estimated by exploiting the relationship between the localization length and the nonlocal conductance values. For the hybrid superconductor-semiconductor quantum device 1300, the junctions can attenuate the nonlocal conductance signal. This substantially eliminates the measurement problems described previously, but complicates the relationship between the localization lengths and the nonlocal conductance values. In the hybrid superconductor-semiconductor quantum device 1300, the junctions can attenuate the nonlocal conductance signal, which complicates the relationship between the extracted localization lengths and the nonlocal conductance. The complication arises from the fact that part of the nonlocal conductance signal is affected not only by the disorder in the transport in the semiconductor nanowire, but also by the attenuation caused by the junction itself. The attenuation caused by the junction itself has a random component to it. To remove the effect of the junction attenuation, in one example, the nonlocal conductance signal is normalized by the square root of the product of the local conductance values (N=G.sub.RRG.sub.LL). The attenuation of the signal due to the junctions is equal to the attenuation of the nonlocal conductance. By defining a new quantity B=G.sub.nonlocal/N, which is invariant to changes in the junction transparency, the localization lengths can be estimated as described further.

[0077] With continued reference to FIG. 13, in this example, the hybrid superconductor-semiconductor quantum device 1300 has junctions that are optimized for operating in the tunneling regime. These junctions have a reduced size relative to the junctions described previously with respect to FIG. 2, such that the effect of the disorder with respect to the qubits is minimized. Hybrid superconductor-semiconductor quantum device 1300 includes a superconducting wire 1310, which interfaces with the underlying semiconductor. Superconducting wire 1310 corresponds to the parent superconductor. Hybrid superconductor-semiconductor quantum device 1300 includes drain and source terminals and several gates for operating the hybrid superconductor-semiconductor quantum device 1300. In this example, hybrid superconductor-semiconductor quantum device 1300 is shown as having two drain terminals (labeled as drain_left and drain_right). The hybrid superconductor-semiconductor quantum device 1300 is further shown as having six source terminals (labeled as source_1, source_2, source_3, source_4, source_5, and source_6).

[0078] With continued reference to FIG. 13, the hybrid superconductor-semiconductor quantum device 1300 is further shown as having six top gates (labeled as top_1_gate, top_2_ gate, top_3_gate, top_4_gate, top_5_gate, and top_6_gate). The hybrid superconductor-semiconductor quantum device 1300 is further shown as having six helper gates (labeled as helper_1_gate, helper_2_gate, helper_3_gate, helper_4_gate, helper_5_gate, and helper_6_gate). The hybrid superconductor-semiconductor quantum device 1300 is further shown as having two side plunger gates (labeled as sideplunger_left_gate and sideplunger_right_gate). The hybrid superconductor-semiconductor quantum device 1300 is further shown as having six plunger gates (labeled as plunger_1_2_gate, plunger_2_3_gate, plunger_3_4_gate, plunger_4_5_gate, and plunger_5_6_gate). In this example, the six plunger gates in the middle can have contacts that can be shared among segments of the superconductor wire. This allows for an economical design in terms of the physical layout of the hybrid superconductor-semiconductor quantum device 1300. In addition, the design of hybrid superconductor-semiconductor quantum device 1300 is similar to the design of devices having qubits. This allows for the measurements of nonlocal conductance values for devices with qubits. Although FIG. 13 shows a certain device layout and a corresponding measurement configuration, other device layouts and measurement configurations can also be used to measure the nonlocal conductance values.

[0079] FIG. 14 is an expanded view 1400 of a section 1320 of the hybrid superconductor-semiconductor quantum device 1300 of FIG. 13. Unless indicated otherwise, the same or similar gates and other components that are shown in FIG. 14 are referred to using the same reference numbers as used in FIG. 13. Expanded view 1400 shows a portion 1410 of the superconducting wire 1310 of the hybrid superconductor-semiconductor quantum device 1300 of FIG. 13. In addition, expanded view 1400 shows a portion 1420 of one of the plunger gates (plunger_4_5_gate) and another portion 1422 of another one of the plunger gates (sideplunger_right_gate) of the hybrid superconductor-semiconductor quantum device 1300 of FIG. 13. Expanded view 1400 further shows a portion 1430 of one of the plunger gates (plunger_5_6_gate) of the hybrid superconductor-semiconductor quantum device 1300 of FIG. 13. One of the junctions is between the portion 1420 and the portion 1430 of the respective plunger gates and the other junction is between portion 1422 and portion 1430 of the respective plunger gates. Expanded view 1400 further shows a portion 1442 of helper_5_gate and a portion 1444 of helper_6_gate of the hybrid superconductor-semiconductor quantum device 1300 of FIG. 13. Finally, expanded view 1400 further shows a portion 1452 of top_5_gate and a portion 1454 of top_6_gate of the hybrid superconductor-semiconductor quantum device 1300 of FIG. 13. As explained earlier, the top gates are used to tune the respective junctions into the tunneling regime to allow for the measurement of the nonlocal conductance values.

[0080] FIG. 15 is a diagram of a device layout 1500 of the hybrid superconductor-semiconductor quantum device 1300 of FIG. 13 with multiple gate-defined sections of different lengths (L.sub.1, L.sub.2, L.sub.3, L.sub.4, and L.sub.5) for measuring nonlocal conductance values. Device layout 1500 shows five gate-defined sections with lengths of L.sub.1, L.sub.2, L.sub.3, L.sub.4, and L.sub.5. The superconductor 1510 is underneath the various gates, including side plunger gates 1512 and 1514. Device layout 1500 further shows additional plunger gates 1522, 1524, 1526, 1528, and 1530. Device layout 1500 further shows top gates 1532, 1534, 1536, 1538, 1540, and 1542. Device layout 1500 further shows helper gates 1552, 1554, 1556, 1558, 1560, and 1562. Top gates 1532, 1534, 1536, 1538, 1540, and 1542 are formed in a layer above the layer in which the helper gates and the plunger gates are formed. Although not shown in FIG. 15, these gates are configured to contact the quantum well in a manner that allows the operation of the device. Device layout 1500 corresponds to a physical representation of the hybrid superconductor-semiconductor quantum device 1300 of FIG. 3. The physical representation of the hybrid superconductor-semiconductor quantum device may be a device under test or any other device formed on a single integrated circuit using semiconductor/superconductor fabrication techniques.

[0081] Similar to as described earlier with respect to FIG. 2, the plunger gate voltage of a respective section is varied during the measurement and all other gates are set to highly negative voltages to deplete all unwanted semiconductor states. The nonlocal conductance is then measured with the nanowire (the superconductor 1510) grounded. This measurement is then repeated for all sections (e.g., various combinations of the physical lengths L.sub.1, L.sub.2, L.sub.3, L.sub.4, and L.sub.5) of the nanowire. The junctions for this device can be operated in a regime where the local conductance is either large (in which case the measurements can be performed as described earlier with respect to FIG. 2) or small (in which case the nonlocal conductance is normalized). In the latter case, in one example, the respective top gates are tuned such that the device is in the tunneling regime, where the above gap local conductance is lower than 0.5 e.sup.2/h. The plunger gates and the junction gates described herein may be supplied voltages via voltage waveforms generated by a control system (not shown) associated with the hybrid superconductor-semiconductor quantum device. Such a control system may include oscillators, switches, finite state machines, and a memory. As an example, the memory may be implemented as one or more multi-bit registers for allowing scan-patterns and pulse-patterns to be stored. Although FIG. 15 shows a certain device layout 1500, other device layouts and measurement configurations can also be used to measure nonlocal conductance values.

[0082] FIG. 16 is a cross-section view 1600 of the portion 1500 of FIG. 15 along a junction associated with the hybrid superconductor-semiconductor quantum device 1300 of FIG. 13. As shown in cross-section view 1600, the device includes a substrate 1610 and a quantum well 1620, which is formed over substrate 1610. The device further includes a barrier 1630 formed over quantum well 1620. In this example, substrate 1610 may be an indium phosphide (InP) substrate. Quantum well 1630 may include several layers, including an indium gallium arsenide (InGaAs) layer, an indium arsenide (InAs) layer, and an indium aluminum arsenide (InAlAs) layer. Each of these layers may be formed using molecular-beam epitaxy (MBE). As an example, the MBE related process may be performed in an MBE system that allows the deposition of the appropriate materials in a vacuum.

[0083] With continued reference to FIG. 16, the cross-section view 1600 shows a superconductor 1602 (corresponding to superconducting wire 1510 of FIG. 15) and a contact 1612. A dielectric layer 1640 is shown as formed adjacent to and above superconductor 1602. In one example, superconductor 1602 may be formed by first forming an aluminum layer over barrier 1630, and then forming a dielectric over the aluminum layer. Cross-section view 1600 further shows a plunger gate 1660 formed over dielectric layer 1640, a dielectric layer 1650 formed over plunger gate 1660, and a helper gate 1670 formed over dielectric layer 1650. Dielectric layers 1640 and 1650 may be formed as oxide layers (e.g., hafnium oxide or aluminum oxide) or using another appropriate dielectric layer material. Plunger gate 1660 and helper gate 1670 may be formed of gold (Au) or a titanium-gold (TiAu) alloy. Although cross-section view 1600 of FIG. 16 shows a certain number of layers and components arranged in a certain order, the device (e.g., hybrid superconductor-semiconductor quantum device 1300 of FIG. 13) may include additional or fewer layers, arranged differently.

[0084] FIG. 17 is a flow chart 1700 of a method for estimating localization lengths in using the hybrid superconductor-semiconductor quantum (HSSQ) device of FIG. 13 in accordance with one example. The steps associated with this method may be performed using instructions (e.g., the various code blocks) stored in memory 120 of computing system 100 of FIG. 1. Step 1710 includes obtaining measurements of nonlocal conductance values associated with the HSSQ device, where at least one junction associated with the HSSQ device attenuates one or more of the measured nonlocal conductance values associated with the HSSQ device. As explained earlier, in one example, the measurements associated with the hybrid superconductor-semiconductor quantum device (e.g., HSSQ device 1300 of FIG. 13) comprise physical measurements of conductance for a set of device lengths.

[0085] Step 1720 includes normalizing the measured nonlocal conductance values to remove an effect of the attenuation caused by the at least one junction and extracting localization lengths based on the normalized nonlocal conductance values associated with the HSSQ device. In the hybrid superconductor-semiconductor quantum device 1300, the junctions can attenuate the nonlocal conductance signal, which complicates the relationship between the extracted localization lengths and the nonlocal conductance. The complication arises from the fact that part of the nonlocal conductance signal is affected not only by the disorder in the transport in the semiconductor nanowire, but also by the attenuation caused by the junction itself. The attenuation caused by the junction itself has a random component to it. To remove the effect of the junction attenuation, in one example, the nonlocal conductance signal is normalized by the square root of the product of the local conductance values (N=G.sub.RRG.sub.LL). The attenuation of the signal due to the junctions is equal to the attenuation of the nonlocal conductance. By defining a new quantity B=G.sub.nonlocal/N, which is invariant to changes in the junction transparency, the localization lengths can be estimated as described further.

[0086] The normalized nonlocal conductance values can be used to construct a statistical model for extracting localization lengths based on an implicit description of the measurements associated with the hybrid superconductor-semiconductor quantum device. Other techniques can also be used to construct a statistical model for extracting localization lengths based on an implicit description of the measurements associated with the hybrid superconductor-semiconductor quantum device.

[0087] Step 1730 includes using a processor, estimating the localization lengths for the HSSQ device by a joint prior distribution enforcing smoothness over a function of gate voltages and the extracted localization lengths for the HSSQ device. As explained earlier, the joint prior distribution is constructed by starting with independent local priors, in which a distribution over the localization lengths is assumed to be a product of the independent local priors, and adding one or more of a set of constraints onto the joint prior distribution such that a rate of change of the function is restricted to a specified maximum value. As explained earlier the appropriate level of the uniform smoothness may be determined by cross-validating complementary subsets of data (e.g., even vs. odd localization lengths) related to the extracted localization lengths. Additional details of this step of the method and the smoothing by enforcing the joint prior distribution are similar to as described earlier with respect to the device layout 210 of FIG. 2. In sum, after the nonlocal conductance values are normalized, a statistical model is constructed based on the implicit description of the nonlocal conductance values, where the statistical model comprises estimates of likelihood that are used to extract localization lengths at each of the gate voltages independently.

[0088] In addition, as described earlier, the joint prior distribution is constructed by starting with independent local priors, in which a distribution over the extracted localization lengths is assumed to be a product of the independent local priors, and adding one or more of a set of constraints onto the joint prior distribution such that a rate of change of the function is restricted to a specified maximum value. Finally, as described earlier, the independent local priors include a marginal prior with respect to values of the extracted localization lengths, a smoothness prior with respect to correlation among the values of the extracted localization lengths, and a mean free path prior with respect to values of neighboring extracted localization lengths.

[0089] FIG. 18 is a graph 1800 illustrating the scaling of the normalized nonlocal conductance for specific values of the local conductance in view of the different lengths of the superconducting wire. Each of the sets of dots are the nonlocal conductance values as a function of the length of the wire (e.g., 1.1 m, 1.6 m, 2.3 m, 3.0 m and 4.0 m) as shown in the legend in FIG. 18. Dots 1810 correspond to the theoretical expectation (expressed as the Lyaponuv estimate) for the normalized nonlocal conductance values for different lengths of the superconducting wire.

[0090] FIG. 19 is a graph 1900 illustrating the estimated localization lengths from normalized nonlocal conductance values versus the plunger voltage. Graph 1900 uses simulated data to illustrate the use of the method described with respect to flowchart 1700 of FIG. 17. Dots 1910 correspond to the theoretical expectation (expressed as the Lyaponuv estimate) for the estimated localization lengths. The remaining dots in graph 1900 represent the estimated localization lengths from the normalized nonlocal conductance values. Graph 1900 shows estimated localization lengths for the higher local conductance values (G.sub.LL and G.sub.RR) to the lower conductance values.

[0091] FIG. 20 is a flow chart 2000 of a method for characterizing a level of disorder in HSSQ device 1300 of FIG. 13 in accordance with one example. The steps associated with this method may be performed using instructions (e.g., the various code blocks) stored in memory 120 of computing system 100 of FIG. 1. Step 2010 includes obtaining measurements of nonlocal conductance values associated with the HSSQ device, where at least one junction associated with the HSSQ device attenuates one or more of the measured nonlocal conductance values associated with the HSSQ device. As explained earlier, in one example, the measurements associated with the hybrid superconductor-semiconductor quantum device (e.g., HSSQ device 1300 of FIG. 13) comprise physical measurements of conductance for a set of device lengths.

[0092] Step 2020 includes normalizing the measured nonlocal conductance values to remove an effect of the attenuation caused by the at least one junction and extracting localization lengths based on the normalized nonlocal conductance values associated with the HSSQ device. As noted earlier, in the hybrid superconductor-semiconductor quantum device 1300, the junctions can attenuate the nonlocal conductance signal, which complicates the relationship between the extracted localization lengths and the nonlocal conductance. The complication arises from the fact that part of the nonlocal conductance signal is affected not only by the disorder in the transport in the semiconductor nanowire, but also by the attenuation caused by the junction itself. The attenuation caused by the junction itself has a random component to it. To remove the effect of the junction attenuation, in one example, the nonlocal conductance signal is normalized by the square root of the product of the local conductance values (N=G.sub.RRG.sub.LL). The attenuation of the signal due to the junctions is equal to the attenuation of the nonlocal conductance. By defining a new quantity B=G.sub.nonlocal/N, which is invariant to changes in the junction transparency, the localization lengths can be estimated as described further. The normalized measurement values can be used to construct a statistical model for extracting localization lengths based on an implicit description of the measurements associated with the hybrid superconductor-semiconductor quantum device. Other techniques can also be used to construct a statistical model for extracting localization lengths based on an implicit description of the measurements associated with the hybrid superconductor-semiconductor quantum device.

[0093] Step 2030 includes using a processor, based on the extracted localization lengths, estimating the localization lengths for the HSSQ device. In one example, this step may be performed by a joint prior distribution enforcing smoothness over a function of gate voltages and the extracted localization lengths for the HSSQ device. As explained earlier, the joint prior distribution is constructed by starting with independent local priors, in which a distribution over the localization lengths is assumed to be a product of the independent local priors, and adding one or more of a set of constraints onto the joint prior distribution such that a rate of change of the function is restricted to a specified maximum value. As explained earlier the appropriate level of the uniform smoothness may be determined by cross-validating complementary subsets of data (e.g., even vs. odd localization lengths) related to the extracted localization lengths. Additional details of this step of the method and the smoothing by enforcing the joint prior distribution are similar to as described earlier with respect to the device layout 210 of FIG. 2. In sum, after the nonlocal conductance values are normalized, a statistical model is constructed based on the implicit description of the nonlocal conductance values, where the statistical model comprises estimates of likelihood that are used to extract localization lengths at each of the gate voltages independently.

[0094] In addition, as described earlier, the joint prior distribution is constructed by starting with independent local priors, in which a distribution over the extracted localization lengths is assumed to be a product of the independent local priors, and adding one or more of a set of constraints onto the joint prior distribution such that a rate of change of the function is restricted to a specified maximum value. Finally, as described earlier, the independent local priors include a marginal prior with respect to values of the extracted localization lengths, a smoothness prior with respect to correlation among the values of the extracted localization lengths, and a mean free path prior with respect to values of neighboring extracted localization lengths.

[0095] Step 2040 includes using the processor, based on the estimated localization lengths, characterizing the level of disorder in the HSSQ device. As noted earlier, the disorder in the bulk of superconducting wires associated with the hybrid superconductor-semiconductor quantum devices suppresses the topological gap and increases the coherence length. This, in turn, leads to a minimum length requirement for the superconducting wire to perform well as a part of a qubit that depends on the composition/geometry of the stack of layers used to form the wire and the disorder level. In the topological phase, the coherence length corresponds to the localization length of a Majorana zero mode (MZM). In the topological phase, when the disorder is very weak, the localization length approaches the localization length of a perfectly clean system, which has no states below the clean topological gap, apart from the MZMs. Increased disorder elongates the localization length in the topological phase and shortens it in the trivial phase. In sum, the estimated localization lengths derived from step 2030 can be used to characterize the level of disorder in the HSSQ device 1300 of FIG. 13. As an example, calculation code 126 stored in memory 120 of computing system 100 may be used to characterize the level of disorder based on the estimated localization lengths.

[0096] In conclusion, the present disclosure relates to a method for estimating localization lengths in a hybrid superconductor-semiconductor quantum (HSSQ) device, where the HSSQ device comprises a set of plunger gates formed in a first layer of the HSSQ device and a set of top gates formed, above the set of plunger gates, in a second layer of the HSSQ device. The method may include obtaining measurements of nonlocal conductance values associated with the HSSQ device, where at least one junction associated with the HSSQ device attenuates one or more of the measured nonlocal conductance values associated with the HSSQ device.

[0097] The method may further include normalizing the measured nonlocal conductance values to remove an effect of the attenuation caused by the at least one junction and extracting localization lengths based on the normalized nonlocal conductance values associated with the HSSQ device. The method may further include, using a processor, estimating the localization lengths for the HSSQ device by a joint prior distribution enforcing smoothness over a function of gate voltages and the extracted localization lengths for the HSSQ device.

[0098] As part of this method, normalizing the measured nonlocal conductance values to remove an effect of the attenuation caused by the at least one junction may comprise normalizing each of the measured nonlocal conductance values by a square root of a product of respective local conductance values. Moreover, the measurements of the nonlocal conductance values associated with the HSSQ device may be obtained by measuring nonlocal conductance values of sections of a superconducting wire associated with the HSSQ device by selectively supplying voltages to one or more of the set of plunger gates and the set of top gates, respectively.

[0099] The method may further include constructing a statistical model based on an implicit description of the measurements of the nonlocal conductance values. The statistical model may comprise estimates of likelihood that are used to extract localization lengths at each of the gate voltages independently.

[0100] As part of this example method, the joint prior distribution may be constructed by starting with independent local priors, in which a distribution over the extracted localization lengths is assumed to be a product of the independent local priors, and adding one or more of a set of constraints onto the joint prior distribution such that a rate of change of the function is restricted to a specified maximum value. The independent local priors may include a marginal prior with respect to values of the extracted localization lengths, a smoothness prior with respect to correlation among the values of the extracted localization lengths, and a mean free path prior with respect to values of neighboring extracted localization lengths.

[0101] In another example, the present disclosure relates to a method for estimating localization lengths in a hybrid superconductor-semiconductor quantum (HSSQ) device. The HSSQ device may comprise a set of plunger gates formed in a first layer of the HSSQ device and a set of top gates formed, above the set of plunger gates, in a second layer of the HSSQ device. The method may include measuring nonlocal conductance values of sections of a superconducting wire associated with the HSSQ device by selectively supplying voltages to one or more of the set of plunger gates and the set of top gates, respectively.

[0102] The method may further include extracting localization lengths based on the measured nonlocal conductance values associated with the HSSQ device. The method may further include normalizing the measured nonlocal conductance values to remove an effect of the attenuation caused by the at least one junction and extracting localization lengths based on the normalized nonlocal conductance values associated with the HSSQ device. The method may further include, using a processor, estimating the localization lengths for the HSSQ device by a joint prior distribution enforcing smoothness over a function of gate voltages and the extracted localization lengths for the HSSQ device.

[0103] As part of this method, normalizing the measured nonlocal conductance values to remove an effect of the attenuation caused by the at least one junction may comprise normalizing each of the measured nonlocal conductance values by a square root of a product of respective local conductance values. The method may further include constructing a statistical model based on an implicit description of the measurements of the nonlocal conductance values. The statistical model may comprise estimates of likelihood that are used to extract localization lengths at each of the gate voltages independently.

[0104] As part of this example method, the joint prior distribution may be constructed by starting with independent local priors, in which a distribution over the extracted localization lengths is assumed to be a product of the independent local priors, and adding one or more of a set of constraints onto the joint prior distribution such that a rate of change of the function is restricted to a specified maximum value. The independent local priors may include a marginal prior with respect to values of the extracted localization lengths, a smoothness prior with respect to correlation among the values of the extracted localization lengths, and a mean free path prior with respect to values of neighboring extracted localization lengths.

[0105] In yet another example, the present disclosure relates to a method for characterizing a level of disorder in a hybrid superconductor-semiconductor quantum (HSSQ) device. The HSSQ device may comprise a set of plunger gates formed in a first layer of the HSSQ device and a set of top gates formed, above the set of plunger gates, in a second layer of the HSSQ device. The method may include obtaining measurements of nonlocal conductance values associated with the HSSQ device, where at least one junction associated with the HSSQ device attenuates one or more of the measured nonlocal conductance values associated with the HSSQ device.

[0106] The method may further include normalizing the measured nonlocal conductance values to remove an effect of the attenuation caused by the at least one junction and extracting localization lengths based on the normalized nonlocal conductance values associated with the HSSQ device. The method may further include, using a processor, based on the extracted localization lengths, estimating the localization lengths for the HSSQ device. The method may further include, using the processor, based on the estimated localization lengths, characterizing the level of disorder in the HSSQ device.

[0107] As part of this method, normalizing the measured nonlocal conductance values to remove an effect of the attenuation caused by the at least one junction may comprise normalizing each of the measured nonlocal conductance values by a square root of a product of respective local conductance values. Moreover, the measurements of the nonlocal conductance values associated with the HSSQ device may be obtained by measuring nonlocal conductance values of sections of a superconducting wire associated with the HSSQ device by selectively supplying voltages to one or more of the set of plunger gates and the set of top gates, respectively.

[0108] As part of this method, estimating the localization lengths for the HSSQ device may comprise estimating by a joint prior distribution enforcing smoothness over a function of gate voltages and the normalized localization lengths for the HSSQ device. The method may further comprise constructing a statistical model based on an implicit description of the measurements of the nonlocal conductance values, and where the statistical model may comprise estimates of likelihood that are used to extract localization lengths at each of the gate voltages independently.

[0109] As part of this method, the joint prior distribution may be constructed by starting with independent local priors, in which a distribution over the extracted localization lengths is assumed to be a product of the independent local priors, and adding one or more of a set of constraints onto the joint prior distribution such that a rate of change of the function is restricted to a specified maximum value. The independent local priors may include a marginal prior with respect to values of the extracted localization lengths, a smoothness prior with respect to correlation among the values of the extracted localization lengths, and a mean free path prior with respect to values of neighboring extracted localization lengths.

[0110] It is to be understood that the systems, devices, methods, and components described herein are merely examples. In an abstract, but still definite sense, any arrangement of components to achieve the same functionality is effectively associated such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as associated with each other such that the desired functionality is achieved, irrespective of architectures or inter-medial components. Likewise, any two components so associated can also be viewed as being operably connected, or coupled, to each other to achieve the desired functionality. Merely because a component, which may be an apparatus, a structure, a device, a system, or any other implementation of a functionality, is described herein as being coupled to another component does not mean that the components are necessarily separate components. As an example, a component A described as being coupled to another component B may be a sub-component of the component B, the component B may be a sub-component of the component A, or components A and B may be a combined sub-component of another component C.

[0111] Furthermore, those skilled in the art will recognize that boundaries between the functionality of the above described operations are merely illustrative. The functionality of multiple operations may be combined into a single operation, and/or the functionality of a single operation may be distributed in additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

[0112] Although the disclosure provides specific examples, various modifications and changes can be made without departing from the scope of the disclosure as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure. Any benefits, advantages, or solutions to problems that are described herein with regard to a specific example are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.

[0113] Furthermore, the terms a or an, as used herein, are defined as one or more than one. Also, the use of introductory phrases such as at least one and one or more in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles a or an limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases one or more or at least one and indefinite articles such as a or an. The same holds true for the use of definite articles.

[0114] Unless stated otherwise, terms such as first and second are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.