APPARATUS INCLUDING A CMOS PASS GATE CIRCUIT AND A BOOTSTRAP CIRCUIT
20250309898 ยท 2025-10-02
Assignee
Inventors
Cpc classification
H03K3/012
ELECTRICITY
International classification
H03K3/012
ELECTRICITY
Abstract
One or more examples relate to a complementary metal-oxide-semiconductor (CMOS) device. The CMOS device includes a CMOS pass gate circuit, a control circuit, and a bootstrap circuit. The CMOS pass gate circuit includes an n-channel transistor and a p-channel transistor. The control circuit may activate and deactivate the CMOS pass gate circuit. The bootstrap circuit may be electrically connected between the CMOS pass gate circuit and the control circuit. The bootstrap circuit may increase a first drive gain of the n-channel transistor and a second drive gain of the p-channel transistor.
Claims
1. An apparatus comprising: a complementary metal-oxide-semiconductor (CMOS) pass gate circuit including a first n-channel transistor and a first p-channel transistor; a control circuit to generate control signals to activate the CMOS pass gate circuit; and a bootstrap circuit electrically connected between the CMOS pass gate circuit and the control circuit, said bootstrap circuit to increase a first drive gain of the first n-channel transistor and a second drive gain of the first p-channel transistor.
2. The apparatus of claim 1, wherein said bootstrap circuit comprises a second n-channel transistor and a second p-channel transistor, said second n-channel transistor electrically connected between the control circuit and the first n-channel transistor, said second p-channel transistor electrically connected between the control circuit and the first p-channel transistor, said second n-channel transistor to receive a first complementary control signal of the control signals and convey a first drive voltage corresponding to the first complementary control signal to the first n-channel transistor, said first drive voltage to activate the first n-channel transistor and increase the first drive gain, said second p-channel transistor to receive a second complementary control signal of the control signals and convey a second drive voltage corresponding to the second complementary control signal to the first p-channel transistor, said second drive voltage to activate the first p-channel transistor and increase the second drive gain.
3. The apparatus of claim 2, wherein said control circuit including an output having a first signal path electrically connected to the second p-channel transistor and a second signal path electrically connected to the second n-channel transistor, said second signal path including an inverter, said inverter to invert a control signal of the control signals to generate the first complementary control signal.
4. The apparatus of claim 2, wherein said control signals include the first complementary control signal and the second complementary control signal, said control circuit includes a first output electrically connected to the second n-channel transistor and a second output electrically connected to the second p-channel transistor, said first output to convey the first complementary control signal to the second n-channel transistor, said second output to convey the second complementary control signal to the second p-channel transistor.
5. The apparatus of claim 2, comprising an input terminal electrically connected to the CMOS pass gate circuit, said input terminal to convey an input signal to the CMOS pass gate circuit, said input signal to alternate between a high voltage level and a low voltage level, said high voltage level being greater than said low voltage level, respective ones of said first p-channel transistor, first n-channel transistor, second p-channel transistor, and second n-channel transistor including a respective gate terminal, a respective source terminal, and a respective drain terminal.
6. The apparatus of claim 5, comprising a first capacitive coupling formed between the gate and source terminals of the first n-channel transistor, said first capacitive coupling generated by the first drive voltage, a second capacitive coupling formed between the gate and source terminals of the first p-channel transistor, said second capacitive coupling generated by the second drive voltage.
7. The apparatus of claim 6, said first and second capacitive couplings to increase a first gate voltage of the first n-channel transistor and a second gate voltage of the first p-channel transistor in proportion to a rise of the input signal.
8. The apparatus of claim 6, said first and second capacitive couplings to decrease a first gate voltage of the first n-channel transistor and a second gate voltage of the first p-channel transistor in proportion to a fall of the input signal.
9. The apparatus of claim 6, including said gate terminal of the first p-channel transistor electrically connected to the source terminal of the second p-channel transistor, said gate terminal of the first n-channel transistor electrically connected to the source terminal of the second n-channel transistor, said source terminals of the first p-channel transistor and the first n-channel transistor electrically connected to the input terminal, said gate terminals of the second p-channel transistor and the second n-channel transistor electrically connected to one or more power supplies, said drain terminals of the second p-channel transistor and the second n-channel transistor electrically connected to the control circuit.
10. A circuit arrangement comprising: a complementary metal-oxide-semiconductor (CMOS) pass gate circuit; and a bootstrap circuit electrically connected to the CMOS pass gate circuit, said bootstrap circuit to increase a drive gain of the CMOS pass gate circuit.
11. The circuit arrangement of claim 10, wherein said CMOS pass gate circuit comprises a first n-channel transistor and a first p-channel transistor, said bootstrap circuit comprises a second n-channel transistor electrically connected to the first n-channel transistor and a second p-channel transistor electrically connected to the first p-channel transistor, said second n-channel transistor to convey a first drive voltage to the first n-channel transistor, said second p-channel transistor to convey a second drive voltage to the first p-channel transistor.
12. The circuit arrangement of claim 11, respective ones of said first p-channel transistor, first n-channel transistor, second p-channel transistor, and second n-channel transistor including a respective gate terminal, a respective source terminal, and a respective drain terminal.
13. The circuit arrangement of claim 12, comprising an input terminal to receive an input signal, said input terminal electrically connected to the respective source terminals of the first n-channel transistor and the first p-channel transistor, a first capacitive coupling between the gate and source terminals of the first n-channel transistor, said first capacitive coupling generated by the first drive voltage, a second capacitive coupling between the gate and source terminals of the first p-channel transistor, said second capacitive coupling generated by the second drive voltage.
14. The circuit arrangement of claim 13, comprising a first gate-source voltage of the first n-channel transistor to have a first constant voltage value maintained by said first capacitive coupling, a second gate-source voltage of the first p-channel transistor to have a second constant voltage value maintained by said second capacitive coupling.
15. The circuit arrangement of claim 12, comprising a control circuit, an input terminal, said gate terminal of the first p-channel transistor electrically connected to the source terminal of the second p-channel transistor, said gate terminal of the first n-channel transistor electrically connected to the source terminal of the second n-channel transistor, said source terminals of the first p-channel transistor and the first n-channel transistor electrically connected to the input terminal, said gate terminals of the second p-channel transistor and the second n-channel transistor electrically connected to one or more power supplies, said drain terminals of the second p-channel transistor and the second n-channel transistor electrically connected to the control circuit.
16. A method comprising: activating, by one or more power supplies, a bootstrap circuit; generating, by a control circuit, one or more control signals; activating, by the bootstrap circuit, a complementary metal-oxide-semiconductor (CMOS) pass gate circuit based on the one or more control signals; receiving, by the CMOS pass gate circuit, an input signal; and increasing, by the bootstrap circuit, a drive gain of the CMOS pass gate circuit.
17. The method of claim 16, comprising receiving, by a first n-channel transistor of the CMOS pass gate circuit, a first drive voltage corresponding to a first complementary control signals of the one or more control signals from the bootstrap circuit, receiving, by a first p-channel transistor of the CMOS pass gate circuit, a second drive voltage corresponding to a second complementary control signal of the one or more control signals from the bootstrap circuit.
18. The method of claim 17, comprising generating, in response to receiving the first drive voltage at the first n-channel transistor, a first capacitive coupling between a gate terminal and a source terminal of the first n-channel transistor, generating, in response to receiving the second drive voltage at the first p-channel transistor, a second capacitive coupling between a gate terminal and a source terminal of the first p-channel transistor.
19. The method of claim 18, wherein increasing the drive gain of the CMOS pass gate circuit comprises increasing, by the first capacitive coupling, a first gate voltage of the first n-channel transistor in response to a rise in the input signal, decreasing, by the second capacitive coupling, a second gate voltage of the first p-channel transistor in response to a fall in the input signal.
20. The method of claim 18, said input signal increasing in voltage during a rise period and decreasing in voltage during a fall period, said increasing of the drive gain of the CMOS pass gate circuit comprising maintaining, by the first capacitive coupling, a first constant voltage value of a first gate-source voltage of the first n-channel transistor during the rise period and the fall period, maintaining, by the second capacitive coupling, a second constant voltage value of a second gate-source voltage of the first p-channel transistor during the rise period and the fall period.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
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[0015] Unless otherwise indicated, the figures provided herein are meant to illustrate features of examples of this disclosure. These features are believed to be applicable in a wide variety of systems comprising one or more examples of this disclosure. As such, the figures are not meant to include all conventional features known by those of ordinary skill in the art to be required for the practice of the examples disclosed herein.
DETAILED DESCRIPTION
[0016] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and in which are shown, by way of illustration, specific examples in which the present disclosure may be practiced. These examples are described in sufficient detail to enable a person of ordinary skill in the art to practice the present disclosure. However, other examples may be utilized, and structural, material, and process changes may be made without departing from the scope of the disclosure.
[0017] The illustrations presented herein are not meant to be actual views of any particular method, system, device, or structure, but are merely idealized representations that are employed to describe the examples of the present disclosure. The drawings presented herein are not necessarily drawn to scale. Similar structures or components in the various drawings may retain the same or similar numbering for the convenience of the reader; however, the similarity in numbering does not mean that the structures or components are necessarily identical in size, composition, configuration, or any other property.
[0018] The following description may include examples to help enable one of ordinary skill in the art to practice the disclosed examples. The use of the terms exemplary, by example, and for example, means that the related description is explanatory, and though the scope of the disclosure is intended to encompass the examples and legal equivalents, the use of such terms is not intended to limit the scope of an example or this disclosure to the specified components, operations, features, functions, or the like.
[0019] It will be readily understood that the components of the examples as generally described herein and illustrated in the drawings could be arranged and designed in a wide variety of different configurations. Thus, the following description of various examples is not intended to limit the scope of the present disclosure but is merely representative of various examples.
[0020] Various examples of the present disclosure relate to a CMOS device having a bootstrap circuit and a CMOS pass gate circuit. The bootstrap circuit may boost a drive gain of the CMOS pass gate circuit. The boosted drive gain may enable a constant drive voltage to be maintained across one or more transistors included in the CMOS pass gate circuit. Maintaining a constant drive voltage may prevent significant current leakage or voltage decay associated with the CMOS pass gate circuit during operation of the CMOS device.
[0021] In various examples, the CMOS device may be utilized as part of a reprogrammable device or an integrated circuit (IC), without limitation. In various examples, the reprogrammable device may be a field-programmable gate array (FPGA), a programmable logic device (PLD), or a field-programmable system level integrated circuit (FPSLIC), without limitation. The reprogrammable device may include a control circuit. The control circuit may be a configuration memory circuit. The configuration memory circuit may include a random access memory (RAM), static random access memory (SRAM), a serial SRAM, a non-volatile random access memory (NVRAM), a serial peripheral interface (SPI) flash memory, a non-volatile static random access memory (NVSRAM), or a non-volatile memory (NVM) type circuit, without limitation. In various examples, a plurality of CMOS devices may be implemented in the reprogrammable device.
[0022]
[0023] In various examples, the control circuit 102 may be a memory device for configuring one or more FPGAs, such as a RAM, SRAM, serial SRAM, NVRAM, SPI flash memory, NVSRAM, or other NVM type circuit, without limitation. The control circuit 102 may configure or reprogram one or more reprogrammable devices, such as an FPGA, FPSLIC, or PLD, without limitation. The control circuit 102 may be electrically connected to one or more power supplies 124. The one or more power supplies 124 may provide electric power to the control circuit 102. In various examples, the one or more power supplies 124 connected to the control circuit 102 may or may not be the same as the one or more power supplies 124 electrically connected to the bootstrap circuit 104. In various examples, the one or more power supplies 124 may be a voltage rail or voltage bus, without limitation.
[0024] In various examples, the CMOS pass gate circuit 110 includes a first n-channel transistor 112 and a first p-channel transistor 114. In various examples, the first n-channel transistor 112 may be an n-channel metal oxide semiconductor (NMOS) transistor and the first p-channel transistor 114 may be a p-channel metal oxide semiconductor (PMOS) transistor. In various examples, the bootstrap circuit 104 includes a second p-channel transistor 106 and a second n-channel transistor 108. In various examples, the second p-channel transistor 106 may be a PMOS transistor and the second n-channel transistor 108 may be an NMOS transistor.
[0025] The PMOS transistor 106 includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the PMOS transistor 106 may be electrically connected to the one or more power supplies 124, as described above. The drain terminal of the PMOS transistor 106 may be electrically connected to the control circuit 102. The NMOS transistor 108 includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the NMOS transistor 108 may be electrically connected to the one or more power supplies 124, as described above. The drain terminal of the NMOS transistor 108 may be electrically connected to the control circuit 102. The gate, source, and drain terminals of the NMOS transistor 108 and PMOS transistor 106 are described in detail below with reference to
[0026] In various examples the NMOS transistor 112 includes a gate terminal, a source terminal, and a drain terminal. The PMOS transistor 114 includes a gate terminal, a source terminal, and a drain terminal. The source terminal of the PMOS transistor 114 and the source terminal of the NMOS transistor 112 may be electrically connected to the input terminal 116. The drain terminal of the PMOS transistor 114 and the drain terminal of the NMOS transistor 112 may be electrically connected to the output terminal 118. The gate, source, and drain terminals of the NMOS transistor 112 and PMOS transistor 114 are described in detail below with reference to
[0027] The control circuit 102 may include a first output terminal 120 and a second output terminal 122. The control circuit 102 may generate one or more control signals for activating or deactivating the CMOS pass gate circuit 110. The one or more control signals may include a logic high value, a logic low value, or both a logic high value and a logic low value, without limitation. The one or more control signals may include a first complementary control signal and a second complementary control signal. The first complementary control signal may activate or deactivate the NMOS transistor 112 and may be provided on the control circuit second output terminal 122. The second complementary control signal may activate or deactivate the PMOS transistor 114 and may be provided on the control circuit first output terminal 120. The first and second output terminals 120, 122 may convey the complementary control signals to the bootstrap circuit 104. The bootstrap circuit 104 may pass the complementary control signals to the CMOS pass gate circuit 110.
[0028] In various examples, the first and second complementary control signals may have complementary values. In a first state, the first complementary control signal may include the logic low value and the second complementary control signal may include the logic high value. The first state of the control signals may activate the CMOS pass gate circuit 110. In a second state, the first complementary control signal may include the logic high value and the second complementary control signal may include the logic low value. The second state of the control signal may deactivate the CMOS pass gate circuit 110. In various examples, the logic high value may be equivalent to a source voltage V.sub.dd. The logic low value may be equivalent to a ground voltage. In various examples, the source voltage V.sub.dd may be 0.75V, 0.85V, 1.5V, or another voltage, without limitation. The ground voltage may be 0V, without limitation.
[0029] In various examples, PMOS transistor 106 and NMOS transistor 108 may be electrically connected to one or more power supplies 124. The one or more power supplies 124 may activate the bootstrap circuit 104. The one or more power supplies 124 may supply the source voltage V.sub.dd to the gate terminal of the NMOS transistor 108 and the ground voltage to the gate terminal of the PMOS transistor 106.
[0030] In various examples, the gate terminal of the NMOS transistor 112 may be electrically connected to the source terminal of the NMOS transistor 108. A first drive voltage corresponding to the first complementary control signal may be received at the gate terminal of the NMOS transistor 112. More specifically, the first drive voltage may be generated by the NMOS transistor 112 in response to receiving the first complementary control signal. The NMOS transistor 108 of the bootstrap circuit 104 may receive the first complementary control signal and provide the first drive voltage to the NMOS transistor 112. The bootstrap circuit 104 may increase a first drive gain of the NMOS transistor 108 based on, at least in part, the value of the first complementary control signal. The first complementary control signal may activate or deactivate the NMOS transistor 112. The first complementary control signal having the high logic value may activate the NMOS transistor 112. The first complementary control signal having the low logic value may deactivate the NMOS transistor 112.
[0031] In various examples, the gate terminal of the PMOS transistor 114 may be electrically connected to the source terminal of the PMOS transistor 106. A second drive voltage corresponding to the second complementary control signal may be received at the gate terminal of the PMOS transistor 114. More specifically, the second drive voltage may be generated by the PMOS transistor 114 in response to receiving the second complementary control signal. The PMOS transistor 106 of the bootstrap circuit 104 may receive the second complementary control signal and provide the second drive signal to the PMOS transistor 114. In various examples, the second complementary control signal having the low logic value may activate the PMOS transistor 114. The second complementary control signal having the high logic value may deactivate the PMOS transistor 114.
[0032] It would be appreciated by one of ordinary skill in the art that the source and drain terminals of the PMOS transistors 106, 114, and the NMOS transistors 108, 112, may be interchangeable as a function of a voltage difference between the respective gate terminals and the respective source or drain terminals. In various examples, respective bias voltages applied to the PMOS transistors 106, 114 and the NMOS transistors 108, 112 may cause the PMOS transistors 106, 114 and the NMOS transistors 108, 112 to operate in a forward biased state or reverse biased state, depending on whether a respective gate voltage is higher or lower than the source or drain voltage, without departing from the scope of the present disclosure. In various examples, the PMOS transistors 106, 114 and the NMOS transistors 108, 112 may be fin field-effect transistors (FinFETs), without limitation.
[0033] In various examples, the bootstrap circuit 104 may increase respective drive gains of the NMOS transistor 112 and the PMOS transistor 114. The PMOS transistor 106 and the NMOS transistor 108 may control an amount of voltage supplied to the gate terminals of the PMOS transistor 114 and the NMOS transistor 112, respectively. The NMOS transistor 108 and the PMOS transistor 106 may continuously receive power from the one or more power supplies 124 and may provide the first and second drive voltages to the NMOS transistor 112 and the PMOS transistor 114 in response to receiving the first and second complementary control signals. The NMOS transistor 108 and the PMOS transistor 106 may cause first and second capacitive couplings to form across the respective gate and source terminals of the NMOS transistor 112 and the PMOS transistor 114, respectively, in response to signal transitions of the input signal.
[0034] The signal transitions of the input signal may include a rise and a fall. The rise may correspond to a voltage increase of the input signal. In various examples, the input signal may rise from a low voltage level to a high voltage level. The high voltage level may be greater than the low voltage level. In various examples, the high voltage level may correspond to a source voltage V.sub.dd, without limitation. In various examples, the low voltage level may be equivalent to a ground voltage, or 0V, without limitation. The fall may correspond to a voltage decrease of the input signal. The decrease may be from the high voltage level to the low voltage level. The rise may be associated with a rise time. The rise time may correspond to a time period beginning when the input signal begins increasing in voltage from the low voltage level and ending when the input signal reaches the high voltage level. The fall time may correspond to a time period beginning when the input signal begins decreasing in voltage from the high voltage level and ending when the input signal reaches the low voltage level. In various examples, the input signal may be received at the input terminal 116. In various examples, the input signal may be a continuous signal, without limitation.
[0035] The first capacitive coupling may be formed between the gate and source terminals of NMOS transistor 112 in response to receiving the first drive voltage at the NMOS transistor 112. The first drive voltage may be supplied to the NMOS transistor 112 before the input signal is received. The NMOS transistor 108 may shut off after supplying the drive voltage to the NMOS transistor 112 due to equivalent gate voltages at the NMOS transistors 108, 112. The shut off of the NMOS transistor 108 may trap a charge at the gate of the NMOS transistor 112, causing the first capacitive coupling to form. When the input signal is received, the capacitive coupling may cause the gate voltage of the NMOS transistor 112 to increase and decrease by a same amount as, or proportional to, the rise and fall of the input signal. The increase and decrease of the gate voltage of the NMOS transistor 112 in proportion to the input signal may cause a first constant voltage value to be maintained across the gate and source terminals of the NMOS transistor 112. Accordingly, signal leakage associated with the rise and fall times of the input signal may be minimized and switching times may be reduced.
[0036] The second capacitive coupling may be formed between the gate and source terminals of PMOS transistor 114 in response to receiving the second drive voltage at the PMOS transistor 114. The second drive voltage may be supplied to the PMOS transistor 114 before the input signal is received. The PMOS transistor 106 may shut off after supplying the second drive voltage to the PMOS transistor 114 due to equivalent gate voltages at the PMOS transistors 106, 114. The shut off of the PMOS transistor 108 may trap a charge at the gate of the PMOS transistor 114, causing the second capacitive coupling to form. When the input signal is received, the second capacitive coupling may cause the gate voltage of the PMOS transistor 114 to increase and decrease by a same amount as, or proportional to, the rise and fall of the input signal. The increase and decrease of the gate voltage of the PMOS transistor 114 in proportion to the input signal may cause a second constant voltage value to be maintained across the gate and source terminals of the PMOS transistor 114. Accordingly, signal leakage associated with the rise and fall times of the input signal may be minimized and switching times may be reduced.
[0037] The respective capacitive couplings may cause respective gate voltages of the NMOS transistor 112 and the PMOS transistor 114 to increase or decrease in proportion to the rise and fall of the input signal received at the input terminal 116. More specifically, as the input signal increases from 0V to V.sub.dd, the respective gate voltages of the NMOS transistor 112 and the PMOS transistor 114 may increase by the same amount as the input signal, or V.sub.dd. If the input signal decreased from Vdd to 0V The respective gate voltages of the NMOS transistor 112 and the PMOS transistor 114 may decrease by the same amount, or V.sub.dd.
[0038] In various examples, the input signal may initially be at the low voltage level and the gate voltage of the NMOS transistor 112 may be equivalent to the source voltage V.sub.dd due to the first drive voltage from the bootstrap circuit 104. As described above, after supplying the first drive voltage, the NMOS transistor 108 may be turned off before the input signal is received, causing a first charge to be trapped at the gate of the NMOS transistor 112. The first trapped charge may cause the first capacitive coupling to form. As the input signal rises from the low voltage level to the high voltage level, the first capacitive coupling causes the gate voltage of the NMOS transistor 112 to increase in proportion with the voltage increase of the input signal. As the input signal reaches the source voltage V.sub.dd, the gate voltage of the NMOS transistor 112 may be 2V.sub.dd. Accordingly, the first capacitive coupling may maintain the first constant voltage value across the source and gate terminals of the NMOS transistor 112.
[0039] When the input signal begins to fall from V.sub.dd to 0V, the gate voltage of the PMOS transistor 114 may be equal to 0V and may decrease in proportion to the fall of the input signal. As described above, after supplying the second drive voltage, the PMOS transistor 106 may be turned off before the input signal is received, causing a second charge to be trapped at the gate of the PMOS transistor 114. The second trapped charge may cause the second capacitive coupling to form. As the input signal falls, the gate voltage of the PMOS transistor 114 may decrease, or be coupled down, by an amount of voltage equivalent to the fall of the input signal. As the input signal reaches 0V, the gate voltage of the PMOS transistor 114 may be V.sub.dd. Accordingly, the second capacitive coupling may maintain the second constant voltage value across the source and gate terminals of the NMOS transistor 112.
[0040] In various examples, the NMOS transistor 112 and the PMOS transistor 114 are being over-driven as the input signal rises and falls by the first and second capacitive couplings formed in response to receiving the first and second drive voltages. First and second gate-source voltages V.sub.gs, of the NMOS transistor 112 and the PMOS transistor 114, may be maintained at the first and second constant voltage levels, respectively, due to the first and second drive voltages from the bootstrap circuit 104 causing the first and second capacitive couplings to be formed. In various examples, the gate-source voltage of the NMOS transistor 112 may be maintained at V.sub.dd. The gate-source voltage of the PMOS transistor 114 may be maintained at V.sub.dd. Maintaining the gate-source voltage at the first and second constant levels may reduce signal leakage, such as sub-threshold leakage, associated with rise and fall times of the input signal, increase the drive gain of the CMOS pass gate circuit 110, and reduce a switching time associated with signal transitions of the input signal.
[0041]
[0042] In various examples, the control circuit 202 may be a memory device for configuring one or more FPGAs, such as a RAM, SRAM, serial SRAM, NVRAM, SPI flash memory, NVSRAM, or other NVM type circuit, without limitation. The control circuit 202 may configure or reprogram one or more reprogrammable devices, such as an FPGA, FPSLIC, or PLD, without limitation. The control circuit 202 may be electrically connected to one or more power supplies 224. The one or more power supplies 224 may provide electric power to the control circuit 202. In various examples, the one or more power supplies 224 connected to the control circuit 202 may or may not be the same as the one or more power supplies 224 electrically connected to the bootstrap circuit 204. In various examples, the one or more power supplies 224 may be a voltage rail or voltage bus, without limitation.
[0043] In various examples, the CMOS pass gate circuit 210 includes a first n-channel transistor 212 and a first p-channel transistor 214. The first n-channel transistor 212 may be an NMOS transistor and the first p-channel transistor 214 may be a PMOS transistor. In various examples, the bootstrap circuit 204 includes a second p-channel transistor 206 and a second n-channel transistor 208. In various examples, the second p-channel transistor 206 may be a PMOS transistor and the second n-channel transistor 208 may be an NMOS transistor.
[0044] The PMOS transistor 206 includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the PMOS transistor 206 may be electrically connected to the one or more power supplies 224, as described above. The drain terminal of the PMOS transistor 206 may be electrically connected to the control circuit 202. The NMOS transistor 208 includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the NMOS transistor 208 may be electrically connected to the one or more power supplies 224, as described above. The drain terminal of the NMOS transistor 208 may be electrically connected to the control circuit 202. The gate, source, and drain terminals of the NMOS transistor 208 and PMOS transistor 206 are described in detail below with reference to
[0045] In various examples the NMOS transistor 212 includes a gate terminal, a source terminal, and a drain terminal. The PMOS transistor 214 includes a gate terminal, a source terminal, and a drain terminal. The source terminal of the PMOS transistor 214 and the source terminal of the NMOS transistor 212 may be electrically connected to the input terminal 216. The drain terminal of the PMOS transistor 214 and the drain terminal of the NMOS transistor 212 may be electrically connected to the output terminal 218. The gate, source, and drain terminals of the NMOS transistor 212 and PMOS transistor 214 are described in detail below with reference to
[0046] The control circuit 202 may include a control circuit output terminal 220. The control circuit 202 may generate a control signal for activating or deactivating the CMOS pass gate circuit 210. The control signal may be provided to the control circuit output terminal 220. The control signal may include a logic high value or a logic low value. The control signal may be split into a first signal path 225 and a second signal path 226. The second signal path 226 may include a logic inverter 222. The logic inverter 222 may invert the control signal from the logic high value to the logic low value, or vice versa. The second signal path 226 may provide a first complementary control signal to the bootstrap circuit 204. The first signal path 225 may provide a second complementary control signal to the bootstrap circuit 204. The first complementary control signal may activate or deactivate the NMOS transistor 212. The second complementary control signal may activate or deactivate the PMOS transistor 214. The control circuit output terminal 220 may convey the control signal to the first signal path 225 and the second signal path 226. The inverter 222 may invert the control signal received in the second signal path 226, such that the first signal path 225 provides the second complementary control signal, and the second signal path 226 provides the first complementary control signal, to the bootstrap circuit 204. The bootstrap circuit 204 may generate the first and second drive voltage in response to receiving the first and second complementary control signals and convey the first and second drive voltages to the CMOS pass gate circuit 210.
[0047] It would be appreciated by one of ordinary skill in the art that either the first signal path 225 or the second signal path 226 could include the logic inverter 222 without departing from the scope of the present disclosure. The logic inverter 222 may decrease power consumption, operating costs, and improve efficiency associated with the control circuit 202 by reducing the number of control signals produced by the control circuit 202. It should be understood that all features, concepts, structures and operations discussed throughout in connection with the examples shown in
[0048] In various examples, the first and second complementary control signals received by the NMOS transistor 208 and PMOS transistor 206, respectively, may have complementary values. In a first state, the first complementary control signal may include the logic low value and the second complementary control signal may include the logic high value. The first state of the control signal may activate the CMOS pass gate circuit 210. In a second state, the first complementary control signal may include the logic high value and the second complementary control signal may include the logic low value. The second state of the control signal may deactivate the CMOS pass gate circuit 210. In various examples, the logic high value may be equivalent to a source voltage V.sub.dd. The logic low value may be equivalent to a ground voltage. In various examples, the source voltage V.sub.dd may be 0.75V, 0.85V, 1.5V, or another voltage, without limitation. The ground voltage may be 0V, without limitation.
[0049] In various examples, PMOS transistor 206 and NMOS transistor 208 may be electrically connected to one or more power supplies 224. The one or more power supplies 224 may activate the bootstrap circuit 204. The one or more power supplies 224 may supply the source voltage V.sub.dd to a gate terminal of the NMOS transistor 208 and the ground voltage to a gate terminal of the PMOS transistor 206.
[0050] In various examples, the gate terminal of the NMOS transistor 212 may be electrically connected to the source terminal of the NMOS transistor 208. A first drive voltage corresponding to the first complementary control signal may be received at the gate terminal of the NMOS transistor 212. The NMOS transistor 208 of the bootstrap circuit 204 may receive the first complementary control signal and provide the first drive voltage to the NMOS transistor 212. The first drive voltage may correspond to the first complementary control signal. The bootstrap circuit 204 may increase a first drive gain of the NMOS transistor 208 based on, at least in part, the value of the first complementary control signal. The first complementary control signal may activate or deactivate the NMOS transistor 212. The first complementary control signal having the high logic value may activate the NMOS transistor 212. The first complementary control signal having the low logic value may deactivate the NMOS transistor 212.
[0051] In various examples, the gate terminal of the PMOS transistor 214 may be electrically connected to the source terminal of the PMOS transistor 206. A second drive voltage corresponding to the second complementary control signal may be received at the gate terminal of the PMOS transistor 214. The PMOS transistor 206 of the bootstrap circuit 204 may receive the second complementary control signal and provide the second drive signal to the PMOS transistor 214. The second drive voltage may correspond to the second complementary control signal. In various examples, the second complementary control signal having the low logic value may activate the PMOS transistor 214. The second complementary control signal having the high logic value may deactivate the PMOS transistor 214.
[0052] It would be appreciated by one of ordinary skill in the art that the source and drain terminals of the PMOS transistors 206, 214, and the NMOS transistors 208, 212, may be interchangeable as a function of a voltage difference between the respective gate terminals and the respective source or drain terminals. In various examples, respective bias voltages applied to the PMOS transistors 206, 214 and the NMOS transistors 208, 212 may cause the PMOS transistors 206, 214 and the NMOS transistors 208, 212 to operate in a forward biased state or reverse biased state, depending on whether a respective gate voltage is higher or lower than a the source or drain voltage, without departing from the scope of the present disclosure. In various examples, the PMOS transistors 206, 214 and the NMOS transistors 208, 212 may be FinFETs, without limitation.
[0053] In various examples, the bootstrap circuit 204 may increase respective drive gains of the NMOS transistor 212 and the PMOS transistor 214. The PMOS transistor 206 and the NMOS transistor 208 may control an amount of voltage supplied to the gate terminals of the PMOS transistor 214 and the NMOS transistor 212, respectively. The NMOS transistor 208 and the PMOS transistor 206 may continuously receive power from the one or more power supplies 224 and may provide the first and second drive voltages to the NMOS transistor 212 and the PMOS transistor 214 in response to receiving the first and second complementary control signals. The NMOS transistor 208 and the PMOS transistor 206 may cause first and second capacitive couplings to form across the respective gate and source terminals of the NMOS transistor 212 and the PMOS transistor 214, respectively, in response to signal transitions of the input signal.
[0054] The signal transitions of the input signal may include a rise and a fall. The rise may correspond to a voltage increase of the input signal. In various examples, the input signal may rise from a low voltage level to a high voltage level. The high voltage level may be greater than the low voltage level. In various examples, the high voltage level may correspond to a source voltage V.sub.dd, without limitation. In various examples, the low voltage level may be equivalent to a ground voltage, or 0V, without limitation. The fall may correspond to a voltage decrease of the input signal. The decrease may be from the high voltage level to the low voltage level. The rise may be associated with a rise time. The rise time may correspond to a time period beginning when the input signal begins increasing in voltage from the low voltage level and ending when the input signal reaches the high voltage level. The fall time may correspond to a time period beginning when the input signal begins decreasing in voltage from the high voltage level and ending when the input signal reaches the low voltage level. In various examples, the input signal may be received at the input terminal 216. In various examples, the input signal may be a continuous signal, without limitation.
[0055] The first capacitive coupling may be formed between the gate and source terminals of NMOS transistor 212 in response to receiving the first drive voltage at the NMOS transistor 212. The first drive voltage may be supplied to the NMOS transistor 212 before the input signal is received. The NMOS transistor 208 may shut off after supplying the drive voltage to the NMOS transistor 212 due to equivalent gate voltages at the NMOS transistors 208, 212. The shut off of the NMOS transistor 208 may trap a charge at the gate of the NMOS transistor 212, causing the first capacitive coupling to form. When the input signal is received, the capacitive coupling may cause the gate voltage of the NMOS transistor 212 to increase and decrease by a same amount as, or proportional to, the rise and fall of the input signal. The increase and decrease of the gate voltage of the NMOS transistor 212 in proportion to the input signal may cause a first constant voltage value to be maintained across the gate and source terminals of the NMOS transistor 212. Accordingly, signal leakage associated with the rise and fall times of the input signal may be minimized and switching times may be reduced.
[0056] The second capacitive coupling may be formed between the gate and source terminals of PMOS transistor 214 in response to receiving the second drive voltage at the PMOS transistor 214. The second drive voltage may be supplied to the PMOS transistor 214 before the input signal is received. The PMOS transistor 206 may shut off after supplying the second drive voltage to the PMOS transistor 214 due to equivalent gate voltages at the PMOS transistors 206, 214. The shut off of the PMOS transistor 208 may trap a charge at the gate of the PMOS transistor 214, causing the second capacitive coupling to form. When the input signal is received, the second capacitive coupling may cause the gate voltage of the PMOS transistor 214 to increase and decrease by a same amount, or in proportion to, the rise and fall of the input signal. The increase and decrease of the gate voltage of the PMOS transistor 214 in proportion to the input signal may cause a second constant voltage value to be maintained across the gate and source terminals of the PMOS transistor 214. Accordingly, signal leakage associated with the rise and fall times of the input signal may be minimized and switching times may be reduced.
[0057] The respective capacitive couplings may cause respective gate voltages of the NMOS transistor 212 and the PMOS transistor 214 to increase or decrease in proportion to the rise and fall of the input signal received at the input terminal 216. More specifically, as the input signal increases from 0V to V.sub.dd, the respective gate voltages of the NMOS transistor 212 and the PMOS transistor 214 may increase by the same amount as the input signal, or V.sub.dd. If the input signal decreased from Vdd to 0V The respective gate voltages of the NMOS transistor 212 and the PMOS transistor 214 may decrease by the same amount, or V.sub.dd.
[0058] In various examples, the input signal may initially be at the low voltage level and the gate voltage of the NMOS transistor 212 may be equivalent to the source voltage V.sub.dd due to the first drive voltage from the bootstrap circuit 204. As described above, after supplying the first drive voltage, the NMOS transistor 208 may be turned off before the input signal is received, causing a first charge to be trapped at the gate of the NMOS transistor 212. The first trapped charge may cause the first capacitive coupling to form. As the input signal rises from the low voltage level to the high voltage level, the first capacitive coupling causes the gate voltage of the NMOS transistor 212 to increase in proportion to the rise of the input signal. As the input signal reaches the source voltage V.sub.dd, the gate voltage of the NMOS transistor 212 may be 2V.sub.dd. Accordingly, the first capacitive coupling may maintain the first constant voltage value across the source and gate terminals of the NMOS transistor 212.
[0059] When the input signal begins to fall from V.sub.dd to 0V, the gate voltage of the PMOS transistor 214 may be equal to 0V and may decrease in proportion to the fall of the input signal. As described above, after supplying the second drive voltage, the PMOS transistor 206 may be turned off before the input signal is received, causing a second charge to be trapped at the gate of the PMOS transistor 214. The second trapped charge may cause the second capacitive coupling to form. As the input signal falls, the gate voltage of the PMOS transistor 214 may decrease, or be coupled down, by an amount of voltage equivalent to the fall of the input signal. As the input signal reaches 0V, the gate voltage of the PMOS transistor 214 may be V.sub.dd. Accordingly, the second capacitive coupling may maintain the second constant voltage value across the source and gate terminals of the NMOS transistor 212.
[0060] In various examples, the NMOS transistor 212 and the PMOS transistor 214 are being over-driven as the input signal rises and falls by the first and second capacitive couplings formed in response to receiving the first and second drive voltages. First and second gate-source voltages V.sub.gs, of the NMOS transistor 212 and the PMOS transistor 214 may be maintained at the first and second constant voltage levels, respectively, due to the first and second drive voltages from the bootstrap circuit 204 causing the first and second capacitive couplings to be formed. In various examples, the gate-source voltage of the NMOS transistor 212 may be maintained at V.sub.dd. The gate-source voltage of the PMOS transistor 214 may be maintained at V.sub.dd. Maintaining the gate-source voltage at the first and second constant levels may reduce signal leakage, such as sub-threshold leakage, associated with rise and fall times of the input signal, increase the drive gain of the CMOS pass gate circuit 210, and reduce a switching time associated with signal transitions of the input signal.
[0061]
[0062] It would be appreciated by one of ordinary skill in the art that the source terminals 308, 316 may respectively be interchangeable with the drain terminals 306, 316, as a function of a voltage difference between the respective gate terminals and the respective source or drain terminals. In various examples, respective bias voltages applied to the NMOS transistor 302 and the PMOS transistor 310 may cause the he NMOS transistor 302 and the PMOS transistor 310 operate in a forward biased state or reverse biased state, depending on whether a respective gate voltage is higher or lower than a the source or drain voltage, without departing from the scope of the present disclosure. In various examples, the NMOS transistor 302 and the PMOS transistor 310 may be FinFETs, without limitation.
[0063] In various examples, the source terminals 308, 316 may be electrically connected to an input terminal 318. The drain terminals 306, 314 may be electrically connected to an output terminal 320. The CMOS pass gate circuit 300 may receive an input signal at the input terminal 318 and provide an output signal to the output terminal 320 when the NMOS transistor 302 and the PMOS transistor 310 are activated.
[0064] The gate terminals 304, 312 may be electrically connected to a bootstrap circuit, such as the bootstrap circuit 110 (shown in
[0065] In various examples, the first and second drive voltages from the bootstrap circuit may be received at the gate terminals 304, 312. The first and second drive voltages may cause the first and second capacitive couplings to be formed between the gate terminals 304, 312, and the source terminals 308, 316, respectively, as described above with reference to
[0066] As described above with reference to
[0067]
[0068] In various examples, the bootstrap circuit 401 may include a PMOS transistor 404 and an NMOS transistor 412. The PMOS transistor 404 may include a gate terminal 406, a drain terminal 408, and a source terminal 410. The NMOS transistor 412 may include a gate terminal 414, a drain terminal 416, and a source terminal 418. The drain terminals 408, 416 may be electrically connected to the control circuit 402. The source terminals 410, 418 may be electrically connected to the CMOS pass gate circuit. The gate terminals 406, 414 may be electrically connected to the one or more power supplies 424. In various examples, the one or more power supplies 424 may be a voltage rail or voltage bus, without limitation.
[0069] The gate terminals 406, 414 may receive electric power from the one or more power supplies 424. In various examples, the one or more power supplies 424 may activate the bootstrap circuit 401 by supplying 0V the gate terminal 406 of the PMOS transistor 404 and the source voltage V.sub.dd to the gate terminal 414 of the NMOS transistor 412. Upon receiving electric power at the gate terminals 406, 414, the bootstrap circuit 401 may be activated. The bootstrap circuit 401 may receive complementary control signals from the control circuit 402 at the drain terminals 408, 416. The source terminals 410, 418 may provide the first and second drive voltages to the CMOS pass gate circuit in response to receiving the complementary control signals. As described above with reference to
[0070] In various examples, the source voltage V.sub.dd may be supplied to the gate terminal 414 by the one or more power supplies 424. The ground voltage or 0V may be supplied to the gate terminal 406 by the one or more power supplies 424. The source terminal 418 may provide the first drive voltage to the CMOS pass gate circuit. The source terminal 410 may provide the second drive voltage to the CMOS pass gate circuit.
[0071] It would be appreciated by one of ordinary skill in the art that the source terminals 410, 418 may be interchangeable with the drain terminals 408, 416, respectively, as a function of a voltage difference between the respective gate terminals and the respective source or drain terminals. In various examples, respective bias voltages applied to the NMOS transistor 412 and the PMOS transistor 404 may cause the NMOS transistor 412 and the PMOS transistor 404 to operate in a forward biased state or reverse biased state, depending on whether a respective gate voltage is higher or lower than the source or drain voltage, without departing from the scope of the present disclosure. In various examples, the NMOS transistor 412 and the PMOS transistor 404 may be FinFETs, without limitation.
[0072]
[0073] The input signal voltage 502 may correspond to one or more voltage levels of an input signal, such as the input signal received at the input terminal 116, the input terminal 216, or the input terminal 318. The input signal may alternate between the ground voltage and the source voltage V.sub.dd. In various examples, the input signal may be associated with a rise time and a fall time. The rise time may correspond to a time period in which the signal increases from the ground voltage to V.sub.dd. The fall time may correspond to a time period in which the signal decreases from V.sub.dd to the ground voltage. It would be appreciated by one of ordinary skill in the art that although the voltage rise and fall of the input signal are shown to be instantaneous in the form of a square wave, the voltage rise and fall of the input signal would not be instantaneous in practice.
[0074] The NMOS transistor gate voltage 504 illustrates one or more gate voltage levels of the first n-channel transistor of the CMOS pass gate circuit. The NMOS transistor gate voltage 504 may be equal to the source voltage V.sub.dd when the input signal voltage 502 is at the ground voltage, due to the first drive voltage received from the bootstrap circuit. In various examples, the ground voltage may be 0V. In various examples, the first drive voltage may be equal to the source voltage V.sub.dd. As described above with reference to
[0075] The PMOS transistor gate voltage 506 illustrates one or more gate voltage levels of the first p-channel transistor of the CMOS pass gate circuit. In various examples, the first p-channel transistor may correspond to the PMOS transistor 114, the PMOS transistor 214, or the PMOS transistor 310, without limitation. The PMOS transistor gate voltage 506 may be equal to V.sub.dd when the input signal voltage decreases to the ground voltage, due to a second capacitive coupling formed between gate and source terminals of the first p-channel transistor in response to receiving the second drive voltage from the bootstrap circuit, as described above with reference to
[0076]
[0077] At operation 604, the bootstrap circuit may activate the CMOS pass gate circuit. The control circuit may generate one or more control signals for activating the CMOS pass gate circuit, as described in reference to
[0078] At operation 606, an input signal may be received by the first n-channel transistor and first p-channel transistor. In various examples, the input signal may be received at respective source terminals of the first n-channel transistor and first p-channel transistor. As noted above, the source and drain terminals of the first n-channel transistor and first p-channel transistor may be interchangeable as a function of respective bias voltages applied to gate terminals of the first n-channel transistor and first p-channel transistor, without limitation. The input signal may have or vary between a low voltage level and a high voltage level. The low voltage level may correspond to a ground voltage or 0V, without limitation. The high voltage level may correspond to a source voltage V.sub.dd. The input signal may be associated with a rise period and a fall period. The rise period may correspond a first transition time in which the voltage of the input signal increases from the low voltage level to the high voltage level. The fall period may correspond to a second transition time in which the voltage of the input signal decreases from the high voltage level to the low voltage level.
[0079] At operation 608, the bootstrap circuit may increase a drive gain of the CMOS pass gate circuit. The second n-channel transistor may provide the first drive voltage to the first n-channel transistor based on the one or more control signals received from the control circuit. The first drive voltage may be received at the gate terminal of the first n-channel transistor. The second p-channel transistor may provide the second drive voltage to the first p-channel transistor. The second drive voltage may be received at the gate terminal of the first p-channel transistor.
[0080] A first capacitive coupling may be generated between the gate and source terminals of the first n-channel transistor in response to receiving the first drive voltage at the first n-channel transistor. The first capacitive coupling may cause a gate voltage of the first n-channel transistor to increase during each rise period. The first capacitive coupling may cause the gate voltage of the first n-channel transistor to decrease during each fall period. The increase and decrease of the gate voltage may be proportional to voltage increases and decreases of the input signal. The first capacitive coupling may cause a gate-source voltage of the first n-channel transistor to be maintained at a constant level during each rise period and fall period. Additionally, the gate-source voltage may be maintained at the constant level at all times during operation of the CMOS pass gate device.
[0081] A second capacitive coupling may be generated between the gate and source terminals of the first p-channel transistor in response to receiving the second drive voltage at the second p-channel transistor. The second capacitive coupling may cause a gate voltage of the first p-channel transistor to increase during each rise period. The second capacitive coupling may cause the gate voltage of the first p-channel transistor to decrease during each fall period. The increase and decrease of the gate voltage may be proportional to voltage increases and decreases of the input signal. The second capacitive coupling may cause a gate-source voltage of the first p-channel transistor to be maintained at a constant level during each rise period and fall period. Additionally, the gate-source voltage may be maintained at the constant level at all times during operation of the CMOS pass gate device.
[0082] The first and second drive voltages may cause the first n-channel transistor and first p-channel transistor to be over-driven when an input signal is received, thereby increasing a drive gain of the CMOS pass gate circuit. As a result, sub-threshold leakage associated with the rise and fall periods of the input signal may be significantly reduced. Furthermore, providing the first and second drive voltages to the CMOS pass gate circuit by the bootstrap circuit of the present disclosure may reduce an amount of time associated with activating the transistors of the CMOS pass gate circuit, thereby improving an overall efficiency of the CMOS pass gate circuit while maintaining low power consumption.
[0083] As discussed in more detail above, the CMOS device may receive the input signal from an input device and provide an output signal to an output device, pursuant to the operations of method 600. The output signal may include data to be provided to the output device. In various examples, the input device and output device may be an FPGA, FPSLIC, PLD, one or more multiplexors, or another type of reprogrammable device, without limitation. In various examples, the input device and the output device may be respective CMOS devices. In various examples, the CMOS device, the input device, and the output device may be integrated into a single reprogrammable device.
[0084] According to various examples of the present disclosure, an apparatus is provided that includes a CMOS pass gate circuit, a control circuit, and a bootstrap circuit. The CMOS pass gate circuit may include a first n-channel transistor and a first p-channel transistor. The control circuit may generate control signals to activate the CMOS pass gate circuit. The bootstrap circuit may be electrically connected between the CMOS pass gate circuit and the control gate circuit. The bootstrap circuit may increase a first drive gain of the first n-channel transistor and a second drive gain of the first p-channel transistor.
[0085] In combination with any of the above examples, the bootstrap circuit may include a second n-channel transistor and a second p-channel transistor. The second n-channel transistor may be electrically connected between the control circuit and the first n-channel transistor. The second p-channel transistor may be electrically connected between the control circuit and the first p-channel transistor. The second n-channel transistor may receive a first complementary control signal of the control signals and convey a first drive voltage corresponding to the first complementary control signal to the first n-channel transistor. The first drive voltage may increase the first drive gain of the first n-channel transistor. The second p-channel transistor may receive a second complementary control signal of the control signals and convey a second drive voltage corresponding to the second complementary control signal to the first p-channel transistor. The second drive voltage may increase the second drive gain.
[0086] In combination with any of the above examples the one or more control signals may be a control signal. The control circuit may include an output having a first signal path and a second signal path. The control signal may be split between the first signal path and the second signal path. The first signal path may be electrically connected to the second p-channel transistor. The second signal path may be electrically connected to the second n-channel transistor. The second signal path may include an inverter. The inverter may invert a control signal of the complementary control signal to generate the first complementary control signal.
[0087] In combination with any of the above examples, the control signals may include the first complementary control signal and the second complementary control signal. The control circuit may include a first output connected to the second n-channel transistor and a second output electrically connected to the second p-channel transistor. The first output may convey the first complementary control signal to the second n-channel transistor. The second output may convey the second complementary control signal to the second p-channel transistor.
[0088] In combination with any of the above examples, the apparatus may include an input terminal electrically connected to the CMOS pass gate circuit. The input terminal may convey an input signal to the CMOS pass gate circuit. The input signal may alternate between a high voltage level and a low voltage level. Respective ones of the first p-channel transistor, first n-channel transistor, second p-channel transistor, and second n-channel transistor may include a respective gate terminal, a respective source terminal, and a respective drain terminal. A first capacitive coupling is formed between the gate and source terminals of the first n-channel transistor. A second capacitive coupling to form between the gate and source terminals of the first p-channel transistor. The first and second capacitive couplings may be generated based on the first and second drive voltages, respectively.
[0089] In combination with any of the above examples, the first and second capacitive couplings may increase a first gate voltage of the first n-channel transistor and a second gate voltage of the first p-channel transistor in proportion to a rise of the input signal.
[0090] In combination with any of the above examples, the first and second capacitive couplings may decrease a first gate voltage of the first n-channel transistor and a second gate voltage of the first p-channel transistor in proportion to a fall of the input signal.
[0091] In combination with any of the above examples, the gate terminal of the first p-channel transistor may be electrically connected to the source terminal of the second p-channel transistor. The gate terminal of the first n-channel transistor may be electrically connected to the source terminal of the second n-channel transistor. The source terminals of the first p-channel transistor and the first n-channel transistor may be electrically connected to the input terminal. The gate terminals of the second p-channel transistor and the second n-channel transistor may be electrically connected to one or more power supplies. The drain terminals of the second p-channel transistor and the second n-channel transistor may be electrically connected to the control circuit.
[0092] According to various examples of the present disclosure, a circuit arrangement may be provided. The circuit arrangement may include a complementary metal-oxide-semiconductor (CMOS) pass gate circuit and a bootstrap circuit. The bootstrap circuit may be electrically connected to the CMOS pass gate circuit. The bootstrap circuit may increase a drive gain of the CMOS pass gate circuit.
[0093] In combination with any of the above examples, the CMOS pass gate circuit may include a first n-channel transistor and a first p-channel transistor. The bootstrap circuit may include including a second n-channel transistor and a second p-channel transistor. The second n-channel transistor may be electrically connected to the first n-channel transistor. The second p-channel transistor may be electrically connected to the first p-channel transistor. The second n-channel transistor may convey a first drive voltage to the first n-channel transistor. The second p-channel transistor may convey a second drive voltage to the first p-channel transistor.
[0094] In combination with any of the above examples, the first p-channel transistor may include a gate terminal, a source terminal, and a drain terminal. The first n-channel transistor may include a gate terminal, a source terminal, and a drain terminal. The second p-channel transistor may include a gate terminal, a source terminal, and a drain terminal. The second n-channel transistor may include a gate terminal, a source terminal, and a drain terminal.
[0095] In combination with any of the above examples, the circuit may include an input terminal to receive an input signal. The input terminal may be electrically connected to the respective source terminals of the first n-channel transistor and the first p-channel transistor. A first capacitive coupling may be formed between the gate and source terminals of the first n-channel transistor by the first drive voltage. A second capacitive coupling may be formed between the gate and source terminals of the first p-channel transistor by the second drive voltage.
[0096] In combination with any of the above examples, a first gate-source voltage of the first n-channel transistor may have a first constant voltage value maintained by the first capacitive coupling. A second gate-source voltage of the first p-channel transistor may have a second constant voltage value maintained by the second capacitive coupling.
[0097] In combination with any of the above examples, the circuit arrangement may include a control circuit and an input terminal. The gate terminal of the first p-channel transistor may be electrically connected to the source terminal of the second p-channel transistor. The gate terminal of the first n-channel transistor may be electrically connected to the source terminal of the second n-channel transistor. The source terminals of the first p-channel transistor and the first n-channel transistor may be electrically connected to the input terminal. The gate terminals of the second p-channel transistor and the second n-channel transistor may be electrically connected to one or more power supplies. The drain terminals of the second p-channel transistor and the second n-channel transistor may be electrically connected to the control circuit.
[0098] According to various examples of the present disclosure, a method is provided. One or more power supplies may activate a bootstrap circuit. A control circuit may generate one or more control signals. A complementary metal-oxide-semiconductor (CMOS) pass gate circuit may be activated by the bootstrap circuit based on the one or more control signals. The CMOS pass gate circuit may receive an input signal. The bootstrap circuit may increase a drive gain of the CMOS pass gate circuit.
[0099] In combination with any of the above examples, a first drive voltage corresponding to a first complementary control signal of the one or more control signals may be received by a first n-channel transistor of the CMOS pass gate circuit from the bootstrap circuit. A second drive voltage corresponding to a second complementary control signal of the one or more control signals may be received by a first p-channel transistor of the CMOS pass gate circuit from the bootstrap circuit.
[0100] In combination with any of the above examples, a first capacitive coupling may be generated in response to receiving the first drive voltage at the first n-channel transistor. The first capacitive coupling may be generated between a gate terminal and a source terminal of the first n-channel transistor. A second capacitive coupling may be generated in response to receiving the second drive voltage at the first p-channel transistor. The second capacitive coupling may be generated between a gate terminal and a source terminal of the first p-channel transistor.
[0101] In combination with any of the above examples, increasing the drive gain of the CMOS pass gate circuit includes increasing a first gate voltage of the first n-channel transistor in response a rise in the input signal. The second capacitive coupling may decrease the second gate voltage in response to a fall in the input signal.
[0102] In combination with any of the above examples, the input signal may increase in voltage during a rise period and decrease in voltage during a fall period. Increasing the drive gain of the CMOS pass gate circuit includes maintaining a first constant voltage value of a first gate-source voltage of the first n-channel transistor and a second constant voltage value of a second gate-source voltage of the first p-channel transistor during the rise period and the fall period. The first capacitive coupling may maintain the first constant voltage value. The second capacitive coupling may maintain the second constant voltage value.
[0103] While the present disclosure has been described herein with respect to certain illustrated examples, those of ordinary skill in the art will recognize and appreciate that the present disclosure is not so limited. Rather, many additions, deletions, and modifications to the illustrated and described examples may be made without departing from the scope of the disclosure as hereinafter claimed along with their legal equivalents. In addition, features from one example may be combined with features of another example while still being encompassed within the scope of the disclosure as contemplated by the inventors.