Broad-area diode laser comprising integrated p-n tunnel junction
20250309616 ยท 2025-10-02
Inventors
- Paul CRUMP (Berlin, DE)
- Hans Wenzel (Berlin, DE)
- Mohamed ELATTAR (Berlin, DE)
- Andre Maassdorf (Berlin, DE)
- Dominik Martin (Berlin, DE)
- Olaf BROX (Berlin, DE)
Cpc classification
H01S5/2205
ELECTRICITY
International classification
H01S5/20
ELECTRICITY
H01S5/30
ELECTRICITY
H01S5/323
ELECTRICITY
Abstract
The present invention relates to a broad-area diode laser (BAL) comprising an integrated p-n tunnel junction. The present invention in particular relates to a high-performance broad-area diode laser in which, in order to improve the beam quality and to reduce the thermal resistance, a p-n tunnel junction, biased in the reverse direction, is integrated in the layer system of the diode laser.
A laser diode according to the invention comprises an active layer (20) formed between an n-doped semiconductor material (10, 12, 14) and a p-doped semiconductor material (30, 32, 34), the active layer (20) forming, along a longitudinal axis, an active zone for generating electromagnetic radiation; wherein at least one n-doped intermediate layer (50, 54) is arranged between an overlying p-side metal contact (52) and the p-doped semiconductor material (30, 32, 34), and, in the at least one n-doped intermediate layer (50, 54) in the region above the active zone, a p-n tunnel junction (40) being formed which is directly adjacent to the p-doped semiconductor material (30, 32, 34).
Claims
1. A laser diode, comprising: an active layer formed between an n-doped semiconductor material and a p-doped semiconductor material, the active layer forming, along a longitudinal axis, an active zone for generating electromagnetic radiation; wherein at least one n-doped intermediate layer is arranged between an overlying p-side metal contact and the p-doped semiconductor material, and, in the at least one n-doped intermediate layer in the region above the active zone, a p-n tunnel junction being formed which is directly adjacent to the p-doped semiconductor material.
2. The laser diode according to claim 1, wherein the p-n tunnel junction comprises a p.sup.+ tunnel layer arranged on the p-doped semiconductor material and an n.sup.+ tunnel layer arranged thereon.
3. The laser diode according to claim 1, wherein the p-n tunnel junction is arranged on a p-doped sub-contact layer of the p-doped semiconductor material.
4. The laser diode according to claim 1, wherein the p-n tunnel junction is arranged on a p-doped cover layer of the p-doped semiconductor material.
5. The laser diode according to claim 1, wherein an n-doped cover layer is arranged on the p-n tunnel junction.
6. The laser diode according to claim 1, wherein a stripe width of the diode laser is specified over a lateral width W of the p-n tunnel junction.
7. The laser diode according to claim 1, wherein the p-n tunnel junction is formed as a layer and a stripe width of the diode laser is specified over a lateral width W of an opening in an n-current shield introduced into the p-doped semiconductor material.
8. The laser diode according to claim 1, wherein the p-n tunnel junction is formed as a layer and a stripe width of the diode laser is specified over a lateral width W of a region between two adjacent deep implantation areas.
9. The laser diode according to claim 1, wherein the semiconductor material is based on GaAs.
10. The laser diode according to claim 1, wherein the minimum distance between the active layer and the p-n tunnel junction is less than 1.3 m.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The invention is described below with reference to exemplary embodiments and on the basis of the associated drawings, in which:
[0026]
[0027]
[0028]
[0029]
[0030]
[0031]
DETAILED DESCRIPTION OF THE DRAWINGS
[0032]
[0033] This embodiment of the invention can be provided by a two-stage epitaxy process having an etching step between these two stages. In a first growth step, the structure can be grown as far as the p-n tunnel junction 40. The tunnel junction layers (42, 44) can then be selectively etched away outside the stripe. Following subsequent epitaxial growth of the n-contact layer 50, a p-n junction is produced in the outer regions of the structure in the reverse direction, while the central p-n tunnel junction 40 facilitates the flow of current. This is a known method for current and optical limitation in surface-emitting lasers having vertical resonators (VCSELs).
[0034]
[0035] In this embodiment of the invention, the current confinement can likewise be achieved by a two-step epitaxy process having an etching step between these two steps. In this case, the power cut-off at the component edges is produced independently of the tunnel junction by the so-called (enhanced) self-aligned lateral structure. For this purpose, highly n-doped layers can be integrated in the vicinity of the underside of the p-side contact layer (i.e. the p-sub-contact layer 34), which results in a reverse-biased p-n junction. The first growth step ends after the growth of these layers. They can then be selectively etched away in the center in order to make a corresponding opening for the flow of current. The rest of the p-sub-contact layer 34 as well as the p-n tunnel junction 40 and the n-contact layer 50 can then be grown over the structured n-current shield 60.
[0036]
[0037] By contrast with the above-described exemplary embodiments, this embodiment can be produced by single-stage epitaxial growth, which reduces the complexity and thus costs of the production process. The current limitation is for example carried out by high-energy deep ion implantation at the edges of the component. This can prevent the flow of current by increasing the intermediate resistance and introducing point defects, at which carriers rapidly recombine. Deep implantation through the active zone effectively prevents current spreading and LCA, as a result of which the beam quality could be considerably improved, but the power and efficiency are significantly impaired. Therefore, an implantation profile that is dimensioned such that it ends above the active zone (e.g. within the p-cover layer) with regard to the total power is preferred.
[0038]
[0039] The substantial difference from the embodiment shown in
[0040]
[0041]
LIST OF REFERENCE SIGNS
[0042] 10 n-substrate (e.g. GaAs) [0043] 12 n-cover layer (n-side, e.g. AlGaAs) [0044] 14 n-waveguide layer (e.g. AlGaAs) [0045] 20 active layer (comprises active zone) [0046] 30 p-waveguide layer (e.g. AlGaAs) [0047] 32 p-cover layer (e.g. AlGaAs) [0048] 34 p-sub-contact layer (e.g. GaAs) [0049] 40 p-n tunnel junction [0050] 42 p.sup.+ tunnel layer (e.g. p.sup.+ GaAs) [0051] 44 n.sup.+ tunnel layer (e.g. n.sup.+ GaAs) [0052] 50 n-(sub-)contact layer (p-side, e.g. GaAs) [0053] 52 metal contact (p-side) [0054] 54 n-cover layer (p-side, e.g. AlGaAs) [0055] 60 n-current shield [0056] 70 deep implantation area [0057] W lateral width [0058] d.sub.res residual layer thickness