INTEGRATION METHOD FOR MODULARIZED SILICON-BASED HETEROGENEOUS PHOTOELECTRIC INTEGRATED ARCHITECTURE

Abstract

The present invention relates to an integration method for a modularized silicon-based heterogeneous photoelectric integrated architecture. According to the integration method, a modularized form is adopted, different functional units are used as individual unit modules, and then different types of integrated architectures are formed through customized increase and decrease in different usage scenarios. Among them, customized combinations of one unit module, two unit modules up to five unit modules can be adopted to construct up to 22 types of module-combined integrated architectures. By adopting a modularized solution, various functional materials can be easily selected and combined, thus improving a degree of freedom of integration and reducing costs.

Claims

1. An integration method for a modularized silicon-based heterogeneous photoelectric integrated architecture, wherein the integration method is used for integrating a modularized silicon-based heterogeneous photoelectric integrated architecture and comprises the following steps: S1, integrating an ultra-low-loss material module, a high-frequency material module, and an integrated circuit module on a first silicon wafer; S2, preparing a laser material module on a second silicon wafer, and performing wafer-level bonding on the first silicon wafer and the second silicon wafer; S3, thinning a substrate on the first silicon wafer; S4, extracting a redistribution layer electrode at a bonding interface of a third silicon wafer containing the integrated circuit module and the first silicon wafer to form a TSV-1; S5, connecting a metal electrode of a III-V laser device outwards to form a TSV-2; S6, preparing micro-bumps on the TSV-1 and the TSV-2 for packaging with a PCB, wherein the step S1 comprises: S11, selecting the first silicon wafer, and fabricating a passive optical device and a germanium device on top silicon of the first silicon wafer to obtain a silicon photonic module; S12, providing the ultra-low-loss material module on the silicon photonic module, wherein the ultra-low-loss material module comprises a SiN device formed on the first silicon wafer by etching after SiN deposition; S13, heterogeneously bonding TFLN on the first silicon wafer, and etching the TFLN to form a TFLN device; S14, providing a plurality of layers of metal and vias on the germanium device and the TFLN device to form a metal electrode; and S15, performing wafer-level hybrid bonding on a third silicon wafer containing the integrated circuit module and the first silicon wafer, and removing a substrate of the first silicon wafer; the step S2 comprises: S21, fabricating a passive photonic device on the second silicon wafer; S22, providing a III-V group semiconductor epitaxial material on the second silicon wafer; S23, performing etching on the III-V group semiconductor epitaxial material to form a III-V laser device; and S24, fabricating a plurality of layers of metal and vias on the III-V laser device to form a metal electrode, wherein the step S22 comprises: heterogeneously bonding the III-V group semiconductor epitaxial material to the second silicon wafer by a wafer-to-wafer method or a chip-to-wafer method, wherein the III-V group semiconductor epitaxial material comprises an upper cladding layer, an active layer, and a lower cladding layer.

2. The integration method for a modularized silicon-based heterogeneous photoelectric integrated architecture according to claim 1, wherein the high-frequency material module comprises thin film lithium niobate capable of being heterogeneously bonded to a wafer of the silicon photonic module.

3. The integration method for a modularized silicon-based heterogeneous photoelectric integrated architecture according to claim 1, wherein the ultra-low-loss material module comprises a SiN device formed by etching after SiN deposition via PECVD or LPCVD.

4. The integration method for a modularized silicon-based heterogeneous photoelectric integrated architecture according to claim 1, wherein the wafer of the integrated circuit module is connected to the wafer of the silicon photonic module by bonding in a form of chip-to-wafer or wafer-to-wafer.

5. The integration method for a modularized silicon-based heterogeneous photoelectric integrated architecture according to claim 1, wherein the wafer of the laser material module is connected to the wafer of the silicon photonic module by bonding in a form of chip-to-wafer or wafer-to-wafer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0036] FIG. 1 is a schematic structural diagram of a silicon photonic module according to an embodiment of the present invention;

[0037] FIG. 2 is a schematic structural diagram of a high-frequency material module according to an embodiment of the present invention;

[0038] FIG. 3 is a schematic structural diagram of a laser material module according to an embodiment of the present invention;

[0039] FIG. 4 is a schematic structural diagram of an ultra-low-loss material module according to an embodiment of the present invention;

[0040] FIG. 5 is a schematic structural diagram of an integrated circuit module according to an embodiment of the present invention;

[0041] FIG. 6 is an initial structure of a first silicon wafer according to an embodiment of the present invention;

[0042] FIG. 7 is a schematic diagram of a structure after etching a passive photonic device in FIG. 6;

[0043] FIG. 8 is a schematic diagram of a structure after etching a SiN device in FIG. 7;

[0044] FIG. 9 is a schematic diagram of a structure after preparing a TFLN device in FIG. 8;

[0045] FIG. 10 is a schematic diagram of a structure after forming a metal electrode in FIG. 9;

[0046] FIG. 11 is a schematic diagram of a state in which a third silicon wafer and a first silicon wafer are subjected to wafer-level hybrid bonding;

[0047] FIG. 12 is a schematic diagram of a structure after removing a substrate of the first silicon wafer in FIG. 11;

[0048] FIG. 13 is a schematic diagram of an initial structure of a second silicon wafer;

[0049] FIG. 14 is a schematic diagram of a structure after etching a passive photonic device in FIG. 13;

[0050] FIG. 15 is a schematic diagram of a structure after heterogeneously bonding a III-V group semiconductor epitaxial material in FIG. 14;

[0051] FIG. 16 is a schematic structure of a structure in FIG. 15 after stepwise etching the III-V group semiconductor epitaxial material to form a III-V laser device;

[0052] FIG. 17 is a schematic diagram of a structure after forming a metal electrode of an upper cladding layer and a lower cladding layer in FIG. 16;

[0053] FIG. 18 is a schematic diagram of a state in which a second silicon wafer and a first silicon wafer are aligned for wafer-level bonding;

[0054] FIG. 19 is a schematic diagram of a structure after implementing steps S4 and S5 in FIG. 18;

[0055] FIG. 20 is a schematic diagram of a structure after implementing step S6 in FIG. 19; and

[0056] FIG. 21 is a schematic diagram of a structure after forming micro-bumps in FIG. 20.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0057] To facilitate understanding, the present application will be described in more detail below with reference to the accompanying drawings. Embodiments of the present application are provided in the accompanying drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present application. The terms used in the specification of the present application are only intended for describing specific embodiments rather than limit the present application.

[0059] It can be understood that spatial relationship terms such as below, under, lower, beneath, above, upper, etc. can be used herein to describe the relationship between an element or feature shown in the figures and other elements or features. It should be appreciated that in addition to orientations shown in the figures, the spatial relationship terms also encompass different orientations of devices in use and in operation. For example, if the devices in the figures are flipped, elements or features described as being under other elements or beneath or below other elements or features would then be oriented as being above the other elements or features. Therefore, exemplary terms under and below may include both upper and lower orientations. In addition, the devices may also be oriented in other ways (e.g., rotated 90 degrees or at other orientations), and the spatial description terms used herein should be interpreted accordingly.

[0060] It should be noted that when an element is considered to be connected to another element, it can be either directly connected to the other element or connected to the other element through a centered element. For the term connection in the following embodiments, if the connected circuits, modules, units, etc. transmit electrical signals or data to each other, connection should be understood as electrical connection or communication connection, etc.

[0061] As used herein, the singular forms a, an, and said/the may also include plural forms unless the context clearly indicates otherwise. It should also be understood that the terms comprise/include or have, etc. specify the existence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the existence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0062] As shown in FIG. 1, the present application first discloses a modularized silicon-based heterogeneous photoelectric integrated architecture, which consists of a single unit module or is formed by at least two unit modules through wafer-level silicon-based photoelectric heterogeneous integration.

[0063] According to the requirements of silicon photonic integration, the unit module includes any one of a silicon photonic module 100, a high-frequency material module 200, a laser material module 300, an ultra-low-loss material module 400, or an integrated circuit module 500, where types of different unit modules in the same integrated architecture are different from each other.

[0064] The silicon photonic module 100 refers to a wafer which is fabricated using an SOI wafer with a top silicon thickness of approximately 200-300 nm and contains a silicon photonic device; the high-frequency material module 200 generally refers to a wafer which is fabricated using materials such as TFLN (thin film lithium niobate) and BTO (lithium carbonate) and contains a high-frequency modulation device; the laser material module 300 generally refers to a wafer which is fabricated using III-V group compound semiconductor materials such as InP and GaAs and contains a laser device and an amplifier device; the ultra-low-loss material module 400 generally refers to a wafer which is fabricated using dielectric materials such as SiN and SiON and contains an ultra-low-loss optical waveguide; and the integrated circuit module 500 generally refers to a wafer which is fabricated using materials such as Si, SiC, and GaN and contains an integrated circuit device.

[0065] As shown in FIG. 1, the silicon photonic module 100 includes a first silicon wafer 10, the first silicon wafer 10 is composed of a silicon substrate and a silicon dioxide buried compound, and the silicon buried compound contains a passive photonic device and an interconnect metal 16 serving as optical information transmission channels therein, where the passive photonic device includes a grating 11, a waveguide 12, and a modulator 13 which are formed by a plurality of Si etchings at different depths as well as a germanium device which is formed by local opening and germanium epitaxial growth, specifically, the germanium device includes germanium (Ge) and a germanium detector 15.

[0066] FIG. 2 shows a basic structure of the high-frequency material module 200. In this embodiment, the high-frequency material is illustrated by TFLN (thin film lithium niobate), and includes a passive photonic device formed on a corresponding silicon wafer by TFLN etching, specifically including a lithium niobate grating 21, a lithium niobate waveguide 22, and a lithium niobate modulator 23, where a metal electrode is connected to the lithium niobate modulator 23.

[0067] FIG. 3 shows a schematic diagram of a basic structure of the laser material module 300. The III-V module 300 includes a III-V laser device formed by etching a III-V group semiconductor epitaxial material; a metal electrode 35 is connected to the III-V laser device; and the III-V group semiconductor epitaxial material includes an upper cladding layer 31, an active layer 32, and a lower cladding layer 33, where the III-V laser device is formed by stepwise etching the III-V group semiconductor epitaxial material.

[0068] FIG. 4 shows a schematic diagram of a basic structure of the ultra-low-loss material module 400. The ultra-low-loss material module includes a SiN device which is formed on a corresponding silicon wafer and is made of a SiN material, and may specifically include a SiN grating 41, a SiN waveguide 42, and a SiN coupler 43, where the SiN material may be SiOxNy.

[0069] FIG. 5 is a schematic diagram of a basic structure of the integrated circuit module 500.

[0070] It can be understood that in the present application, each individual unit module is prepared into a predetermined silicon wafer with specific functional devices. When a combination is required, the silicon wafers of different modules can be combined based on wafer-level silicon-based photoelectric heterogeneous integration.

[0071] According to the silicon-based heterogeneous photoelectric integrated architecture provided by this embodiment, a modularized form is adopted, different functional units are used as individual unit modules, and then different types of integrated architectures are formed through customized increase and decrease in different usage scenarios. Among them, customized combinations of one unit module, two unit modules up to five unit modules can be adopted to construct up to 22 types of module-combined integrated architectures. By adopting a modularized solution, various functional materials can be easily selected and combined, thus improving a degree of freedom of integration and reducing costs.

[0072] The following 22 types of module combinations are obtained after combining different unit modules and eliminating other combinations that are less practical, as shown in Table 1: List of Implementable Silicon-based Heterogeneous Photoelectric Integrated Architectures.

TABLE-US-00001 TABLE 1 List of Implementable Silicon-based Heterogeneous Photoelectric Integrated Architectures Integrated Silicon architecture photonic 1 module Integrated Silicon High-frequency architecture photonic material 2 module module Integrated Silicon Ultra-low- architecture photonic loss 3 module module Integrated Silicon High-frequency Ultra-low- architecture photonic material loss 4 module module module Integrated Silicon High-frequency Laser Ultra-low- architecture photonic material material loss 5 module module module module Integrated Silicon High-frequency Laser Ultra-low- Integrated architecture photonic material material loss circuit 6 module module module module module Integrated Silicon High-frequency Ultra-low- Integrated architecture photonic material loss circuit 7 module module module module Integrated Silicon Laser Ultra-low- architecture photonic material loss 8 module module module Integrated Silicon Laser Ultra-low- Integrated architecture photonic material loss circuit 9 module module module module Integrated Silicon Ultra-low- Integrated architecture photonic loss circuit 10 module module module Integrated Silicon Laser architecture photonic material 11 module module Integrated Silicon Integrated architecture photonic circuit 12 module module Integrated Laser architecture material 13 module Integrated High-frequency Laser Integrated architecture material material circuit 14 module module module Integrated High-frequency Laser architecture material material 15 module module Integrated Laser Ultra-low- architecture material loss 16 module module Integrated High-frequency architecture material 17 module Integrated High-frequency Ultra-low- architecture material loss 18 module module Integrated High-frequency Ultra-low- Integrated architecture material loss circuit 19 module module module Integrated Integrated architecture circuit 20 module Integrated Ultra-low- architecture loss 21 module Integrated Integrated architecture circuit 22 module

[0073] To provide a more comprehensive understanding of the integrated architectures in the present application, the embodiments of the present application are illustrated with the most complex integrated architecture 6 containing five unit modules.

[0074] To facilitate fabrication, the silicon photonic module 100, the ultra-low-loss module 400, and the high-frequency material module 200 are first integrated onto a silicon wafer, that is, the first silicon wafer. Specifically, the ultra-low-loss material module 400 includes a SiN device formed on the first silicon wafer by etching after SiN deposition via PECVD or LPCVD, and thin film lithium niobate is heterogeneously bonded onto the first silicon wafer; and interconnect metals are formed on both the high-frequency material module 200 and the germanium device.

[0075] A third silicon wafer corresponding to the integrated circuit module 500 and the first silicon wafer are subjected to wafer-level hybrid bonding.

[0076] Next, the laser material module 300 utilizes a second silicon wafer, a III-V laser device coupling region is formed in the second silicon wafer, a III-V group semiconductor epitaxial material is heterogeneously bonded to the second silicon wafer, and the III-V group semiconductor epitaxial material includes an upper cladding layer, an active layer, and a lower cladding layer distributed in a single stacked manner. The III-V laser device is formed by stepwise etching the III-V group semiconductor epitaxial material. The III-V module 300 and the SOI silicon photonic module form an integrated architecture through wafer-level bonding.

[0077] Specifically, an integration approach for the integrated architecture includes the following steps: [0078] S1, integrating a silicon photonic module, an ultra-low-loss material module, a high-frequency material module, and an integrated circuit module on a first silicon wafer, where [0079] the step S1 includes: [0080] S11, selecting the first silicon wafer, and fabricating a passive optical device and a germanium device on top silicon of the first silicon wafer;

[0081] FIG. 6 shows an initial structure of the first silicon wafer 10, including a Si substrate 101, a buried oxide BOX, and a top silicon layer 103, where a BOX layer has a thickness of 2-4 m, and the top silicon layer has a thickness of approximately 200-350 nm.

[0082] The passive photonic device such as a waveguide 12 and a grating 11 is formed by adopting multi-step Si etching and a plurality of Si etchings at different depths, as shown in FIG. 7.

[0083] S12, providing the ultra-low-loss material module on the first silicon wafer, where the ultra-low-loss material module includes a SiN device formed on the first silicon wafer by etching after SiN deposition; [0084] the SiN device is formed by etching after SiN deposition via PECVD or LPCVD, as shown in FIG. 8.

[0085] S13, heterogeneously bonding thin film lithium niobate on the first silicon wafer, and etching the thin film lithium niobate to form a high-frequency material module; [0086] through local opening and germanium epitaxial growth, a Ge device is formed and a tungsten (W) through via is prepared.

[0087] Metal is ohmic contacted by tungsten via, which is formed by SiO2 etching and silicide formation, and heterogeneous bonding of thin film lithium niobate (TFLN) is implemented by a wafer-to-wafer method or a chip-to-wafer method, where the TFLN can be replaced with other piezoelectric materials such as PZT in other embodiments, and a TFLN device is prepared by etching the TFLN, as shown in FIG. 9.

[0088] S14, providing a plurality of layers of metal and vias on the germanium device and the TFLN module to form a metal electrode; [0089] specifically, a plurality of layers of metals (divided into metal 1, metal 2, . . . , top metal by layer) and vias (via 1, . . . , top via) are fabricated by a damascene process, and a redistribution layer (RDL) for subsequent 3D packaging is prepared on the top metal, as shown in FIG. 10.

[0090] S15, performing wafer-level hybrid bonding on the third silicon wafer 30 containing a CMOS module and the first silicon wafer 10, as shown in FIG. 11, and removing the substrate of the first silicon wafer 10, as shown in FIG. 12, so that an architecture integrating a silicon photonic module, an ultra-low-loss material module, a high-frequency material module, and an integrated circuit module, i.e., the integrated architecture 7 in the table, is formed.

[0091] S2, preparing a laser material module on a second silicon wafer, where [0092] the step S2 includes: [0093] S21, fabricating a passive photonic device on the second silicon wafer 20;

[0094] FIG. 13 shows an initial structure of the second silicon wafer 20, which is structurally similar to the second silicon wafer 10. However, a thickness of a BOX layer of the second silicon wafer 20 is less than 100 nm, and a thickness of a top silicon layer thereof is 400-700 nm which is thicker than that of top silicon of a conventional silicon photonic wafer. This top silicon layer is mainly used for coupling with evanescent waves of the III-V laser device.

[0095] As shown in FIG. 14, the passive photonic device such as a silicon waveguide and a grating is formed by multi-step etching and a plurality of Si etchings at different depths, where a III-V laser device coupling region 24 is formed on the second silicon wafer 20.

[0096] S22, providing a III-V group semiconductor epitaxial material on the second silicon wafer; [0097] heterogeneous bonding of the III-V group semiconductor epitaxial material is implemented by a wafer-to-wafer method or a chip-to-wafer method, and the III-V group semiconductor epitaxial material includes InP, GaAs, and the like, where the III-V group semiconductor epitaxial material includes an upper cladding layer 31, an active layer 32 (i.e., quantum wells or quantum dots), and a lower cladding layer 33, as shown in FIG. 15.

[0098] S23, performing etching on the III-V group semiconductor epitaxial material to form a III-V laser device; [0099] the upper cladding layer, the active layer (i.e., quantum wells or quantum dots), and the lower cladding layer are stepwise etched to form the III-V laser device 34, as shown in FIG. 16.

[0100] S24, fabricating a plurality of layers of metal and vias on the III-V laser device to form a metal electrode.

[0101] The metal electrode 35 of the upper cladding layer 31 and the lower cladding layer 33 is formed by first depositing SiO2, followed by etching holes through SiO2 and filling with metal (such as Au or Ti), as shown in FIG. 17.

[0102] S3, performing wafer-level bonding on the first silicon wafer and the second silicon wafer.

[0103] The prepared second silicon wafer 20 as described above is bonded to a carrier wafer using an insulating bonding adhesive, and then the second silicon wafer 20 and the first silicon wafer 10 are aligned for wafer-level bonding, as shown in FIG. 18.

[0104] At this point, the integration of the integrated architecture 6 in the table is completed.

[0105] To facilitate packaging, based on the above steps, the integration method further includes: [0106] S4, thinning a substrate on the first silicon wafer 10; [0107] specifically, the substrate on the CMOS wafer side is thinned to approximately 10 m by grinding and etching.

[0108] S5, extracting a redistribution layer electrode at a bonding interface of a third silicon wafer containing the integrated circuit module and the first silicon wafer to form a TSV-1 (Through Silicon Via); [0109] specifically, as shown in FIG. 19, the through via is etched to penetrate the wafer, the RDL is used as a stop layer, metal Cu is filled to form the TSV-1, and a photoelectric RDL is extracted; [0110] S6, connecting a metal electrode of a III-V laser device outwards to form a TSV-2; [0111] specifically, the wafer is penetrated by through via etching, Au is used as the stop layer, metal Cu is filled to form the TSV-2, and an electrode of the III-V laser device is extracted; and Si is used as the stop layer, and metal Cu is filled to form a thermal shunt, as shown in FIG. 20; [0112] S7, preparing micro-bumps 50 on the TSV-1 and the TSV-2 for packaging with a PCB, as shown in FIG. 21, which is an overall architecture after preparation.

[0113] The foregoing descriptions are merely preferred embodiments of the present invention, but are not intended to limit the present invention. Any modification, equivalent replacement, or improvement made without departing from the spirit and principle of the present invention shall fall within the protection scope of the present invention.