METHODS FOR THE PRODUCTION OF CANNABINOID COMPOSITIONS

Abstract

A method for direct current (DC)-DC conversion. The method includes converting an input voltage to a set of output voltages by selecting a first output capacitor in a set of output capacitors of a DC-DC converter, charging an inductor of the DC-DC converter, and discharging an electric current passing through the inductor into the first output capacitor. The first output capacitor is selected responsive to a voltage level of the first output capacitor being less than a first reference voltage in a set of reference voltages. The inductor is charged by applying the input voltage to the inductor. The first output capacitor maintains a first output voltage in the set of output voltages.

Claims

1. A method for the production of a low-THC cannabinoid isolate comprising a target cannabinoid, the method comprising (i) providing an initial composition comprising at least one cannabinoid, wherein said at least one cannabinoid comprises THC and said at least one target cannabinoid, which target cannabinoid is a non-THC cannabinoid and wherein a concentration of said THC is between 0.1% and 10 wt % of a total cannabinoid content of said composition; (ii) partially separating said THC from said target cannabinoid, by a process selected to produce a first THC-enriched composition comprising a first fraction of said target cannabinoid and a first THC-depleted composition comprising a second fraction of said target cannabinoid, wherein (a) said first THC-enriched composition comprises at least 5% wt/wt of the content of said target cannabinoid in said initial composition, (b) a concentration of said THC wt/wt of total cannabinoids in said first THC-enriched composition is at least twice that in said initial composition, and (c) a concentration of said THC wt/wt of total cannabinoids in said first THC-depleted composition is less than one half that in said initial composition; (iii) selectively oxidizing at least 30% of said THC in said first THC-enriched composition to form a first oxidized composition comprising at least one oxidation product of THC, residual THC, and said target cannabinoid; (iv) at least partially recovering said target cannabinoid from said first oxidized composition; and (v) combining said first THC-depleted composition with at least a fraction of said target cannabinoid recovered from said first oxidized composition, wherein said low-THC cannabinoid isolate is formed, comprising said first THC-depleted composition and said target cannabinoid recovered from said first oxidation composition.

2. The method of claim 1, wherein said recovering comprises recycling at least a fraction of said first oxidized composition for further partially separating.

3. The method of claim 1, wherein said first THC-enriched composition, said THC-depleted composition or both comprise said oxidation product.

4. The method of claim 1, wherein said low-THC cannabinoid isolate comprises said oxidation product.

5. The method of claim 3, further comprising at least partially separating said oxidation product from at least one of said THC-enriched composition and said THC-depleted composition.

6. The method of claim 1, wherein said recovering comprises blending at least a fraction of said first oxidized composition with at least a fraction of said first THC-depleted composition to form a first blend, wherein said blend is said low-THC cannabinoid isolate.

7. The method of claim 1, wherein said recovering comprises at least partially separating said residual THC from said target cannabinoid and/or said oxidation product of THC in said oxidized composition, to form a second THC-enriched composition and a second THC-depleted composition, wherein said second THC-depleted composition comprises at least 50% wt/wt of the content of said target cannabinoid in said oxidized composition.

8. The method of claim 7, wherein said recovering further comprises blending at least a fraction of said second THC-depleted composition with at least a fraction of said first THC-depleted composition to form a second blend, wherein said second blend is said low-THC cannabinoid isolate.

9. The method of claim 1, further comprising selectively oxidizing at least 30% of said THC in said second THC-enriched composition to form a second oxidized composition.

10. The method of claim 1, wherein said target cannabinoid is selected from the group consisting of cannabidiol in acid or decarboxylated form (CBDa or CBD, respectively), cannabigerol in acid or decarboxylated form (CBGa or CBG, respectively), cannabichromene in acid or decarboxylated form (CBCa or CBC, respectively), tetrahydrocannabivarin in acid or decarboxylated form (THCVa or THCV, respectively), Cannabidivarin in acid or decarboxylated form (CBDVa or CBDV respectively) and cannabinol in acid or decarboxylated form (CBNa or CBN, respectively) and combinations thereof.

11. The method of claim 1, wherein said target cannabinoid is selected from the group consisting of CBD, CBDa and combinations thereof.

12. The method of claim 1, wherein said partially separating said THC from said target cannabinoid and/or said at least partially separating said residual THC from said target cannabinoid and/or said oxidation product of THC in said oxidized composition comprises use of a method selected from the group consisting of chromatographic separation, selective adsorption, crystallization, distillation and combinations thereof,

13. The method of claim 2, wherein said separating said oxidation product from at least one of said THC-enriched composition and said THC-depleted composition comprises use of a method selected from the group consisting of chromatographic separation, selective adsorption, crystallization, distillation and combinations thereof,

14. The method of claim 1, further comprising at least partially purifying at least one low-THC composition selected from the group consisting of said first THC-depleted composition, said second THC-depleted composition, said first oxidized composition, said second oxidized composition, said first blend and said second blend to provide an increase of at least 5% in a concentration of said target cannabinoid wt/wt of a total cannabinoid content with respect to said low THC composition.

15. The method of claim 14, wherein said at least partially purifying comprises use of a method selected from the group consisting of crystallization, distillation, chromatographic separation, selective adsorption and combinations thereof.

16. The method of claim 14, wherein said at least one cannabinoid in said initial composition comprises THCA, the method further comprising at least partially decarboxylating said THCA to THC prior to or subsequent to said selectively oxidizing.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawing figures depict one or more implementations in accord with the present teachings, by way of example only, not by way of limitation. In the figures, like reference numerals refer to the same or similar elements.

[0020] FIG. 1A shows a flowchart of a method for DC-DC conversion, consistent with one or more exemplary embodiments of the present disclosure.

[0021] FIG. 1B shows a flowchart of a method for selecting an output capacitor in a set of output capacitors, consistent with one or more exemplary embodiments of the present disclosure.

[0022] FIG. 1C shows a flowchart of a method for applying an input voltage to an inductor, consistent with one or more exemplary embodiments of the present disclosure.

[0023] FIG. 1D shows a flowchart of a method for applying an input voltage to an inductor, consistent with one or more exemplary embodiments of the present disclosure.

[0024] FIG. 1E shows a flowchart of a method for discharging an electric current into an output capacitor, consistent with one or more exemplary embodiments of the present disclosure.

[0025] FIG. 2A shows a schematic of a DC-DC converter, consistent with one or more exemplary embodiments of the present disclosure.

[0026] FIG. 2B shows a schematic of a DC-DC converter including a voltage divider and a comparator, consistent with one or more exemplary embodiments of the present disclosure.

[0027] FIG. 2C shows a schematic of a digital circuit, consistent with one or more exemplary embodiments of the present disclosure.

[0028] FIG. 3A shows control signals, an electric current, and output voltages for non-overlapped request signals, consistent with one or more exemplary embodiments of the present disclosure.

[0029] FIG. 3B shows control signals, an electric current, and output voltages for overlapped request signals, consistent with one or more exemplary embodiments of the present disclosure.

[0030] FIG. 3C shows an output voltage provided to a constant load, consistent with one or more exemplary embodiments of the present disclosure.

[0031] FIG. 3D shows a spectrum of an output voltage, consistent with one or more exemplary embodiments of the present disclosure.

[0032] FIG. 3E shows an output voltage provided to a variant load, consistent with one or more exemplary embodiments of the present disclosure.

[0033] FIG. 4 shows a high-level functional block diagram of a computer system, consistent with one or more exemplary embodiments of the present disclosure.

DESCRIPTION OF EMBODIMENTS

[0034] In the following detailed description, numerous specific details are set forth by way of examples in order to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings may be practiced without such details. In other instances, well known methods, procedures, components, and/or circuitry have been described at a relatively high-level, without detail, in order to avoid unnecessarily obscuring aspects of the present teachings.

[0035] The following detailed description is presented to enable a person skilled in the art to make and use the methods and devices disclosed in exemplary embodiments of the present disclosure. For purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that these specific details are not required to practice the disclosed exemplary embodiments. Descriptions of specific exemplary embodiments are provided only as representative examples. Various modifications to the exemplary implementations will be readily apparent to one skilled in the art, and the general principles defined herein may be applied to other implementations and applications without departing from the scope of the present disclosure. The present disclosure is not intended to be limited to the implementations shown, but is to be accorded the widest possible scope consistent with the principles and features disclosed herein.

[0036] Herein is disclosed an exemplary method for direct current (DC)-DC conversion. An exemplary method may include selecting an output capacitor of a DC-DC converter that requires charging to maintain an output voltage. An exemplary output capacitor may be selected when a voltage level of the output capacitor is smaller than a reference voltage of the output capacitor. When voltage levels of two or more output capacitors are less than respective reference voltages, the output capacitors may be prioritized to select an output capacitor with highest priority, that is, the output capacitor that is going to be charged first. After selecting an exemplary output capacitor, an inductor of the DC-DC converter may be charged by applying an input voltage to the inductor. Next, an electric current passing through the inductor may be discharged into the output capacitor with highest priority. To avoid drawing an excessive current from an exemplary output capacitor, transferred energy from a voltage source of the DC-DC converter to the output capacitor may be calculated, and when the transferred energy is larger than a threshold, the output capacitor may not be selected for charging. Similarly, to avoid drawing excessive current from the voltage source, a total transferred energy from the voltage source to all of output capacitors may be calculated, and when the total transferred energy is larger than a threshold, none of output capacitors may be selected. As a result, the transferred energy may decrease and the voltage source may be protected from overcurrent.

[0037] FIG. 1A shows a flowchart of a method for DC-DC conversion, consistent with one or more exemplary embodiments of the present disclosure. In an exemplary embodiment, a method 100 may include converting an input voltage to a set of output voltages by selecting an output capacitor in a set of output capacitors of a DC-DC converter (step 102), charging an inductor of the DC-DC converter (step 104), and discharging an electric current passing through the inductor into the output capacitor (step 106). In an exemplary embodiment, different steps of method 100 may be implemented utilizing a processor, facilitating a fully digital, programmable, and reconfigurable implementation of method 100. An exemplary fully digital implementation of method 100 may decrease a sensitivity of voltage conversion to process, voltage, and temperature (PVT) variations.

[0038] FIG. 2A shows a schematic of a DC-DC converter, consistent with one or more exemplary embodiments of the present disclosure. Referring to FIGS. 1A and 2A, in an exemplary embodiment, different steps of method 100 may be implemented utilizing a DC-DC converter 200. In an exemplary embodiment, DC-DC converter 200 may include a set of output capacitors 202 and an inductor L. In an exemplary embodiment, set of output capacitors 202 may include an output capacitor 204. In an exemplary embodiment, DC-DC converter may convert an input voltage V.sub.in to a set of output voltages 206. In an exemplary embodiment, method 100 may include a switching method for converting input voltage V.sub.in to set of output voltages 206. In an exemplary embodiment, DC-DC converter may include a processor 208. In an exemplary embodiment, processor 208 may turn on and off switches in DC-DC converter 200 by generating a respective control signal for each switch.

[0039] For further detail with respect to step 102, FIG. 1B shows a flowchart of a method for selecting an output capacitor in a set of output capacitors, consistent with one or more exemplary embodiments of the present disclosure. Referring to FIGS. 1B and 2A, in an exemplary embodiment, output capacitor 204 may be selected utilizing processor 208. In an exemplary embodiment, selecting output capacitor 204 may include generating a set of request signals (step 108) and selecting a first request signal in the set of request signals by prioritizing the set of request signals (step 110).

[0040] FIG. 2B shows a schematic of a DC-DC converter including a voltage divider and a comparator, consistent with one or more exemplary embodiments of the present disclosure. In an exemplary embodiment, DC-DC converter 200A may include a first implementation of DC-DC converter 200. In an exemplary embodiment, DC-DC converter 200A may include a comparator 210, a voltage divider 212, and a digital circuit 214. In an exemplary embodiment, output capacitor 204 may be selected responsive to an output voltage V.sub.out,n of output capacitor 204 being less than a reference voltage V.sub.ref,n in a set of reference voltages. In an exemplary embodiment, output voltage V.sub.out,n may be compared with reference voltage V.sub.ref,n utilizing comparator 210. In an exemplary embodiment, output voltage V.sub.out,n may not be in an input voltage range of comparator 210. Therefore, in an exemplary embodiment, reference voltage V.sub.ref,n may be compared with output voltage V.sub.out,n through voltage divider 212. As a result, reference voltage V.sub.ref,n may be compared with a voltage V.sub.div,n instead of output voltage V.sub.out,n. In an exemplary embodiment, voltage V.sub.div,n may be in the input voltage range of comparator 210.

[0041] Referring to FIGS. 1B and 2A, in an exemplary embodiment, step 108 may include generating a set of request signals. In an exemplary embodiment, generating a set of request signals 216 may include generating each request signal in set of request signals 216 responsive to a voltage level of a respective output capacitor in set of output capacitors 202 being less than a respective reference voltage in the set of reference voltages. In an exemplary embodiment, request signal Req.sub.n may be associated with output capacitor 204. Specifically, in an exemplary embodiment, request signal Req.sub.n may be generated from output voltage V.sub.out,n of output capacitor 204. In an exemplary embodiment, request signal Req.sub.n may be generated utilizing digital circuit 214. An exemplary output of comparator 210 may be fed to digital circuit 214. Therefore, in an exemplary embodiment, digital circuit 214 may generate request signal Req.sub.n responsive to voltage V.sub.div,n being less than reference voltage V.sub.ref,n.

[0042] FIG. 2C shows a schematic of a digital circuit, consistent with one or more exemplary embodiments of the present disclosure. In an exemplary embodiment, digital circuit 214 may include a NOT gate 218, an AND gate 220, a NAND gate 222, and a D flip-flop 224. Referring to FIGS. 2A and 2C, in an exemplary embodiment, DC-DC converter 200 may further include a zero-current detector 225. In an exemplary embodiment, zero-current detector 225 may detect a change in a level of an electric current I.sub.L passing through inductor L from positive to negative. In an exemplary embodiment, zero-current detector 225 may generate a signal ZCD responsive to electric current I.sub.L reaching zero. In an exemplary embodiment, when voltage V.sub.div,n is larger than reference voltage V.sub.ref,n, an output of comparator 210 may include a logical 1 value and signal ZCD may include a logical 1 value. As a result, a reset signal of D flip-flop 224 may include a logical 0 value and request signal Req.sub.n may include a logical 0 value. In contrast, an exemplary output of comparator 210 may include a logical 0 value when voltage V.sub.div,n is less than reference voltage V.sub.ref,n. Thus, in an exemplary embodiment, reset signal may include a logical 1 value and request signal Req.sub.n may still include a logical 0 value. Therefore, in an exemplary embodiment, a clock signal CLK of D flip-flop 224 may become a logical 1 value, changing a value of request signal Req.sub.n from a logical 0 value to a logical 1 value. In other words, in an exemplary embodiment, request signal Req.sub.n may be generated responsive to voltage V.sub.div,n being less than reference voltage V.sub.ref,n.

[0043] Referring to FIGS. 1B and 2A, in an exemplary embodiment, step 110, may include selecting request signal Req.sub.n. In an exemplary embodiment, request signal Req.sub.n may be selected by prioritizing set of request signals 216. Two or more exemplary output capacitors in set of output capacitors 202 may require to be charged simultaneously to maintain corresponding output voltages. However, only one exemplary output capacitor may be charged at any given instant. Therefore, exemplary request signals may be prioritized and an output capacitor with highest priority may be selected for charging. In an exemplary embodiment, output capacitor 204 may be of highest priority among output capacitors that require to be charged. An exemplary priority measure may include a priority in generation of request signals. In other words, an exemplary request signal that is generated prior to other request signals may be selected as a highest priority request signal. Besides, in an exemplary embodiment, arbitrary priority levels may be assigned to different request signals set of request signals 216.

[0044] In an exemplary embodiment, processor 208 may generate a set of enabling signals from set of request signals 216. Each exemplary enabling signal may be utilized for charging a respective output capacitor in set of output capacitors 202. In an exemplary embodiment, processor 208 may prioritize set of request signals 216 by activing only one enabling signal corresponding to output capacitor 204. Activating an exemplary enabling signal may be referred to as assigning a logical 1 value to an enabling signal. A logical 0 value may be assigned to all other exemplary enabling signals.

[0045] Referring to FIGS. 1A, 1B, and 2A, in an exemplary embodiment, selecting output capacitor 204 in step 102 may further include setting set of request signals 216 to an empty set (step 112). An exemplary voltage source may provide input voltage V.sub.in to DC-DC converter 200. In an exemplary embodiment, an average of electric current I.sub.L drawn from the voltage source may increase by increasing a consumed power of a set of loads 226 connected to DC-DC converter 200. An exemplary excessive current may be drawn from the voltage source when set of loads 226 consume excessive power, resulting in possible damage to the voltage source. In an exemplary embodiment, setting set of request signals 216 to the empty set may prevent set of loads 226 to draw an excessive current from the voltage source because no output capacitor may be charged when no request signal is generated.

[0046] In an exemplary embodiment, set of request signals 216 may be set to an empty set responsive to a consumed energy of a voltage source being higher than an input energy threshold. To detect an excessive current drawn from an exemplary voltage source, a consumed energy of the voltage source in a specified time interval may be calculated. In an exemplary embodiment, consumed energy of the voltage source is calculated by calculating a transferred energy from inductor L to each output capacitor in set of output capacitors 202 in the specified time interval. A transferred energy from an exemplary voltage source to set of output capacitors 202 may be calculated by a Coulomb counting method, as described below.

[0047] In an exemplary embodiment, transferred energy from inductor L to each output capacitor may depend on an operating mode of DC-DC converter 200, that is, a boost mode or a buck mode. In an exemplary embodiment, DC-DC converter 200 may operate in a boost mode when V.sub.out,n>V.sub.in. In an exemplary embodiment, DC-DC converter 200 may operate in a buck mode when V.sub.outn <V.sub.in. In an exemplary embodiment, when inductor L is charging, electric current I.sub.L may be equal to

[00001]$I_L=\frac{1}{L}{V}_{\mathrm{in}}.Math.t,$

where t(0, T.sub.Charge,n) and T.sub.charge,n is a duration of charging inductor L. In an exemplary embodiment, transferred energy from inductor L to output capacitor 204 in a buck mode may be calculated according to an operation defined by the following:

[00002]$\begin{array}{cc}{E}_{\mathrm{Buck},n}={}_0^{T_{\mathrm{Charge},n}}{V}_{in}.Math.I_{L}dt=\frac{V_{in}^2.Math.T_{\mathrm{Charge},n}^2}{2L},& \mathrm{Equation}\left(1\right)\end{array}$

In an exemplary embodiment, when DC-DC converter operates in the boost mode and inductor L is discharging into output capacitor 204, electric current I.sub.L may be calculated according to an operation defined by the following:

[00003]$\begin{array}{cc}{I}_L=-\frac{1}{L}\left(V_{\mathrm{out},i}-V_{in}\right).Math.\left(t-T_{\mathrm{Charge},n}\right)+\frac{1}{L}{V}_{in}.Math.T_{\mathrm{Charge},n},& \mathrm{Equation}\left(2\right)\end{array}$

where t(T.sub.Charge,n, T.sub.Charge,n+T.sub.Discharge,n) and T.sub.Discharge,n is a duration of discharging inductor L into output capacitor 204. In an exemplary embodiment, transferred energy from inductor L to output capacitor 204 in the boost mode may be calculated according to an operation defined by the following:

[00004]$\begin{array}{cc}{E}_{Bo\mathrm{ost},n}={}_0^{T_{\mathrm{Charge},n}}{V}_{in}.Math.I_{L}dt+{}_{T_{\mathrm{Charge},n}}^{T_{\mathrm{Charge},n}+T_{\mathrm{Discharge},n}}{V}_{in}.Math.I_L\mathrm{dt}=\frac{V_{in}^2.Math.T_{Cha\mathrm{rge},n}^2}{2L}+\frac{V_{in}^3.Math.T_{Cha\mathrm{rge},n}^2}{2L.Math.\left(V_{\mathrm{out},n}-V_{in}\right)}& \mathrm{Equation}\left(3\right)\end{array}$

[0048] To identify whether an excessive current is drawn from an exemplary voltage source, transferred energy in a specified time interval may be calculated. In an exemplary embodiment, a total transferred energy E.sub.total in a specified time interval may be equal to E.sub.total=.sub.m=1.sup.Mq.sub.mE.sub.Buck,m+(1q.sub.m), where q.sub.m=1 for the buck mode, q.sub.=0 in the boost mode, and M is a total number of output capacitors that are charged in a specified time interval. In an exemplary embodiment, total transferred energy E.sub.total may be compared with an input energy threshold E.sub.th,in. In an exemplary embodiment, input energy threshold E.sub.th,in may be obtained from a maximum current that a voltage source can provide to set of output capacitors 202. In an exemplary embodiment, when E.sub.total>E.sub.th,in, an excessive current may be drawn from the voltage source and set of request signals 216 may be set to an empty set to protect the voltage source from excessive current until a condition E.sub.total<E.sub.th,in is satisfied. An exemplary state of charge of the voltage source may be obtained from total transferred energy E.sub.total and by measuring voltage input V.sub.in in different time instances.

[0049] In an exemplary embodiment, selecting output capacitor 204 in step 102 may further include eliminating an overcurrent request signal from set of request signals 216 (step 114). An exemplary overcurrent request signal may be eliminated responsive to a transferred energy from the voltage source to an overcurrent output capacitor 228 in set of output capacitors 202 being higher than an output energy threshold. In an exemplary embodiment, a load 230 in set of loads 230 may be connected to overcurrent output capacitor 228. In an exemplary embodiment, load 230 may consume excessive energy that may pertain to a damage in load 230. In an exemplary embodiment, DC-DC converter 200 may protect load 230 from being overcurrent. An exemplary excessive current may be drawn from overcurrent output capacitor 228. In an exemplary embodiment, similar to transferred energy calculation in step 112, a transferred energy from the voltage source to overcurrent output capacitor 228 may be calculated. An exemplary voltage level of overcurrent output capacitor 228 may be smaller than a reference voltage when an overcurrent occurs in load 230. As a result, an exemplary overcurrent request signal in set of request signals 216 may be generated. In an exemplary embodiment, transferred energy from the voltage source to output capacitor 228 may be calculated according to one of Equation (1) or Equation (2). Therefore, an exemplary overcurrent request signal may be eliminated from set of request signals 216 when E.sub.Boost>E.sub.th,out or E.sub.Buck>E.sub.th,out, depending on a buck or a boost operating mode of DC-DC converter for output capacitor 228.

[0050] In an exemplary embodiment, when DC-DC converter 200 starts working, set of output voltages 206 may be zero. As a result, in an exemplary embodiment, set of output capacitors 202 may require to continuously be charged until each output voltage reaches a respective reference voltage, resulting in a steep increase in output voltages. In an exemplary embodiment, to avoid a steep increase in output voltages, a transferred energy from the voltage source to each output capacitor may be found by coulomb counting in step 114, and charging of overcurrent outputs may be prevented.

[0051] In an exemplary embodiment, step 104 may include charging inductor L by applying input voltage V.sub.in to inductor L. In further detail with respect to step 104, FIG. 1C shows a flowchart of a method for applying an input voltage to an inductor, consistent with one or more exemplary embodiments of the present disclosure. Referring to FIGS. 1C and 2A, in an exemplary embodiment, applying input voltage V.sub.in to inductor L may include applying input voltage V.sub.in to a first node 232 of inductor L (step 116) and coupling a second node 234 of inductor L to a ground node 236 (step 118).

[0052] For further detail regarding step 116, in an exemplary embodiment, input voltage V.sub.in may be applied to first node 232 through a first switch S1 of DC-DC converter 200. In an exemplary embodiment, processor 208 may generate a control signal Ctrl1 for charging inductor L. In an exemplary embodiment, control signal Ctrl1 may be applied to a gate of switch S1 through a driver circuit of DC-DC converter 200. As a result, in an exemplary embodiment, switch S1 may be turned on and input voltage V.sub.in may be applied to first node 232.

[0053] In further detail with regard to step 118, in an exemplary embodiment, second node 234 may be coupled to ground node 236 through a second switch S2 of DC-DC converter 200. In an exemplary embodiment, processor 208 may generate a control signal Ctrl2 for charging inductor L. In an exemplary embodiment, control signal Ctrl2 may be applied to a gate of switch S2 through a driver circuit of DC-DC converter 200. As a result, in an exemplary embodiment, switch S2 may be turned on and second node 234 may be coupled to ground node 236.

[0054] In an exemplary embodiment, a load connected to output capacitor 204 may be short-circuited. As a result, in an exemplary embodiment, output capacitor 204 may require to be charged continuously. In an exemplary embodiment, to avoid feeding excessive current to a short-circuited load, a duration of charging inductor L may be limited and may be equal to T.sub.charge,n. As a result, in an exemplary embodiment, stored energy in inductor L may be limited in each time of charging and an excessive current may not be drawn by a short-circuited load connected to output capacitor 204. Therefore, in an exemplary embodiment, DC-DC converter 200 may be protected from short-circuited loads.

[0055] Referring again to FIGS. 1A and 2A, in an exemplary embodiment, step 106 may include discharging electric current I.sub.L into output capacitor 204. For further detail regarding step 106, FIG. 1D shows a flowchart of a method for applying an input voltage to an inductor, consistent with one or more exemplary embodiments of the present disclosure. Referring to FIGS. 1D and 2A, in an exemplary embodiment, discharging electric current I.sub.L may include coupling first node 232 to ground node 236 (step 120), decoupling second node 234 from ground node 236 (step 122), and coupling second node 234 to output capacitor 204 (step 124). In an exemplary embodiment, DC-DC converter 200 may further include a set of output switches 238. Each exemplary output switch in set of output switches 238 may be connected between second node 234 and a respective output capacitor in set of output capacitors 202. Specifically, in an exemplary embodiment, an output switch 240 in set of output switches 238 may be connected between second node 234 and output capacitor 204. After charging inductor L, in an exemplary embodiment, processor 208 may activate an enabling signal for output capacitor 204. Then, in an exemplary embodiment, processor 208 may accordingly generate a set of control signals to generate a path between inductor L and output capacitor 204. Each exemplary control signal may be applied to a gate of a respective switch of DC-DC converter 200 to discharge electric current I.sub.L into output capacitor 204.

[0056] In further detail with respect to step 120, in an exemplary embodiment, first node 232 may be coupled to ground node 236 through a third switch S3 of DC-DC converter 200. In an exemplary embodiment, first node 232 may be coupled to ground node 236 responsive to DC-DC converter 200 operating in a buck mode. Meanwhile, in an exemplary embodiment, first node 232 may be decoupled from input voltage V.sub.in by turning off switch S1 responsive to DC-DC converter 200 operating in a buck mode. In an exemplary embodiment, processor 208 may generate a control signal Ctrl3 for discharging inductor L. In an exemplary embodiment, control signal Ctrl3 may be applied to a gate of switch S3 through a driver circuit of DC-DC converter 200. As a result, in an exemplary embodiment, switch S3 may be turned on and first node 232 may be coupled to ground node 236. In contrast, in an exemplary embodiment, switch S1 may be remained turned on and switch S3 may be remained turned off responsive to DC-DC converter 200 operating in a boost mode.

[0057] For further detail regarding step 122, in an exemplary embodiment, second node 234 may be decoupled from ground node 236 by turning off switch S2. In an exemplary embodiment, processor 208 may turn off switch S2 by deactivating control signal Ctrl2.

[0058] In further detail with regard to step 124, in an exemplary embodiment, second node 234 may be coupled to output capacitor 204 through output switch 240. In an exemplary embodiment, processor 208 may generate a control signal Ctrl.sub.out,n to couple second node 234 to output capacitor 204. In an exemplary embodiment, control signal Ctrl.sub.out,n may be applied to a gate of output switch 240 through a driver circuit of DC-DC converter 200. As a result, in an exemplary embodiment, output switch 240 may be turned on and second node 234 may be coupled to output capacitor 204.

[0059] Referring to FIGS. 1A, 1D, and 2A, in an exemplary embodiment, discharging electric current I.sub.L in step 106 may further include decoupling second node 234 from output capacitor 204 (step 126A). In an exemplary embodiment, step 126A may include a first implementation of decoupling second node 234 from output capacitor 204. In an exemplary embodiment, second node 234 may be decoupled from output capacitor 204 by turning off output switch 240. In an exemplary embodiment, output switch 240 may be turned off responsive to a value of electric current I.sub.L being in a neighborhood of zero. In an exemplary embodiment, the neighborhood of zero may be calculated according to an operation defined by the following:

[00005]$\begin{array}{cc}.Math.I_L.Math.<\frac{V_{in}{T}_{\mathrm{charge},n}}{L}\sqrt{}& \mathrm{Inequality}\left(1\right)\end{array}$

where is a reduction in an efficiency of DC-DC converter 200 due to an imprecise current detection of zero-current detector 225. In an exemplary embodiment, for one percent reduction in an efficiency of DC-DC converter 200, may be equal to 0.01.

[0060] In an exemplary embodiment, electric current I.sub.L may flow from the voltage source to output capacitor 204 when electric current I.sub.L is positive. Therefore, in an exemplary embodiment, output capacitor 204 may be charged to output voltage V.sub.out,n. In contrast, in an exemplary embodiment, electric current I.sub.L may flow from output capacitor 204 to the voltage source when electric current I.sub.L is negative. Therefore, in an exemplary embodiment, output capacitor 204 may be discharged. To avoid discharging output capacitor 204, in an exemplary embodiment, output switch 240 may be turned off when electric current I.sub.L crosses zero. In an exemplary embodiment, zero-current detector 225 may generate a signal ZCD and responsive to electric current I.sub.L crossing zero. Then in an exemplary embodiment, zero-current detector 225 may send signal ZCD to processor 208. In an exemplary embodiment, processor 208 may then deactivate control signal Ctrl.sub.out,n. As a result, in an exemplary embodiment, output switch 240 may be turned off.

[0061] FIG. 1E shows a flowchart of a method for discharging an electric current into an output capacitor, consistent with one or more exemplary embodiments of the present disclosure. Referring to FIGS. 1A, 1E, and 2A, in an exemplary embodiment, discharging electric current I.sub.L in step 106 may further include decoupling second node 234 from output capacitor 204 (method 126B). In an exemplary embodiment, method 126B may include a second implementation of decoupling second node 234 from output capacitor 204. In an exemplary embodiment, discharging electric current I.sub.L may further include decoupling second node 234 from output capacitor 204 (step 128) and coupling first node 232 to second node 234 (step 130).

[0062] For further detail with respect to step 128, in an exemplary embodiment, second node 234 may be decoupled from output capacitor 204 by turning off output switch 240. In an exemplary embodiment, output switch 240 may be turned off responsive to a value of electric current I.sub.L being in a neighborhood of a positive threshold I.sub.th. As a result, in an exemplary embodiment, charging output capacitor 204 may be stopped before fully discharging electric current I.sub.L. In an exemplary embodiment, the neighborhood of positive threshold I.sub.th may be calculated according to an operation defined by the following:

[00006]$\begin{array}{cc}.Math.I_L.Math.<.Math.I_{th}-\frac{1}{L}\sqrt{.Math.I_{th}^2{L}^2-L\left(2I_{th}+\frac{V_{in}{T}_{\mathrm{charge},n}}{L}\right)V_{in}{T}_{\mathrm{Charge},n}.Math.}.Math.& \mathrm{Inequality}\left(2\right)\end{array}$

where is a reduction in an efficiency of DC-DC converter 200 due to an imprecise current detection of a current-detection circuit.

[0063] In further detail regarding step 130, in an exemplary embodiment, coupling first node 232 to second node 234 may include turning on fourth switch S4 of DC-DC converter 200. In an exemplary embodiment, fourth switch S4 may be connected in parallel with inductor L. In an exemplary embodiment, coupling first node 232 to second node 234 before fully discharging inductor L may preserve electric current I.sub.L flowing in a loop between first node 232 and second node 234.

[0064] FIG. 3A shows control signals, an electric current, and output voltages for non-overlapped request signals, consistent with one or more exemplary embodiments of the present disclosure. Referring to FIGS. 2A, 2B, and 3A, in an exemplary embodiment, an output voltage V.sub.out,1 may become smaller than a reference voltage V.sub.ref,1 due to a power consumption of a load connected to an output capacitor of DC-DC converter 200. Thus, in an exemplary embodiment, digital circuit 214 may generate a request signal Req.sub.1 and may preserve a value of request signal Req.sub.1 during a time interval 1. In an exemplary embodiment, since only request signal Req.sub.1 is generated in time interval 1, set of request signals 216 may include only request signal Req.sub.1. Therefore, in an exemplary embodiment, processor 208 may select request signal Req.sub.1 as a highest priority request signal. In an exemplary embodiment, processor 208 may activate control signal Ctrl1 and control signal Ctrl3 to charge inductor L. In an exemplary embodiment, electric current I.sub.L may increase to a peak value in time interval 1. Then, in an exemplary embodiment, processor 208 may deactivate control signal Ctrl3 to decouple second node 234 from ground node 236. In an exemplary embodiment, DC-DC converter 200 may operate in a boost mode for output voltage V.sub.out,1, that is, V.sub.out,1>V.sub.in. As a result, in an exemplary embodiment, control signal Ctrl1 may remain activated when inductor L is discharging. Meanwhile, in an exemplary embodiment, processor 208 may activate a control signal Ctrl.sub.out,1 to turn on a first output switch in set of output switches 238, making a path for discharging inductor L. By discharging inductor L, in an exemplary embodiment, output voltage V.sub.out,1 become larger than reference voltage V.sub.ref,1. In an exemplary embodiment, electric current I.sub.L may be decreasing when control signal Ctrl.sub.out,1 is activated. In an exemplary embodiment, when electric current I.sub.L reaches zero, zero-current detector 225 may generate signal ZCD. As a result, in an exemplary embodiment, digital circuit 214 may deactivate control signal Req.sub.1 and processor 208 may deactivate control signal Ctrl1.

[0065] In an exemplary embodiment, a similar procedure may be performed in a time interval 2 to charge an output capacitor of a second output of DC-DC converter 200. In an exemplary embodiment, DC-DC converter 200 may operate in a buck mode for an output voltage V.sub.out,2. Therefore, in an exemplary embodiment, processor 208 may deactivate control signal Ctrl1 and activate a control signal Ctrl2 for discharging inductor L.

[0066] FIG. 3B shows control signals, an electric current, and output voltages for overlapped request signals, consistent with one or more exemplary embodiments of the present disclosure. Referring to FIGS. 2A and 3B, in an exemplary embodiment, a request signal Req.sub.1 may be generated in a time interval 3 and inductor L may be charged accordingly. Meanwhile, in an exemplary embodiment, a request signal Req2 may be generated in a time interval 4 that overlaps with time interval 3. As a result, in an exemplary embodiment, set of request signals 216 may include request signal Req.sub.1 and request signal Req2. In an exemplary embodiment, request signal Req.sub.1 may be selected because request signal Req.sub.1 is requested prior to request signal Req2. In an exemplary embodiment, after charging an output capacitor of request signal Req.sub.1, inductor L may be charged and discharged to charge an output capacitor of request signal Req2.

[0067] FIG. 3C shows an output voltage provided to a constant load, consistent with one or more exemplary embodiments of the present disclosure. Referring to FIGS. 2A and 3C, in an exemplary embodiment, a voltage 302 of output voltage V.sub.outn may be provided to a constant load, that is, a load that draws a constant current in time. In an exemplary embodiment, since output capacitor 204 may not be periodically charged, an overall charging and discharging time of output capacitor 204 may include a jitter in different charging and discharging turns. Specifically, in an exemplary embodiment, charging and discharging of output capacitor 204 may take T, T+j.sub.1, T+j.sub.2, and T+j.sub.3 seconds in four consecutive charging turns, where T is a period of charging set of output capacitors 202 and j.sub.1, j.sub.2, and j.sub.3 are jitters of charging and discharging output capacitor 204.

[0068] FIG. 3D shows a spectrum of an output voltage, consistent with one or more exemplary embodiments of the present disclosure. Referring to FIGS. 1A, 3C, and 3D, in an exemplary embodiment, a spectrum of voltage 302 may include a spectrum 304. In an exemplary embodiment, a spectrum 306 may include a spectrum of an output voltage that charges with fixed frequency. As a result, in an exemplary embodiment, spectrum 306 may include a number of harmonics at r/T Hz, where r>1 is a number of harmonics. In contrast to spectrum 306, in an exemplary embodiment, spectrum 304 may be flattened around each harmonic. Therefore, in an exemplary embodiment, method 100 may be more robust to noise than fixed-frequency voltage conversion methods such as pulse width modulation methods.

[0069] FIG. 3E shows an output voltage provided to a variant load, consistent with one or more exemplary embodiments of the present disclosure. Referring to FIGS. 1A, 3D, and 3E, in an exemplary embodiment, a spectrum 308 may include a spectrum of an output voltage 310 provided to a variant load. In an exemplary embodiment, a charging and discharging times of an output voltage 310 may be independent in different turns for a variant load, that is, a load that draws a variant current from an output capacitor in time. As a result, in an exemplary embodiment, spectrum 308 may be spread in different frequencies rather than being concentrated around different harmonics. As a result, in an exemplary embodiment, a noise immunity of method 100 may enhance for variant loads.

[0070] FIG. 4 shows an example computer system 400 in which an embodiment of the present invention, or portions thereof, may be implemented as computer-readable code, consistent with exemplary embodiments of the present disclosure. For example, different steps of method 100 may be implemented in computer system 400 using hardware, software, firmware, tangible computer readable media having instructions stored thereon, or a combination thereof and may be implemented in one or more computer systems or other processing systems. Hardware, software, or any combination of such may embody any of the modules and components in FIGS. 1A-2C.

[0071] If programmable logic is used, such logic may execute on a commercially available processing platform or a special purpose device. One ordinary skill in the art may appreciate that an embodiment of the disclosed subject matter can be practiced with various computer system configurations, including multi-core multiprocessor systems, minicomputers, mainframe computers, computers linked or clustered with distributed functions, as well as pervasive or miniature computers that may be embedded into virtually any device.

[0072] For instance, a computing device having at least one processor device and a memory may be used to implement the above-described embodiments. A processor device may be a single processor, a plurality of processors, or combinations thereof. Processor devices may have one or more processor cores.

[0073] An embodiment of the invention is described in terms of this example computer system 400. After reading this description, it will become apparent to a person skilled in the relevant art how to implement the invention using other computer systems and/or computer architectures. Although operations may be described as a sequential process, some of the operations may in fact be performed in parallel, concurrently, and/or in a distributed environment, and with program code stored locally or remotely for access by single or multi-processor machines. In addition, in some embodiments the order of operations may be rearranged without departing from the spirit of the disclosed subject matter.

[0074] Processor device 404 may be a special purpose (e.g., a graphical processing unit) or a general-purpose processor device. As will be appreciated by persons skilled in the relevant art, processor device 404 may also be a single processor in a multi-core/multiprocessor system, such system operating alone, or in a cluster of computing devices operating in a cluster or server farm. Processor device 404 may be connected to a communication infrastructure 406, for example, a bus, message queue, network, or multi-core message-passing scheme.

[0075] In an exemplary embodiment, computer system 400 may include a display interface 402, for example a video connector, to transfer data to a display unit 430, for example, a monitor. Computer system 400 may also include a main memory 408, for example, random access memory (RAM), and may also include a secondary memory 410. Secondary memory 410 may include, for example, a hard disk drive 412, and a removable storage drive 414. Removable storage drive 414 may include a floppy disk drive, a magnetic tape drive, an optical disk drive, a flash memory, or the like. Removable storage drive 414 may read from and/or write to a removable storage unit 418 in a well-known manner. Removable storage unit 418 may include a floppy disk, a magnetic tape, an optical disk, etc., which may be read by and written to by removable storage drive 414. As will be appreciated by persons skilled in the relevant art, removable storage unit 418 may include a computer usable storage medium having stored therein computer software and/or data.

[0076] In alternative implementations, secondary memory 410 may include other similar means for allowing computer programs or other instructions to be loaded into computer system 400. Such means may include, for example, a removable storage unit 422 and an interface 420. Examples of such means may include a program cartridge and cartridge interface (such as that found in video game devices), a removable memory chip (such as an EPROM, or PROM) and associated socket, and other removable storage units 422 and interfaces 420 which allow software and data to be transferred from removable storage unit 422 to computer system 400.

[0077] Computer system 400 may also include a communications interface 424. Communications interface 424 allows software and data to be transferred between computer system 400 and external devices. Communications interface 424 may include a modem, a network interface (such as an Ethernet card), a communications port, a PCMCIA slot and card, or the like. Software and data transferred via communications interface 424 may be in the form of signals, which may be electronic, electromagnetic, optical, or other signals capable of being received by communications interface 424. These signals may be provided to communications interface 424 via a communications path 426. Communications path 426 carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, an RF link or other communications channels.

[0078] In this document, the terms computer program medium and computer usable medium are used to generally refer to media such as removable storage unit 418, removable storage unit 422, and a hard disk installed in hard disk drive 412. Computer program medium and computer usable medium may also refer to memories, such as main memory 408 and secondary memory 410, which may be memory semiconductors (e.g. DRAMs, etc.).

[0079] Computer programs (also called computer control logic) are stored in main memory 408 and/or secondary memory 410. Computer programs may also be received via communications interface 424. Such computer programs, when executed, enable computer system 400 to implement different embodiments of the present disclosure as discussed herein. In particular, the computer programs, when executed, enable processor device 404 to implement the processes of the present disclosure, such as the operations in method 100 illustrated by flowcharts of FIGS. 1A-1E discussed above. Accordingly, such computer programs represent controllers of computer system 400. Where an exemplary embodiment of method 100 is implemented using software, the software may be stored in a computer program product and loaded into computer system 400 using removable storage drive 414, interface 420, and hard disk drive 412, or communications interface 424.

[0080] Embodiments of the present disclosure also may be directed to computer program products including software stored on any computer useable medium. Such software, when executed in one or more data processing device, causes a data processing device to operate as described herein. An embodiment of the present disclosure may employ any computer useable or readable medium. Examples of computer useable mediums include, but are not limited to, primary storage devices (e.g., any type of random access memory), secondary storage devices (e.g., hard drives, floppy disks, CD ROMS, ZIP disks, tapes, magnetic storage devices, and optical storage devices, MEMS, nanotechnological storage device, etc.).

[0081] The embodiments have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0082] While the foregoing has described what may be considered to be the best mode and/or other examples, it is understood that various modifications may be made therein and that the subject matter disclosed herein may be implemented in various forms and examples, and that the teachings may be applied in numerous applications, only some of which have been described herein. It is intended by the following claims to claim any and all applications, modifications and variations that fall within the true scope of the present teachings.

[0083] Unless otherwise stated, all measurements, values, ratings, positions, magnitudes, sizes, and other specifications that are set forth in this specification, including in the claims that follow, are approximate, not exact. They are intended to have a reasonable range that is consistent with the functions to which they relate and with what is customary in the art to which they pertain.

[0084] The scope of protection is limited solely by the claims that now follow. That scope is intended and should be interpreted to be as broad as is consistent with the ordinary meaning of the language that is used in the claims when interpreted in light of this specification and the prosecution history that follows and to encompass all structural and functional equivalents. Notwithstanding, none of the claims are intended to embrace subject matter that fails to satisfy the requirement of Sections 101, 102, or 103 of the Patent Act, nor should they be interpreted in such a way. Any unintended embracement of such subject matter is hereby disclaimed.

[0085] Except as stated immediately above, nothing that has been stated or illustrated is intended or should be interpreted to cause a dedication of any component, step, feature, object, benefit, advantage, or equivalent to the public, regardless of whether it is or is not recited in the claims.

[0086] It will be understood that the terms and expressions used herein have the ordinary meaning as is accorded to such terms and expressions with respect to their corresponding respective areas of inquiry and study except where specific meanings have otherwise been set forth herein. Relational terms such as first and second and the like may be used solely to distinguish one entity or action from another without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms comprises, comprising, or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by a or an does not, without further constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0087] The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various implementations. This is for purposes of streamlining the disclosure, and is not to be interpreted as reflecting an intention that the claimed implementations require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed implementation. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.

[0088] While various implementations have been described, the description is intended to be exemplary, rather than limiting and it will be apparent to those of ordinary skill in the art that many more implementations and implementations are possible that are within the scope of the implementations. Although many possible combinations of features are shown in the accompanying figures and discussed in this detailed description, many other combinations of the disclosed features are possible. Any feature of any implementation may be used in combination with or substituted for any other feature or element in any other implementation unless specifically restricted. Therefore, it will be understood that any of the features shown and/or discussed in the present disclosure may be implemented together in any suitable combination. Accordingly, the implementations are not to be restricted except in light of the attached claims and their equivalents. Also, various modifications and changes may be made within the scope of the attached claims.