SEMICONDUCTOR DEVICE INCLUDING TWO-DIMENSIONAL MATERIAL AND METHOD OF MANUFACTURING THE SAME

Abstract

A semiconductor device may include a channel layer including a two-dimensional material layer and a molecular crystal layer on the two-dimensional material layer, the two-dimensional material layer including a two-dimensional semiconductor material; a source electrode and a drain electrode, which respectively may be on both sides of the channel layer; and a gate insulating layer and a gate electrode, which respectively may be on the channel layer between the source electrode and the drain electrode. The molecular crystal layer may include a plate-shaped aromatic compound of C.sub.20-C.sub.40, and may have a thickness of 1 molecular layer to 5 molecular layers.

Claims

1. A semiconductor device comprising: a channel layer including a two-dimensional material layer and a molecular crystal layer on the two-dimensional material layer, the two-dimensional material layer including a two-dimensional semiconductor material; a source electrode and a drain electrode, which respectively are on both sides of the channel layer; and a gate insulating layer and a gate electrode on the channel layer between the source electrode and the drain electrode, wherein the molecular crystal layer includes a plate-shaped aromatic compound of C.sub.20-C.sub.40, and a thickness of the molecular crystal layer is 1 molecular layer to 5 molecular layers.

2. The semiconductor device of claim 1, wherein the plate-shaped aromatic compound has semiconductor characteristics.

3. The semiconductor device of claim 1, wherein the plate-shaped aromatic compound includes a tetracene-based compound, a chrysene-based compound, a triphenylene-based compound, a pyrene-based compound, a perylene-based compound, a pentacene-based compound, a benzopyrene-based compound, a benzoperylene-based compound, or a coronene-based compound.

4. The semiconductor device of claim 2, wherein the plate-shaped aromatic compound includes at least one of a hydroxyl group, a carboxyl group, a metal carboxylate group, an imide group, an amide group, and a carboxylic anhydride group.

5. The semiconductor device of claim 1, wherein the thickness of the molecular crystal layer is 1 molecular layer to 3 molecular layers.

6. The semiconductor device of claim 1, wherein the two-dimensional semiconductor material includes a transition metal dichalcogenide (TMD) or black phosphorus.

7. The semiconductor device of claim 6, wherein the transition metal dichalcogenide (TMD) includes a metal element and a chalcogen element, the metal element includes at least one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, and Re, and the chalcogen element includes at least one of S, Se, and Te.

8. The semiconductor device of claim 6, wherein the transition metal dichalcogenide (TMD) includes MoS.sub.2, MoSe.sub.2, MoTe.sub.2, WS.sub.2, WSe.sub.2, WTe.sub.2, ZrS.sub.2, ZrSe.sub.2, HfS.sub.2, HfSe.sub.2, NbSe.sub.2, ReSe.sub.2, or any combination thereof.

9. The semiconductor device of claim 1, wherein the molecular crystal layer has crystallinity due to a crystal structure of the two-dimensional material layer.

10. The semiconductor device of claim 1, wherein the two-dimensional material layer has a polycrystalline structure.

11. The semiconductor device of claim 1, wherein the channel layer includes a first region and second regions, the first region of the channel layer overlaps the gate electrode, and the second regions of the channel layer overlap the source electrode and the drain electrode, respectively.

12. The semiconductor device of claim 11, wherein a material of the two-dimensional material layer of the first region of the channel layer is different from a material of the two-dimensional material layer of the second regions of the channel layer.

13. The semiconductor device of claim 11, wherein the two-dimensional material layer of the second regions of the channel layer further includes a p-type dopant or an n-type dopant.

14. The semiconductor device of claim 11, wherein the molecular crystal layer of the second regions of the channel layer includes a material configured to provide a p-type dopant or an n-type dopant to the two-dimensional material layer of the second regions of the channel layer.

15. The semiconductor device of claim 14, wherein the material configured to provide the p-type dopant or the n-type dopant includes a plate-shaped aromatic compound including metal ions.

16. The semiconductor device of claim 11, wherein a material of the molecular crystal layer of the first region of the channel layer is different from a material of the molecular crystal layer of the second regions of the channel layer.

17. The semiconductor device of claim 1, wherein the semiconductor device has a planar FET structure, a fin FET (FinFET) structure, a gate all around FET (GAA FET) structure, or a complementary FET (CFET) structure.

18. An electronic apparatus comprising: the semiconductor device of claim 1.

19. A method of manufacturing a semiconductor device, the method comprising: forming a channel layer on a substrate, the forming the channel layer including forming a two-dimensional material layer including a two-dimensional semiconductor material on the substrate and forming a molecular crystal layer including a plate-shaped aromatic compound of C.sub.20-C.sub.40 on the two-dimensional material layer; forming a gate insulating layer and a gate electrode on the channel layer; and forming a source electrode and a drain electrode respectively on both sides of the channel layer.

20. The method of claim 19, wherein the molecular crystal layer is deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), or evaporation.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above and other aspects, features, and advantages of example embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0040] FIG. 1 is a cross-sectional view of a semiconductor device 100 according to an embodiment.

[0041] FIG. 2 is a conceptual diagram of a channel layer 130 according to an embodiment.

[0042] FIG. 3 illustrates molecular model diagrams of PDI, Me-PDI, and PTCDA, which are examples of compounds having a phenylene body among plate-shaped aromatic compounds capable of forming a molecular crystal layer 120.

[0043] FIGS. 4A to 4C are Scanning Tunneling Microscope (STM) images (left) of PDI, Me-PDI, and PTCDA layers deposited on MoS.sub.2 layers on Si/SiO.sub.2 substrates and molecular arrangement diagrams (right) inferred from the STM images, respectively.

[0044] FIG. 5A illustrates scanning electron microscope (SEM) images of the upper surface of a MoS.sub.2/HfO.sub.2 stacked structure on a Si/SiO.sub.2 substrate, and FIG. 5B illustrates SEM images of the upper surface of a MoS.sub.2/PDI/HfO.sub.2 stacked structure on a Si/SiO.sub.2 substrate.

[0045] FIGS. 6A to 6D illustrate atomic force microscope (AFM) images of a MoS.sub.2 layer structure, a MoS.sub.2/HfO.sub.2 layer structure, a MoS.sub.2/PTCDA layer structure and a MoS.sub.2/PTCDA/HfO.sub.2 layer structure, on a Si/SiO.sub.2 substrate, respectively.

[0046] FIGS. 7A to 7E are cross-sectional views for explaining a method for manufacturing a semiconductor device, according to an embodiment.

[0047] FIG. 8 is a schematic cross-sectional view of a semiconductor device 200 according to another embodiment.

[0048] FIG. 9 is a schematic cross-sectional view of a semiconductor device 300 according to another embodiment.

[0049] FIG. 10A is a perspective view schematically illustrating a semiconductor device (FinFET, 500) according to another embodiment, and FIG. 10B is a cross-sectional view taken along the line A-A of FIG. 10A.

[0050] FIG. 11A is a perspective view schematically illustrating a semiconductor device (MBCFET, 600) according to another embodiment, and FIG. 11B is a cross-sectional view taken along the line B-B of FIG. 11A.

[0051] FIG. 12 is a conceptual diagram of a channel layer 630 according to another embodiment.

[0052] FIGS. 13 and 14 are conceptual diagrams schematically illustrating an electronic device architecture capable of being applied to electronic apparatuses, according to an embodiment.

DETAILED DESCRIPTION

[0053] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items. Expressions such as at least one of, when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, at least one of A, B, and C, and similar language (e.g., at least one selected from the group consisting of A, B, and C and at least one of A, B, or C) may be construed as A only, B only, C only, or any combination of two or more of A, B, and C, such as, for instance, ABC, AB, BC, and AC.

[0054] When the terms about or substantially are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., 10%) around the stated numerical value. Moreover, when the words generally and substantially are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified with about or substantially, it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., 10%) around the stated numerical values or shapes. When ranges are specified, the range includes all values therebetween such as at increments of 0.1%.

[0055] Hereinafter, embodiments will be described in detail with reference to the attached drawings. In the drawings below, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience of explanation. The presented embodiments described below are merely non-limiting example, and various modifications are possible from these embodiments.

[0056] Hereinafter, the terms over or on may include not only things that are directly above, below, left, or right in contact, but also things that are indirectly above, below, left, or right in non-contact. Singular expressions include plural expressions unless context clearly dictates otherwise. Additionally, when a part is said to include a component, this does not mean that it excludes other components, but rather that it may include other components, unless otherwise specifically stated.

[0057] The use of the described term above and similar referential terms thereto may refer to both the singular and the plural. Unless steps constituting a method are explicitly described in order or are described to the contrary, these steps may be performed in any suitable order and are not necessarily limited to the order described.

[0058] Additionally, terms such as section, module, etc. described in the specification mean a unit that performs at least one function or operation, which may be implemented by hardware or software or may be implemented by a combination of hardware and software.

[0059] The connections or connection members of lines between components shown in the drawings illustratively represent functional connections and/or physical or circuit connections, and may be represented in an actual device as alternative or additional various functional connections, physical connections, or circuit connections.

[0060] Herein, when a term single layer is used to describe the molecular crystal layer, it means single molecular layer.

[0061] Any use of examples is intended merely to describe technical ideas in detail and is not intended to limit the scope of the disclosure unless otherwise defined by the claims.

[0062] FIG. 1 is a cross-sectional view of a semiconductor device 100 according to an embodiment. The semiconductor device 100 shown in FIG. 1 may be, for example, a field effect transistor (FET).

[0063] Referring to FIG. 1, a channel layer 130 is provided on a substrate 101. The substrate 101 may include various materials such as a semiconductor material, an insulating material, and a metal material. The substrate 101 may also be a substrate for growth of a two-dimensional semiconductor material of the channel layer 130 to be described later.

[0064] The channel layer 130 may include a two-dimensional material layer 110 and a molecular crystal layer 120. The two-dimensional material layer 110 may include a two-dimensional semiconductor material. The two-dimensional semiconductor material refers to a semiconductor material having a two-dimensional crystal structure, and may have a layered structure. Each of the layers constituting this two-dimensional semiconductor material may have a thickness at an atomic level. For example, the two-dimensional semiconductor material may include 1 atomic layer to 3 atomic layers. The two-dimensional semiconductor material may have excellent electrical properties in a horizontal direction and can maintain high mobility without significant changes in their properties even when its thickness is reduced to a nanoscale.

[0065] The two-dimensional semiconductor material may include a material having a band gap of approximately 0.1 eV or more and 3.0 eV or less. For example, the two-dimensional semiconductor material may include, but is not limited to, a transition metal dichalcogenide (TMD).

[0066] TMD is a two-dimensional material having semiconductor properties and is a compound of a transition metal and a chalcogen element. Here, the transition metal may include, for example, at least one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Co, To and Re, and the chalcogen element may include, for example, at least one of S, Se and Te. As specific examples, TMDs may include, but are not limited to, MoS.sub.2, MoSe.sub.2, MoTe.sub.2, WS.sub.2, WSe.sub.2, WTe.sub.2, ZrS.sub.2, ZrSe.sub.2, HfS.sub.2, HfSe.sub.2, NbSe.sub.2, ReSe.sub.2, etc.

[0067] The two-dimensional material layer 110 may include (or be composed of), for example, 1 layer to 10 layers or 1 layer to 5 layers of the two-dimensional semiconductor material, but the disclosure is not limited thereto. The two-dimensional material layer 110 may have a thickness of, for example, about 0.1 nm to about 1 nm.

[0068] The molecular crystal layer 120 is a layer including molecular crystals, and is disposed on the two-dimensional material layer 110. The molecular crystals may be made of a plate-shaped aromatic compound. The plate-shaped aromatic compound refers to an aromatic compound having a two-dimensional structure. The plate-shaped aromatic compound of the present embodiment may be, for example, a plate-shaped aromatic compound of C.sub.20-C.sub.40. The plate-shaped aromatic compound may include, for example, a tetracene-based compound, a chrysene-based compound, a triphenylene-based compound, a pyrene-based compound, a perylene-based compound, a pentacene-based compound, a benzopyrene-based compound, a benzoperylene-based compound, or a coronene-based compound. The plate-shaped aromatic compound may contain, for example, a hydroxyl group, a carboxyl group, a metal carboxylate group, an imide group, an amide group, or a carboxylic anhydride group.

[0069] Examples of the plate-shaped aromatic compound may include, but are not limited to, PDI (perylene diimide), Me-PDI (N,N-dimethyl-3,4,9,10-perylenetetracarboxylic diimide), or PTCDA (perylenetetracarboxylic dianhydride).

[0070] The molecular crystal layer 120 may have a thickness of, for example, 1 molecular layer to 5 molecular layers or 1 molecular layer to 3 molecular layers. The molecular crystal layer 120 may have a thickness of, for example, about 0.1 nm to about 0.5 nm.

[0071] FIG. 2 is a conceptual diagram of a channel layer 130 according to an embodiment. Referring to FIG. 2, the molecular crystal layer 120 is formed on the two-dimensional material layer 110, and both the two-dimensional material layer 110 and the molecular crystal layer 120 are formed as a single layer. In FIG. 2, each spherical shape represents an element constituting a two-dimensional semiconductor material and a plate-shaped aromatic compound. Since the molecular crystal layer 120 is made of the plate-shaped aromatic compound according to the embodiment, it may have crystallinity due to the crystal structure of the two-dimensional material layer 110 on the two-dimensional material layer 110. The molecular crystal layer 120 has a crystal structure in which plate-shaped aromatic compounds are arranged regularly (e.g., in a specific pattern), and its crystal size may be smaller than or equal to the crystal size of the two-dimensional material layer 110.

[0072] FIG. 3 illustrates molecular model diagrams of PDI, Me-PDI, and PTCDA, which are examples of compounds having a phenylene body among plate-shaped aromatic compounds capable of forming a molecular crystal layer 120. Referring to the molecular model diagrams of FIG. 3, it may be expected that each of the PDI, Me-PDI, and PTCDA molecules has an overall plate-like and rod-like shape and are stacked in layers. PDI, Me-PDI, and PTCDA differ in that the ends (circled) of the molecules have a diimide group, a methyldiimide group, and a carboxylic anhydride group, respectively.

[0073] FIGS. 4A to 4C are STM images (left) of PDI, Me-PDI, and PTCDA layers deposited on MoS.sub.2 layers on Si/SiO.sub.2 substrates and molecular arrangement diagrams (right) inferred from the STM images, respectively. A MoS.sub.2 layer was deposited as a single layer by MOCVD on a 2-inch silicon (Si) wafer substrate on which a silicon insulating layer (SiO.sub.2) was formed, and PDI, Me-PDI, and PTCDA layers were deposited as single layers by evaporation on the MoS.sub.2 layer, respectively.

[0074] Referring to FIGS. 4A to 4C, it appears that the molecules of the PDI, Me-PDI, and PTCDA layers are regularly arranged on the MoS.sub.2 layer. It may be confirmed from this that the PDI, Me-PDI, and PTCDA layers have crystallinity. It is shown in FIGS. 4A to 4C that the PDI layer has a brick wall arrangement, the Me-PDI has a canted arrangement, and the PTCDA layer has a herringbone arrangement. The differences in molecular arrangements of PDI, Me-PDI, and PTCDA layers are presumed to be due to the difference in shapes of terminals of these molecules.

[0075] Channels made of a two-dimensional semiconductor material may have better scaling compared to silicon channels, but they may be damaged during a device manufacturing process due to their atomic-level thickness (e.g., three-atom-thick layers in the case of transition metal dichalcogenides). In addition, since there may be no dangling bonds on the surface of the two-dimensional semiconductor material, it may be difficult to deposit another material as a thin and uniform layer on the channels made of the two-dimensional semiconductor material via routes of dangling bonds. When depositing metal for source/drain contacts on two-dimensional semiconductor material channels, damages to the channels may increase contact resistance. In addition, it may be required to deposit a high-dielectric gate insulating layer more thinly and more uniformly between a channel and a gate electrode, but there may be a limit to the scaling of equivalent oxide thickness (EOT) due to the non-uniform deposition of the gate insulating layer. Additionally, interfacial trap density may increase due to damage that may occur in the channel during the formation of the gate insulating layer.

[0076] The molecular crystal layer of the present embodiment can be deposited thinner and more uniformly as a layer (e.g., a single layer) with crystallinity on a two-dimensional semiconductor material layer due to its structural characteristics having molecular crystals. Therefore, in a transistor manufacturing process, the presence of the molecular crystal layer on the two-dimensional semiconductor material layer enables a source/drain metal structure or a gate stacked structure to be formed more thinly and more uniformly. In addition, the molecular crystal layer may have improved chemical and thermal stability, so that a two-dimensional semiconductor material layer can be protected well when forming a structure on the two-dimensional semiconductor material layer. Due to the small thickness of the molecular crystal layer, there may be no deterioration in device characteristics even when it is used as an insertion layer on the two-dimensional semiconductor material layer.

[0077] Referring again to FIG. 1, a source electrode 151 and a drain electrode 152 may be provided on both sides of the channel layer 130. A gate insulating layer 140 may be provided on the channel layer 130 between the source electrode 151 and the drain electrode 152. A gate electrode 160 may be provided on the gate insulating layer 140.

[0078] The gate insulating layer 140 may include silicon oxide (SiO.sub.2), silicon nitride (SiN), hafnium oxide (HfO.sub.2), zirconium oxide (ZrO.sub.2), aluminum oxide (Al.sub.2O.sub.3), yttrium oxide (Y.sub.2O.sub.3), and/or lanthanum oxide (La.sub.2O.sub.3), but the disclosure is not limited thereto. The gate insulating layer 140 may have a thickness of, for example, about 2 nm to about 20 nm or, for example, about 2 nm to about 10 nm.

[0079] The gate electrode 160 may include a metal material or a conductive oxide. Here, the metal material may include at least one selected from the group consisting of Au, Ti, TiN, TaN, W, Mo, WN, Pt, and Ni. The conductive oxide may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), etc. However, this is just illustrative.

[0080] The source electrode 151 and the drain electrode 152 may be provided at both sides of the gate electrode 160, respectively. The source electrode 151 and the drain electrode 152 are provided in the source region and drain region of the channel layer 130, respectively. Here, the source electrode 151 may be provided to contact the source region of the channel layer 130, and the drain electrode 152 may be provided to contact the drain region of the channel layer 130. The source electrode 151 and the drain electrode 152 may include a metal material having excellent electrical conductivity, such as Ag, Au, Pt, or Cu, but the disclosure is not limited thereto.

[0081] FIG. 5A illustrates SEM images of the upper surface of a MoS.sub.2/HfO.sub.2 stacked structure on a Si/SiO.sub.2 substrate, and FIG. 5B illustrates SEM images of the upper surface of a MoS.sub.2/PDI/HfO.sub.2 stacked structure on a Si/SiO.sub.2 substrate. In the stacked structure of FIG. 5A, the MoS.sub.2 layer was deposited as a single layer, and the HfO.sub.2 layer was deposited with a thickness of 10 nm. In the stacked structure of FIG. 5B, the MoS.sub.2 layer and the PDI layer were each deposited as a single layer, and the HfO.sub.2 layer was deposited with a thickness of 10 nm. In this case, the MoS.sub.2 layer has a thickness of about 1 nm, and the PDI layer has a thickness of about 0.5 nm.

[0082] Referring to FIG. 5A, in the MoS.sub.2/HfO.sub.2 stacked structure where the HfO.sub.2 layer is deposited with a thickness of 10 nm on the MoS.sub.2 layer, there are portions (black portions) where HfO.sub.2 is not deposited and portions (white portions) where HfO.sub.2 is thickly deposited, thus indicating that HfO.sub.2 is not uniformly deposited on the MoS.sub.2 layer. Referring to FIG. 5B, in the MoS.sub.2/PDI/HfO.sub.2 stacked structure where the PDI layer is formed on the MoS.sub.2 layer, the SEM images show an overall uniform color distribution, thus indicating that HfO.sub.2 is more uniformly deposited.

[0083] FIGS. 6A to 6D illustrate AFM images of a MoS.sub.2 layer structure, a MoS.sub.2/HfO.sub.2 layer structure, a MoS.sub.2/PTCDA layer structure, and a MoS.sub.2/PTCDA/HfO.sub.2 layer structure on a Si/SiO.sub.2 substrate, respectively. In each of the structures of FIGS. 6A to 6D, the MoS.sub.2 layer was formed as a single layer, the HfO.sub.2 layer was deposited with a thickness of 3 nm, and the PTCDA was formed as a single layer. In the drawings of FIGS. 6A to 6D, the images on the left and right are images of the same object, with the left images being images based on the difference in surface height, and the right images being images based on the difference in surface material (difference in phase). Referring to FIGS. 6A to 6D, it can be seen that the differences in surface height and phase of the MoS.sub.2/PTCDA/HfO.sub.2 layer structure is smaller than that of the MoS.sub.2/HfO.sub.2 layer structure, and thus the surface height and phase appear more uniform.

[0084] Table 1 shows the area capacitance values (F/cm.sup.2) measured for the HfO.sub.2 layer, MoS.sub.2+HfO.sub.2 layer, and MoS.sub.2+PDI+HfO.sub.2 layer according to the thickness of HfO.sub.2. The area capacitance was measured by positioning the structure in Table 1 between metal electrodes (gold). In Table 1, the effective oxide thickness represents a thickness of SiO.sub.2 to have the same capacitance as HfO.sub.2.

[0085] In the MoS.sub.2+HfO.sub.2 layer and MoS.sub.2+PDI+HfO.sub.2 layer, MoS.sub.2 and PDI were each formed as a single layer, and HfO.sub.2 was formed in a thickness value shown in Table 1. Referring to Table 1, in the structure of MoS.sub.2+HfO.sub.2, the capacitance was measured only when HfO.sub.2 was formed to the largest thickness of 34 nm, and the capacitance was not measured due to short circuit when HfO.sub.2 was formed to thicknesses of 13 nm, 7 nm, and 3 nm. This means that as thinner HfO.sub.2 layer is formed on the MoS.sub.2 layer, there are more portions where HfO.sub.2 is not formed. On the other hand, in the structure of MoS.sub.2+PDI+HfO.sub.2, when PDI was formed on the MoS.sub.2 layer, the capacitances were measured for HfO.sub.2 of all thicknesses, and they were almost identical to the capacitance value for a single HfO.sub.2 layer. This shows that thinner HfO.sub.2 can be formed more reliably in the structure of MoS.sub.2+PDI+HfO.sub.2.

TABLE-US-00001 TABLE 1 HfO.sub.2 Effective thick- oxide MoS.sub.2 + ness thickness HfO.sub.2 MoS.sub.2 + HfO.sub.2 PDI + HfO.sub.2 (nm) (nm) (F/cm.sup.2) (F/cm.sup.2) (F/cm.sup.2) 34 5 0.61 0.01 0.65 0.03 0.64 0.03 13 3 1.13 0.03 short circuit 1.39 0.09 7 2 1.79 0.02 short circuit 1.7 0.2 3 1.5 2.2 0.2 short circuit 2.2 0.3

[0086] Hereinafter, a method of manufacturing the above-described semiconductor device 100 according to the embodiment will be described. FIGS. 7A to 7E are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment.

[0087] Referring to FIG. 7A, a two-dimensional material layer 110 may be formed on a substrate 101. The substrate 101 may include various materials such as a semiconductor material, an insulating material, and/or a metal material. Here, the two-dimensional material layer 110 may be formed by depositing and growing a two-dimensional semiconductor material on the surface of the substrate 101. Deposition of the two-dimensional semiconductor material may be performed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like, but example embodiments are not limited thereto.

[0088] TMD is a two-dimensional material having semiconductor properties and is a compound of a transition metal and a chalcogen element. Here, the transition metal may include, for example, at least one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Co, Tc, and Re, and the chalcogen element may include, for example, at least one of S, Se, and Te. Specific examples of the TMD may include MoS.sub.2, MoSe.sub.2, MoTez, WS.sub.2, WSe.sub.2, WTe.sub.2, ZrS.sub.2, ZrSe.sub.2, HfS.sub.2, HfSe.sub.2, NbSe.sub.2, ReSe.sub.2, etc. However, example embodiments are not limited thereto.

[0089] The two-dimensional material layer 110 may have a single-layer or multi-layer structure, where each layer may have an atomic-level thickness. The two-dimensional material layer 110 may include, for example, 1 layer to 10 layers. For example, the two-dimensional material layer 110 may include 1 layer to 5 layers. However, example embodiments are not limited thereto.

[0090] Referring to FIG. 7B, a molecular crystal layer 120 is deposited on the two-dimensional material layer 110 to form a channel layer 130. The molecular crystal layer 120 may be formed of a plate-shaped aromatic compound of C.sub.20-C.sub.40 having a two-dimensional structure. The plate-shaped aromatic compound may include, for example, a tetracene-based compound, a chrysene-based compound, a triphenylene-based compound, a pyrene-based compound, a perylene-based compound, a pentacene-based compound, a benzopyrene-based compound, a benzoperylene-based compound, or a coronene-based compound. The plate-shaped aromatic compound may include, for example, a hydroxyl group, a carboxyl group, a metal carboxylate group, an imide group, an amide group, or a carboxylic anhydride group. Examples of the plate-shaped aromatic compounds may include, but are not limited to, PDI (perylene diimide), Me-PDI (N,N-dimethyl-3,4,9,10-perylenetetracarboxylic diimide), and PTCDA (perylenetetracarboxylic dianhydride).

[0091] The molecular crystal layer 120 may be formed, for example, with a thickness of 1 molecular layer to 5 molecular layers or a thickness of 1 molecular layer to 3 molecular layers. The molecular crystal layer 120 may have a thickness of, for example, about 0.1 nm to about 0.5 nm.

[0092] Referring to FIG. 7C, a gate insulating layer 140 is deposited on the molecular crystal layer 120. The gate insulating layer 140 may be formed of, for example, at least one of silicon oxide (SiO.sub.2), silicon nitride (SiN), hafnium oxide (HfO.sub.2), zirconium oxide (ZrO.sub.2), aluminum oxide (Al.sub.2O.sub.3), yttrium oxide (Y.sub.2O.sub.3), and lanthanum oxide (La.sub.2O.sub.3), or the like, but the disclosure is not limited thereto. The gate insulating layer 140 may be formed to a thickness of, for example, about 2 nm to about 20 nm or, for example, about 2 nm to about 10 nm.

[0093] Referring to FIG. 7D, a gate electrode 160 is formed on the gate insulating layer 140. The gate electrode 160 may be formed of a metal material or a conductive oxide. The metal material may include at least one selected from the group consisting of Au, Ti, TiN, TaN, W, Mo, WN, Pt, and Ni. The conductive oxide may include, for example, at least one of indium tin oxide (ITO), indium zinc oxide (IZO), and the like. However, this is just illustrative.

[0094] Referring to FIG. 7E, a source electrode 151 and a drain electrode 152 are formed on both sides of the channel layer 130. The source electrode 151 and the drain electrode 152 are provided in the source region and drain region of the channel layer 130, respectively. The source electrode 151 may be provided to contact the source region of the channel layer 130, and the drain electrode 152 may be provided to contact the drain region of the channel layer 130.

[0095] FIG. 8 is a schematic cross-sectional view of a semiconductor device 200 according to another embodiment. Hereinafter, differences from the above-described embodiment will be mainly described.

[0096] Referring to FIG. 8, a two-dimensional material layer 210 may include a first region 210a and second regions 210b provided at both sides of the first region 210a. The first region 210a of the two-dimensional material layer 210 may be located at the center portion of the two-dimensional material layer 210. The first region 210a of the two-dimensional material layer 210 may be a channel region corresponding to the gate electrode 160. The second regions 210b of the two-dimensional material layer 210 may be a source region and a drain region corresponding to the source electrode 151 and the drain electrode 152.

[0097] In the present embodiment, the first region 210a of the two-dimensional material layer 210 and the second regions 210b of the two-dimensional material layer 210 may be made of different materials from each other. For example, the two-dimensional semiconductor material of the second regions 210b of the two-dimensional material layer 210 may have higher conductivity than the two-dimensional semiconductor material of the first region 210a of the two-dimensional material layer 210. For example, the two-dimensional semiconductor material of the second regions 210b of the two-dimensional material layer 210 may be a two-dimensional semiconductor material doped with an n-type dopant or a p-type dopant. As the p-type dopant and the n-type dopant, for example, p-type dopants and n-type dopants used in graphene or carbon nanotubes (CNTs) may be used. Nb may be used as the p-type dopant, but the disclosure is not limited thereto. Re may be used as the n-type dopant, but the disclosure is not limited thereto. The p-type dopant or n-type dopant may be doped by ion implantation or chemical doping. Alternatively, the two-dimensional semiconductor material of the second regions 210b of the two-dimensional material layer 210 may be, for example, graphene or a metallic two-dimensional material. 1T-MoS.sub.2 or PtSe.sub.2 may be used as the metallic two-dimensional material, but the disclosure is not limited thereto. Contact resistance may be improved by increasing the conductivity of the second regions 210b, thus improving device performance.

[0098] FIG. 9 is a schematic cross-sectional view of a semiconductor device 300 according to another embodiment. Hereinafter, differences from the above-described embodiment will be mainly described.

[0099] Referring to FIG. 9, a molecular crystal layer 320 may include a first region 320a and second regions 320b provided at both sides of the first region 320a. The first region 320a of the molecular crystal layer 320 may be located at the center portion of the molecular crystal layer 320. The first region 320a of the molecular crystal layer 320 may be a channel region corresponding to the gate electrode 160. The second regions 320b of the molecular crystal layer 320 may be a source region and a drain region corresponding to the source electrode 151 and the drain electrode 152.

[0100] In the present embodiment, the first region 320a of the molecular crystal layer 320 and the second regions 320b of the molecular crystal layer 320 may be made of different materials from each other. In an embodiment, the plate-shaped aromatic compound of the second regions 320b of the molecular crystal layer 320 may include a compound capable of modulation-doping the second regions 210b of the two-dimensional material layer 210. For example, for modulation-doping, the second regions 320b may include a plate-shaped aromatic compound including metal ions. Examples of the metal ions may include Al.sup.3+, Mg.sup.2+, Mn.sup.2+, Zn.sup.2+, Co.sup.2+, Fe.sup.3+, Ni.sup.2+, and the like.

[0101] The conductivity of the second regions 210b of the two-dimensional material layer 210 can be increased by modulation-doping, thereby improving contact resistance and thus enhancing device performance. In an embodiment, the first region 320a of the molecular crystal layer 320 may not be doped.

[0102] In the above-described embodiments, semiconductor devices 100 to 300 having a planar structure were described as examples. However, the disclosure is not limited thereto, and for example, a semiconductor device having a Fin Field Effect Transistor (FinFET) structure or a semiconductor device having a Gate-All-Around FET (GAA FET) (e.g., Multi Bridge Channel FET (MBCFET)) or Complementary Field Effect Transistor (CFET) (e.g., Vertical CFET) structure may be provided.

[0103] FIG. 10A is a perspective view schematically illustrating a semiconductor device (FinFET, 500) according to another embodiment, and FIG. 10B is a cross-sectional view taken along the line A-A of FIG. 10A.

[0104] Referring to FIGS. 10A and 10B, an insulator 505 is provided on a substrate 501 and may be perpendicular to the substrate 501, and a channel layer 530 may be provided to cover the insulator 505. Here, the channel layer 530 may have a fin shape.

[0105] The channel layer 530 may include a two-dimensional material layer 510 and a molecular crystal layer 520. For the two-dimensional material layer 510 and the molecular crystal layer 520, refer to the above-described two-dimensional material layer 110 and molecular crystal layer 120.

[0106] The two-dimensional material layer 510 may include a first region 510a and second regions 510b provided at both sides of the first region 510a. Similarly, the molecular crystal layer 520 may include a first region 520a and second regions 520b provided at both sides of the first region 520a.

[0107] Three sides of the first region 510a of the two-dimensional material layer 510 and three sides of the first region 520a of the molecular crystal layer 520 are surrounded by a gate electrode 560, and may become channel regions. The second regions 510b of the two-dimensional material layer 510 and the second regions 520b of the molecular crystal layer 520 are located outside the gate electrode 560, and may become source/drain regions.

[0108] A gate insulating layer 540 is provided between the gate electrode 560 and the first region 520a of the molecular crystal layer 520. The gate insulating layer 540 is provided to surround three sides of the channel layer 530, specifically, the first region 520a of the molecular crystal layer 520, and the gate electrode 560 may be provided to surround three sides of the gate insulating layer 540. Although not shown in the drawings, source and drain electrodes may be provided in the second regions 520b of the molecular crystal layer 520.

[0109] In an embodiment, the first region 510a of the two-dimensional material layer 510 and the second regions 510b of the two-dimensional material layer 510 may be made of different materials from each other. For example, the two-dimensional semiconductor material of the second regions 510b of the two-dimensional material layer 510 may have higher conductivity than the two-dimensional semiconductor material of the first region 510a of the two-dimensional material layer 510. In this regard, refer to those described above with respect to the channel layer 230 of FIG. 8.

[0110] In another embodiment, the first region 520a of the molecular crystal layer 520 and the second regions 520b of the molecular crystal layer 520 may be made of different materials from each other. For example, the plate-shaped aromatic compound of the second regions 520b of the molecular crystal layer 520 may include a compound capable of modulation-doping the second regions 510b of the two-dimensional material layer 510. The first region 520a of the molecular crystal layer 520 may not be doped. In this regard, refer to those described above with respect to the channel layer 330 of FIG. 9.

[0111] FIG. 11A is a perspective view schematically illustrating a semiconductor device (MBCFET, 600) according to another embodiment, and FIG. 11B is a cross-sectional view taken along the line B-B of FIG. 11A.

[0112] Referring to FIGS. 11A and 11B, one or more channel layers 630 are arranged over a substrate 601 to be spaced apart from the substrate 601. Here, each of the channel layers 630 may have a sheet shape arranged parallel to the substrate 601. FIGS. 11A and 11B illustrate a case in which two channel layers 630 are arranged vertically over the substrate 601.

[0113] Each of the channel layers 630 may include a two-dimensional material layer 610 and a molecular crystal layer 620. For the two-dimensional material layer 610 and the molecular crystal layer 620, refer to the above-described two-dimensional material layer 110 and molecular crystal layer 120. In the present embodiment, since both the upper and lower surfaces of the channel layer 630 are in contact with a gate insulating layer 640, the molecular crystal layers 620 may be formed on both the upper and lower surfaces of the two-dimensional material layer 610.

[0114] FIG. 12 is a conceptual diagram of a channel layer 630 according to another embodiment. Referring to FIG. 12, molecular crystal layer 620 are formed on and beneath a two-dimensional material layer 610, and both the two-dimensional material layer 610 and the molecular crystal layer 620 are formed as a single layer. In FIG. 12, each spherical shape represents an element constituting a two-dimensional semiconductor material and a plate-shaped aromatic compound. Since the molecular crystal layer 620 is made of the plate-shaped aromatic compound according to the embodiment, it may have crystallinity due to the crystal structure of the two-dimensional material layer 610. In other words, the channel layer 630 in FIG. 12 may include a two-dimensional material layer 610 sandwiched between a pair of molecular crystal layers 620. The channel layer 630 in FIG. 12 may replace any of the channel layers 130, 230, 330, 530, and 630 of the semiconductor devices 100 to 600 described above. Although not shown in the drawings, the channel layer 630 may include a first region between second regions, and materials of the two-dimensional material layer 610, or materials of the two-dimensional material layer 610 and molecular crystal layer 620 each respectively may be different materials in the first region and second regions of the channel layer 630. In this regard, refer to those described above with respect to the channel layer 230 of FIG. 8 and the channel layer 330 of FIG. 9.

[0115] Referring again to FIGS. 11A and 11B, each of the two-dimensional material layers 610 may include a first region 610a and second regions 610b provided at both sides of the first region 610a. Similarly, each of the molecular crystal layers 620 may include a first region 620a and second regions 620b provided at both sides of the first region 620a.

[0116] Four sides of the first region 610a of the two-dimensional material layer 610 and four sides of the first region 620a of the molecular crystal layer 620 are surrounded by a gate electrode 660, and may become channel regions. The second regions 610b of the two-dimensional material layer 610 and the second regions 620b of the molecular crystal layer 620 are located outside the gate electrode 660, and may become source/drain regions.

[0117] A gate insulating layer 640 is provided between the gate electrode 660 and the first region 620a of the molecular crystal layer 620. The gate insulating layer 640 is provided to surround four sides of the channel layer 630, specifically, the first region 620a of the molecular crystal layer 620, and the gate electrode 660 may be provided to surround four sides of the gate insulating layer 640. Although not shown in the drawings, source and drain electrodes may be provided in the second regions 620b of the molecular crystal layer 620. It is also possible for an insulator (not shown) to be placed on the substrate 601 in parallel to the substrate 601 and for the channel layer 630 to be provided to surround the insulator.

[0118] The above-described semiconductor devices 100 to 600 may be applied to memory devices such as DRAMs. The memory device may have a structure in which the above-described semiconductor devices 100 to 600 are electrically connected with capacitors. Additionally, the semiconductor devices 100 to 600 may be applied to various electronic apparatuses. For example, the above-described semiconductor devices 100 to 600 may be used for arithmetic operations, program execution, temporary data retention, etc. in electronic apparatuses such as mobile devices, computers, laptops, sensors, network devices, neuromorphic devices, etc.

[0119] FIGS. 13 and 14 are conceptual diagrams schematically illustrating an electronic device architecture capable of being applied to electronic apparatuses according to an embodiment.

[0120] Referring to FIG. 13, an electronic device architecture 1000 may include a memory unit 1010, an arithmetic logic unit (ALU) 1020, and a control unit 1030. The memory unit 1010, the arithmetic logic unit (ALU) 1020, and the control unit 1030 may be electrically connected to each other. For example, the electronic device architecture 1000 may be implemented as a single chip including the memory unit 1010, the ALU 1020, and the control unit 1030.

[0121] Specifically, the memory unit 1010, the ALU 1020, and the control unit 1030 may be interconnected on-chip through metal lines to communicate directly. The memory unit 1010, the ALU 1020, and the control unit 1030 may be monolithically integrated on one substrate to form one chip. The electronic device architecture (chip) 1000 may be connected to input/output devices 2000 (e.g., keyboard, display, or mouse).

[0122] The ALU 1020 and the control unit 1030 may each independently include the above-described semiconductor devices 100 to 600, and the memory unit 1010 may include the semiconductor devices 100 to 600, capacitors, or a combination thereof. The memory unit 1010 may include both a main memory and a cache memory. This electronic device architecture (chip) 1000 may be an on-chip memory processing unit.

[0123] Referring to FIG. 14, a cache memory 1510, an ALU 1520, and a control unit 1530 may be part of a central processing unit (CPU) 1500. The cache memory 1510 may be formed of a static random access memory (SRAM), and may include the above-described semiconductor devices 100 to 600. In addition to the CPU 1500, a main memory 1600 and an auxiliary storage 1700 may be provided. The main memory 1600 may include a dynamic random access memory (DRAM) device.

[0124] In some cases, the electronic device architecture may be implemented in a form in which computing unit devices and memory unit devices are adjacent to each other on one chip, without distinction between sub-units. Although embodiments have been described above, they are merely exemplary, and various modifications can be made therefrom by those skilled in the art.

[0125] In the semiconductor device according to an embodiment, the presence of a molecular crystal layer on a two-dimensional material layer may enable a source/drain metal structure or a gate stacked structure to be formed more thinly and/or more uniformly. In addition, since the molecular crystal layer has improved or excellent chemical and/or thermal stability, it can protect the two-dimensional material layer better, and thereby prevent deterioration of device performances due to damage of the two-dimensional material layer.

[0126] One or more of the elements disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.

[0127] It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.