MOTOR DRIVER CIRCUIT FOR LINEAR MOTOR, POSITIONING DEVICE USING THE SAME, AND HARD DISK DEVICE

Abstract

Disclosed herein is a motor driver circuit including a logic circuit that generates a second code which changes linearly with a slope “a” with respect to a first code based on a position command for a linear motor to be driven and that can switch the slope “a,” a D/A converter that converts the second code into an analog control signal, and a driver that drives the linear motor such that a current detection signal indicating a drive current of the linear motor approaches a target value that changes linearly with a slope “g” with respect to the control signal, the driver being configured to switch the slope “g.” The motor driver circuit is switchable between a first state in which g=g.sub.1 and a=a.sub.1 and a second state in which g=g.sub.2 (where |g.sub.2|>|g.sub.1|) and a=a.sub.2=a.sub.1×(g.sub.1/g.sub.2).

Claims

1. A motor driver circuit comprising: a logic circuit that generates a second code that changes linearly with a slope “a” with respect to a first code based on a position command for a linear motor to be driven, the logic circuit being configured to switch the slope “a”; a digital-to-analog converter that converts the second code into an analog control signal; and a driver that drives the linear motor such that a current detection signal V.sub.CS indicating a drive current of the linear motor approaches a target value V.sub.REF that changes linearly with a slope “g” with respect to the control signal, the driver being configured to switch the slope “g,” wherein the motor driver circuit is switchable between a first state and a second state, in the first state, g=g.sub.1 and a=a.sub.1, and in the second state, g=g.sub.2 (where |g.sub.2|>|g.sub.1|) and a=a.sub.2=a.sub.1×(g.sub.1/g.sub.2).

2. The motor driver circuit according to claim 1, further comprising: a sample and hold circuit connected between the digital-to-analog converter and the driver.

3. The motor driver circuit according to claim 2, wherein, when a value of the first code at a time of switching from the first state to the second state is X.sub.TH, the logic circuit gradually changes the second code from a value when a=a.sub.1 to a value when a=a.sub.2, and, during the gradual change of the second code, the sample and hold circuit supplies the control signal sampled before the gradual change to the driver.

4. The motor driver circuit according to claim 2, wherein, when a value of the first code at a time of switching from the second state to the first state is X.sub.TH, the logic circuit gradually changes the second code from a value when a=a.sub.2 to a value when a=a.sub.1, and the sample and hold circuit samples the control signal before the gradual change starts, and supplies the sampled control signal to the driver during the gradual change of the second code.

5. The motor driver circuit according to claim 2, wherein the sample and hold circuit includes an input node connected to the digital-to-analog converter, an output node connected to the driver, a first switch connected between the input node and the output node, a capacitor having one end grounded, a second switch connected between another end of the capacitor and the input node, a buffer that receives a voltage at the another end of the capacitor, and a third switch connected between an output of the buffer and the output node, and the sample and hold circuit is switchable between a tracking state in which the first switch and the second switch are on and the third switch is off and a hold state in which the first switch and the second switch are off and the third switch is on.

6. The motor driver circuit according to claim 5, wherein the sample and hold circuit is further switchable to a through state in which the first switch is on and the second switch and the third switch are off.

7. The motor driver circuit according to claim 6, wherein, in a transition period between the first state and the second state, the sample and hold circuit samples the control signal by transitioning from the tracking state to the through state, after the sample and hold circuit completes a sampling operation, the logic circuit gradually changes the second code, and, after completion of the gradual change of the second code, a gain of the driver changes and the sample and hold circuit transitions to the through state, and the sample and hold circuit subsequently transitions to the tracking state.

8. The motor driver circuit according to claim 1, wherein the driver includes a feedback circuit that generates a voltage command signal such that the current detection signal V.sub.CS approaches the target value V.sub.REF, and an output stage that amplifies the voltage command signal and applies the amplified voltage command signal to the linear motor.

9. The motor driver circuit according to claim 8, wherein the feedback circuit includes a current sense amplifier that generates a feedback signal that changes linearly with respect to the current detection signal V.sub.CS and that becomes a predetermined level V.sub.CMREF when V.sub.CS=0.

10. The motor driver circuit according to claim 9, further comprising: a sense resistor disposed on a path of the drive current of the linear motor, wherein the current sense amplifier includes a first operational amplifier, a first resistor connected between an inverting input of the first operational amplifier and one end of the sense resistor, a second resistor connected between the inverting input of the first operational amplifier and an output of the first operational amplifier, a third resistor connected between a non-inverting input of the first operational amplifier and another end of the sense resistor, and a fourth resistor having one end that receives the predetermined level V.sub.CMREF and another end connected to the non-inverting input of the first operational amplifier, and the feedback signal corresponds to an output voltage of the first operational amplifier.

11. The motor driver circuit according to claim 9, wherein the feedback circuit further includes an error amplifier that outputs the voltage command signal such that the feedback signal approaches a target level based on the control signal.

12. The motor driver circuit according to claim 11, wherein the error amplifier includes a first input node that receives the feedback signal, a second input node that receives the control signal, a second operational amplifier having an inverting input, a non-inverting input that receives the predetermined level V.sub.CMREF, and an output, a fifth resistor connected between the inverting input of the second operational amplifier and the first input node, and a sixth resistor connected between the inverting input of the second operational amplifier and the second input node, the voltage command signal corresponds to a voltage at the output of the second operational amplifier, and the sixth resistor is a variable resistor.

13. The motor driver circuit according to claim 8, wherein the output stage includes a first amplifier that amplifies the voltage command signal without inversion, and a second amplifier that inverts and amplifies the voltage command signal.

14. The motor driver circuit according to claim 1, wherein the linear motor is a voice coil motor.

15. The motor driver circuit according to claim 1, wherein the motor driver circuit is integrated on a single semiconductor substrate.

16. A positioning device comprising: a linear motor; and the motor driver circuit according to claim 1, the motor driver circuit driving the linear motor.

17. A hard disk device comprising: the positioning device according to claim 16.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. 1 is a block diagram of a positioning device including a motor driver circuit according to a first embodiment;

[0012] FIG. 2 is a diagram illustrating a relation between a first code x and a second code y in a first state and a second state;

[0013] FIG. 3 is a diagram illustrating input/output characteristics of the motor driver circuit of FIG. 1;

[0014] FIG. 4 is a diagram for describing an operation of a motor driver circuit according to a comparative technology;

[0015] FIG. 5 is a circuit diagram illustrating an example of a specific configuration of the motor driver circuit;

[0016] FIG. 6 is a block diagram of a positioning device including a motor driver circuit according to a second embodiment;

[0017] FIG. 7 is a time chart for describing an operation of the motor driver circuit of FIG. 6;

[0018] FIG. 8 is a circuit diagram illustrating an example of a specific configuration of the motor driver circuit;

[0019] FIG. 9 is a diagram for describing an operation of the motor driver circuit of FIG. 8; and

[0020] FIG. 10 is a view of a hard disk device including the motor driver circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Overview of Embodiments

[0021] An overview of some exemplary embodiments of the present disclosure is described. This overview serves as the preamble of the following detailed description and is intended to simplify and describe some concepts of one or more embodiments for the purpose of basic understanding of the embodiments. It is noted that this overview is not intended to limit the scope of the disclosure. This overview is not a comprehensive overview of all the conceivable embodiments and is not intended to identify key elements of all the embodiments or delineate the scope of part or all of the aspects. For the sake of convenience, “one embodiment” may refer to one or more embodiments (embodiments and modifications) disclosed in the present specification.

[0022] A motor driver circuit according to one embodiment includes a logic circuit that generates a second code that changes linearly with a slope “a” with respect to a first code based on a position command for a linear motor to be driven, the logic circuit being configured to switch the slope “a,” a D/A converter that converts the second code into an analog control signal, and a driver that drives the linear motor such that a current detection signal V.sub.CS indicating a drive current of the linear motor approaches a target value V.sub.REF that changes linearly with a slope “g” with respect to the control signal, the driver being configured to switch the slope “g,” in which the motor driver circuit is switchable between a first state and a second state, in the first state, g=g.sub.1 and a=a.sub.1, and in the second state, g=g.sub.2 (where |g.sub.2|>|g.sub.1|) and a=a.sub.2=a.sub.1×(g.sub.1/g.sub.2).

[0023] The slope “g” of the driver is a gain of the motor driver circuit. By changing the gain “g” as well as the slope “a” of the logic circuit between the first state and the second state, it is possible to continuously change the linear motor with respect to the first code. The gain g.sub.2 in the second state is relatively high. Therefore, a control range of the drive current of the linear motor can be extended. In the first state, the relatively low gain g.sub.1 is selected. Therefore, noise can be suppressed. In other words, noise can be reduced in a certain current range while a wide current control range is secured.

[0024] In one embodiment, the motor driver circuit may further include a sample and hold circuit connected between the D/A converter and the driver. If the second code changes discontinuously when the slope “a” is changed, the control signal, which is the output of the D/A converter, may result in overshooting or undershooting, generating a glitch in the drive current. By inserting the sample and hold circuit and fixing an input into the driver while the control signal fluctuates, it is possible to suppress a glitch in the drive current.

[0025] When a value of the first code at a time of switching from the first state to the second state is x.sub.TH, the logic circuit may gradually change the second code from a value when a=a.sub.1 to a value when a=a.sub.2. During the gradual change of the second code, the sample and hold circuit may supply the control signal sampled in the first state to the driver.

[0026] A glitch in the drive current can be suppressed by gradually changing the second code, keeping the control signal fixed by the sample and hold circuit during the gradual change, and switching the control signal to a correct voltage level at the same time as the gain switching after completion of the gradual change.

[0027] When a value of the first code at a time of switching from the second state to the first state is x.sub.TH, the logic circuit may gradually change the second code from a value when a=a.sub.2 to a value when a=a.sub.1. The sample and hold circuit may sample the control signal before the gradual change starts, and supply the sampled control signal to the driver during the gradual change of the second code. With this configuration, a glitch in the drive current can be suppressed.

[0028] In one embodiment, the sample and hold circuit may include an input node connected to the D/A converter, an output node connected to the driver, a first switch connected between the input node and the output node, a capacitor having one end grounded, a second switch connected between another end of the capacitor and the input node, a buffer that receives a voltage at the another end of the capacitor, and a third switch connected between an output of the buffer and the output node. The sample and hold circuit may be switchable between a tracking state in which the first switch and the second switch are on and the third switch is off and a hold state in which the first switch and the second switch are off and the third switch is on.

[0029] In one embodiment, the sample and hold circuit may be further switchable to a through state in which the first switch is on and the second switch and the third switch are off.

[0030] In one embodiment, in a transition period between the first state and the second state, the sample and hold circuit may sample the control signal by transitioning from the tracking state to the through state. After the sample and hold circuit completes a sampling operation, the logic circuit may gradually change the second code. After completion of the gradual change of the second code, a gain of the driver may change and the sample and hold circuit may transition to the through state. The sample and hold circuit may subsequently transition to the tracking state.

[0031] In one embodiment, the driver may include a feedback circuit that generates a voltage command signal such that the current detection signal V.sub.CS approaches the target value V.sub.REF, and an output stage that amplifies the voltage command signal and applies the amplified voltage command signal to the linear motor.

[0032] In one embodiment, the feedback circuit may include a current sense amplifier that generates a feedback signal that changes linearly with respect to the current detection signal V.sub.CS and that becomes a predetermined level V.sub.CMREF when V.sub.CS=0.

[0033] In one embodiment, the motor driver circuit may further include a sense resistor disposed on a path of the drive current of the linear motor. The current sense amplifier may include a first operational amplifier, a first resistor connected between an inverting input of the first operational amplifier and one end of the sense resistor, a second resistor connected between the inverting input of the first operational amplifier and an output of the first operational amplifier, a third resistor connected between a non-inverting input of the first operational amplifier and another end of the sense resistor, and a fourth resistor having one end that receives the predetermined level V.sub.CMREF and another end connected to the non-inverting input of the first operational amplifier. The feedback signal may correspond to an output voltage of the first operational amplifier.

[0034] In one embodiment, the feedback circuit may further include an error amplifier that outputs the voltage command signal such that the feedback signal approaches a target level based on the control signal.

[0035] In one embodiment, the error amplifier may include a first input node that receives the feedback signal, a second input node that receives the control signal, a second operational amplifier having an inverting input, a non-inverting input that receives the predetermined level V.sub.CMREF, and an output, a fifth resistor connected between the inverting input of the second operational amplifier and the first input node, and a sixth resistor connected between the inverting input of the second operational amplifier and the second input node. The voltage command signal may correspond to a voltage at the output of the second operational amplifier. The sixth resistor may be a variable resistor. The gain of the driver can be controlled according to a resistance value of the sixth resistor.

[0036] In one embodiment, the output stage may include a first amplifier that amplifies the voltage command signal without inversion, and a second amplifier that inverts and amplifies the voltage command signal.

[0037] In one embodiment, the linear motor may be a voice coil motor.

[0038] In one embodiment, the motor driver circuit may be integrated on a single semiconductor substrate. The term “integrated” herein may include a case where all the constituent components of a circuit are formed on a semiconductor substrate or a case where main constituent components of the circuit are integrated thereon, and some resistors and capacitors, for example, may be disposed outside the semiconductor substrate in order to adjust circuit constants. By integrating a circuit on a single chip, it is possible to reduce a circuit area and keep characteristics of circuit elements uniform.

[0039] A positioning device according to one embodiment includes a linear motor, and any of the above-described motor driver circuits that drives the linear motor.

[0040] A hard disk device according to one embodiment includes the positioning device described above.

EMBODIMENTS

[0041] Hereinafter, preferred embodiments are described with reference to the drawings. The same or equivalent constituent components, members, and processes illustrated in the drawings are denoted by the same reference signs, and redundant description is omitted as appropriate. The embodiments are described for exemplary purposes only and are by no means intended to limit the present disclosure. All the features and combinations described in the embodiments are not necessarily essential to the disclosure.

[0042] In the present specification, “the state in which a member A is connected to a member B” includes not only the state in which the member A and the member B are physically directly connected to each other but also the state in which the member A and the member B are indirectly connected to each other via another member that has no substantial effect on the electrical connection between them or that does not impair a function or an effect produced by the connection between them.

[0043] Similarly, “the state in which a member C is disposed between the member A and the member B” includes not only the state in which the member A and the member C or the member B and the member C are directly connected to each other but also the state in which the member A and the member C or the member B and the member C are indirectly connected to each other via another member that has no substantial effect on the electrical connection between them or that does not impair a function or an effect produced by the connection between them.

[0044] The vertical and horizontal axes of the waveform diagrams and time charts referred to in the present specification are enlarged or reduced as appropriate for ease of understanding, and each waveform illustrated therein is also simplified for ease of understanding.

[0045] FIG. 1 is a block diagram of a positioning device 100, which includes a motor driver circuit 200 according to a first embodiment. The positioning device 100 includes a linear motor 102, a host controller 104, and the motor driver circuit 200.

[0046] The host controller 104 integrally controls the positioning device 100. The host controller 104 generates position control data POS, which indicates a target position of the linear motor 102, and transmits the position control data POS to the motor driver circuit 200. The host controller 104 includes, for example, a microcontroller, a field programmable gate array (FPGA), or an application specific integrated circuit (ASIC).

[0047] The motor driver circuit 200 receives the position control data POS and supplies a drive current I.sub.DRV with the amount corresponding to the position control data POS to the linear motor 102. The linear motor 102 is, for example, a voice coil motor, and its movable element is displaced by the amount corresponding to the drive current I.sub.DRV flowing through the linear motor 102.

[0048] A configuration of the motor driver circuit 200 is described next. The motor driver circuit 200 includes an interface circuit 210, a logic circuit 220, a D/A converter 230, and a driver 240. The motor driver circuit 200 is a functional integrated circuit (IC) integrated on a single semiconductor substrate.

[0049] The interface circuit 210 is connected to the host controller 104 and receives the position control data POS. The interface circuit 210 may be, for example, an inter IC (I.sup.2C) interface or a serial peripheral interface (SPI).

[0050] The logic circuit 220 generates a first code x according to the position control data POS. For example, when the position control data POS is changed, the logic circuit 220 gradually changes the first code x from a value based on the position control data POS that has not yet been changed to a value based on the position control data POS that has been changed.

[0051] The logic circuit 220 generates a second code y that changes linearly with a slope “a” with respect to the first code x. The logic circuit 220 is capable of switching the slope “a” between at least two values a.sub.1 and a.sub.2. By generalization, the following equation is obtained.

y=ax+b   (1) [0052] Note that “b” is a constant.

[0053] The D/A converter 230 converts the second code y into an analog control signal V.sub.DAC. For example, the D/A converter 230 includes a converter 232 and a buffer (digital-to-analog converter (DAC) amplifier) 234. The input/output characteristics of the D/A converter 230 are expressed by the following equation.

V.sub.DAC=K.sub.DAC.Math.y   (2)

[0054] The driver 240 receives a current detection signal V.sub.CS, which indicates the drive current I.sub.DRV of the linear motor 102, and the control signal V.sub.DAC. The current detection signal V.sub.CS changes linearly with respect to the drive current I.sub.DRV. For example, the current detection signal V.sub.CS is proportional to the drive current I.sub.DRV, and the following relation holds.

V.sub.CS=α.Math.I.sub.DRV   (3)

[0055] The driver 240 drives the linear motor 102 by feedback such that the current detection signal V.sub.CS approaches its target value V.sub.REF. The target value V.sub.REF of the current detection signal V.sub.CS changes linearly with a slope “g” with respect to the control signal V.sub.DAC. By generalization, the following relation holds between the target value V.sub.REF of the current detection signal V.sub.CS and the control signal V.sub.DAC.

V.sub.REF=g×(V.sub.DAC−V.sub.0)   (4)

[0056] V.sub.0 is a reference voltage V.sub.REF when the drive current I.sub.DRV is zero. V.sub.0 is any constant including zero. Further, “g” may be positive or negative.

[0057] The slope “g” is a gain of the driver 240 and can be switched between at least two values g.sub.1 and g.sub.2. The gain “g” of the driver 240 is controlled by the logic circuit 220.

[0058] In other words, when the drive current I.sub.DRV is stabilized by feedback, V.sub.CS=V.sub.REF holds. That is, since the equations (3) and (4) become equal to each other, the following equation (5) holds.

α.Math.I.sub.DRV=g×(V.sub.DAC−V.sub.0)   (5)

[0059] Therefore, the drive current I.sub.DRV is expressed by the following equation (6) and changes linearly with respect to the control signal V.sub.DAC.

I.sub.DRV=g/α×(V.sub.DAC−V.sub.0)   (6)

[0060] For example, V.sub.0 is determined such that I.sub.DRV=0 when the first code x is a center value x.sub.c.

[0061] The motor driver circuit 200 is switchable between a first state φ.sub.1 and a second state φ.sub.2. [0062] First State φ.sub.1

g=g.sub.1, a=a.sub.1 [0063] Second State φ.sub.2

g=g.sub.2 (where |g.sub.2|>|g.sub.1|)

a=a.sub.2=a.sub.1×(g.sub.1/g.sub.2)

[0064] That is, a product of “g” and “a” is the same between the first state φ.sub.1 and the second state φ.sub.2).

[0065] For example, the logic circuit 220 adaptively selects the first state φ.sub.1 and the second state φ.sub.2 depending on the value of the first code x. That is, when the first code x is within a predetermined range, the logic circuit 220 selects the first state φ.sub.1. When the first code x is out of the predetermined range, the logic circuit 220 selects the second state φ.sub.2. In other words, the logic circuit 220 automatically selects the first state φ.sub.1 and the second state φ.sub.2 without external control. Here, it is assumed that the predetermined range is x.sub.a to x.sub.b. When x.sub.a<x<x.sub.b, the logic circuit 220 selects the first state φ.sub.1. When x<x.sub.a or x.sub.b<x, the logic circuit 220 selects the second state φ.sub.2.

[0066] FIG. 2 is a diagram illustrating the relation between the first code x and the second code y in the first state φ.sub.1 and the second state φ.sub.2. In the first state φ.sub.1 where x.sub.a<x<x.sub.b, the slope of the second code y is Δy/Δx=a.sub.1. In the second state φ.sub.2 where x<x.sub.a or x.sub.b<x, the slope of the second code y is Δy/Δx=a.sub.2.

[0067] The configuration of the motor driver circuit 200 is as described above. An operation of the motor driver circuit 200 is described next.

First State φ.SUB.1

[0068] In the first state φ.sub.1, the following relation holds.

y=a.sub.1x   (1a)

[0069] Further, the control signal V.sub.DAC is as follows.

V.sub.DAC=K.sub.DAC.Math.a.sub.1x   (2a)

[0070] Substituting this into the equation (6) together with g=g.sub.1 obtains the following equation (6a).

I.sub.DRV=g/α×(V.sub.DAC−V.sub.0)=g.sub.1/α×(K.sub.DAC.Math.a.sub.1x−V.sub.0)   (6a)

[0071] This is the input/output characteristics of the motor driver circuit 200 in the first state φ.sub.1. The drive current I.sub.DRV changes linearly with respect to the first code x, and its slope ΔI.sub.DRV/Δx is as follows.

ΔI.sub.DRV/Δx=g.sub.1/α×K.sub.DAC.Math.p   (7a)

Second State φ.SUB.2

[0072] In the second state φ.sub.2, the following relation holds.

y=a.sub.2x   (1b)

[0073] Further, the control signal V.sub.DAC is as follows.

V.sub.DAC=K.sub.DAC.Math.a.sub.2x   (2b)

[0074] Substituting this into the equation (6) together with g=g.sub.2 obtains the following equation (6b).

I.sub.DRV=g/α×(V.sub.DAC−V.sub.0)=g.sub.2/α×(K.sub.DAC.Math.a.sub.2x−V.sub.0)   (6b)

[0075] This is the input/output characteristics of the motor driver circuit 200 in the second state φ.sub.2. The drive current I.sub.DRV changes linearly with respect to the first code x, and its slope ΔI.sub.DRV/Δx is as follows.

ΔI.sub.DRV/Δ.sub.x=g.sub.2/α×K.sub.DAC.Math.a.sub.2   (7b)

[0076] As described above, the following relation holds.

a.sub.2=a.sub.1×(g.sub.1/g.sub.2)

[0077] Substituting this into the equation (7b) obtains the following equation (7b′).

ΔI.sub.DRV/Δx=g.sub.2/g.sub.2×K.sub.DAC.Math.a.sub.1×(g.sub.1/g.sub.2)=g.sub.1/α×K.sub.DAC.Math.a.sub.1   (7b′)

[0078] This matches the equation (7a) of the slope in the first state ℠.sub.1.

[0079] FIG. 3 is a diagram illustrating the input/output characteristics of the motor driver circuit 200 of FIG. 1. Here, it is assumed that “g” is positive and V.sub.0 is positive in the driver 240. The gain “g” is switched between the first state φ.sub.1 and the second state φ.sub.2. Moreover, the slope “a” of the logic circuit 220 is switched such that the product with the gain “g” is constant. With this configuration, the relation between the first code x and the drive current I.sub.DRV can be the same between the first state φ.sub.1 and the second state φ.sub.2. In other words, from the viewpoint of the host controller 104, the input/output characteristics of the motor driver circuit 200 are the same.

[0080] In the first state φ.sub.1, the low value g.sub.1 is selected as the gain “g” of the driver 240. Therefore, noise generated by the driver 240 can be suppressed. Specifically, in the range −I.sup.TH to +I.sup.TH of the drive current I.sub.DRV that corresponds to the range x.sub.a to x.sub.b of the first code, the low gain g.sub.1 is selected and noise is suppressed.

[0081] The advantages of the motor driver circuit 200 become clear by contrast with a comparative technology.

[0082] FIG. 4 is a diagram for describing an operation of a motor driver circuit according to a comparative technology. With the comparative technology, the low gain g.sub.1 is set in the entire range, and noise generated by the driver 240 can be kept small.

[0083] Here, when the gain g.sub.1 of the driver 240 is low and it is desired to generate a large drive current I.sub.DRV, in other words, when it is desired to extend a motion range of the linear motor 102, a voltage level of the control signal V.sub.DAC needs to be increased. However, a voltage range that any signal can take in an analog circuit is restricted by a power supply voltage V.sub.DD. Therefore, since the control signal V.sub.DAC is clamped in a region where the first code x is large, the range of the drive current I.sub.DRV is narrower than that of the case where the gain “g” is large.

[0084] On the other hand, in the present embodiment, the gain g.sub.2 is high in the second state φ.sub.2. Accordingly, a maximum value I.sub.MAX of the drive current I.sub.DRV of the linear motor 102 can be increased, and a control range of the drive current I.sub.DRV can be extended. In the first state φ.sub.1, noise can be suppressed by selecting the relatively low gain g.sub.1. In other words, while a wide current control range is secured, noise can be reduced in a certain current range.

[0085] Next, an example of a specific configuration of the motor driver circuit 200 is described. FIG. 5 is a circuit diagram illustrating an example of a specific configuration of the motor driver circuit 200.

[0086] The linear motor 102 and a current sense resistor R.sub.S are connected in series between output pins AOUT and BOUT of the motor driver circuit 200. A voltage drop proportional to the drive current I.sub.DRV occurs across the current sense resistor R.sub.S. The voltage drop across the current sense resistor R.sub.S is fed back as the current detection signal V.sub.CS between current sense pins ISNS and KSNS of the motor driver circuit 200.

V.sub.CS=R.sub.S×I.sub.DRV   (8)

[0087] The driver 240 includes a feedback circuit 250 and an output stage 260. The feedback circuit 250 generates a voltage command signal V.sub.EAOUT such that the current detection signal V.sub.CS approaches the target value V.sub.REF. The output stage 260 amplifies the voltage command signal V.sub.EAOUT and applies the amplified voltage command signal V.sub.EAOUT to the linear motor 102.

[0088] The feedback circuit 250 includes a current sense amplifier 252 and an error amplifier 254.

[0089] The current sense amplifier 252 generates a feedback signal V.sub.FB, which changes linearly with respect to the current detection signal V.sub.CS and which becomes a predetermined level V.sub.CMREF when V.sub.CS=0 (i.e., I.sub.DRV=0).

[0090] The current sense amplifier 252 includes a first operational amplifier OA1, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4.

[0091] The first resistor R1 is connected between an inverting input (−) of the first operational amplifier OA1 and one end (ISNS pin) of the sense resistor R.sub.S. The second resistor R2 is connected between the inverting input (−) of the first operational amplifier OA1 and an output of the first operational amplifier OA1. The third resistor R3 is connected between a non-inverting input (+) of the first operational amplifier OA1 and another end (KSNS pin) of the sense resistor R.sub.S. One end of the fourth resistor R4 receives a voltage V.sub.CMREF of a predetermined level while another end of the fourth resistor R4 is connected to the non-inverting input (+) of the first operational amplifier OA1. The feedback signal V.sub.FB corresponds to an output voltage of the first operational amplifier OA1.

[0092] When R1=R3 and R2=R4 hold, the following equation (9) holds.

V.sub.FB=R2/R1×V.sub.CS+V.sub.CMREF   (9)

[0093] The error amplifier 254 outputs the voltage command signal V.sub.EAOUT such that the feedback signal V.sub.FB approaches a target level based on the control signal V.sub.DAC.

[0094] The error amplifier 254 includes a first input node n1, a second input node n2, a second operational amplifier OA2, a fifth resistor R5, and a sixth resistor R6. The feedback signal V.sub.FB is input into the first input node n1. The control signal V.sub.DAC is input into the second input node n2. The non-inverting input (+) of the second operational amplifier OA2 receives the reference voltage V.sub.CMREF. A capacitor and resistor for phase compensation are connected between an inverting input (−, EIN pin) and an output (EOUT pin) of the second operational amplifier OA2.

[0095] The fifth resistor R5 is connected between an inverting input (−) of the second operational amplifier OA2 and the first input node n1. The sixth resistor R6 is connected between the inverting input (−) of the second operational amplifier OA2 and the second input node n2. The voltage command signal V.sub.EAOUT may correspond to the voltage at the output of the second operational amplifier OA2.

[0096] The inverting input (−) of the error amplifier 254 is as follows.

(R6.Math.V.sub.FB+R.sub.5.Math.V.sub.DAC)/(R5+R6)

[0097] Further, virtual grounding is made in a steady state. Therefore, the inverting input (−) of the error amplifier 254 becomes equal to the common voltage V.sub.CMREF of the non-inverting input (+) and the following equation (10) is obtained.

(R6.Math.V.sub.FB+R5.Math.V.sub.DAC)/(R5+R6)=V.sub.CMREF   (10)

[0098] Therefore, in the steady state, the following equation (11) holds.

V.sub.FB=−R5/R6.Math.V.sub.DAC+(R5/R6+1).Math.V.sub.CMREF   (11)

[0099] Substituting the equation (9) into the equation (11) obtains the following.

R2/R1×V.sub.CS+V.sub.CMREF=−R5/R6.Math.V.sub.DAC+(R5/R6+1).Math.V.sub.CMREF

[0100] Transforming this obtains the following equation (12).

V.sub.CS=−(R5/R6)(R1/R2).Math.V.sub.DAC+(R5/R6)−V.sub.CMREF=−(R5/R6)(R1/R2){V.sub.DAC−(R1/R2).sup.−1.Math.V.sub.CMREF}  (12)

[0101] Since V.sub.REF in the equation (4) gives a target value of V.sub.CS, they are equal to each other in the steady state and therefore, the equation (12) and the equation (4) are equal to each other. Contrasting the equation (12) with the equation (4) obtains the following.

g=−(R5/R6)(R1/R2)

V.sub.0=(R1 /R2).sup.−1V.sub.CMREF [0102] When R1=R2, the following equations are obtained.

g=−(R5/R6)

V.sub.0=V.sub.CMREF

[0103] In FIG. 5, the sixth resistor R6 includes a variable resistor. The gain “g” of the driver 240 can be controlled depending on a resistance value of the sixth resistor R6. In the first state φ.sub.1, the logic circuit 220 sets the resistance value of the sixth resistor R6 to a relatively high value R6_1. In the second state φ.sub.2, the logic circuit 220 sets the resistance value of the sixth resistor R6 to a relatively low value R6_2.

[0104] The resistance values R6_1 and R6_2 only need to be respectively determined to be as follows.

R6_1=R5/|g.sub.1|

R6_2=R5/|g.sub.2|

[0105] The output stage 260 includes a first amplifier 262 and a second amplifier 264. The first amplifier 262 amplifies the voltage command signal V.sub.EAOUT without inversion. The second amplifier 264 inverts and amplifies the voltage command signal V.sub.EAOUT.

[0106] The first amplifier 262 includes a third operational amplifier OA3 and a seventh resistor R7 to a tenth resistor R10. A configuration of the first amplifier 262 is similar to that of the current sense amplifier 252. When R7=R9 and R8=R10 hold, an output voltage V.sub.AOUT of the first amplifier 262 can be expressed by the following equation (13).

V.sub.AOUT=R8/R7×(V.sub.EAOUT−V.sub.CMREF)+HVPWR   (13)

[0107] The second amplifier 264 includes a fourth operational amplifier OA4 and an eleventh resistor R11 to a fourteenth resistor R14. A configuration of the second amplifier 264 is similar to those of the current sense amplifier 252 and the first amplifier 262. When R11=R13 and R12=R14 hold, an output voltage V.sub.BOUT of the second amplifier 264 is expressed by the following equation (14).

V.sub.BOUT=−R12/R11×(V.sub.EAOUT−V.sub.CMREF)+HVPWR   (14)

[0108] Note that R8/R7=R12/R11 is satisfied.

[0109] The configuration of the motor driver circuit 200 is as described above. The motor driver circuit 200 can suppress noise by reducing the gain “g” of the driver 240 in the first state φ.sub.1 while extending the control range of the drive current I.sub.DRV by increasing the gain “g” of the driver 240 in the second state φ.sub.2.

Second Embodiment

[0110] FIG. 6 is a block diagram of a positioning device 100A, which includes a motor driver circuit 200A according to a second embodiment. The following focuses on the differences between the first embodiment and the second embodiment.

[0111] The motor driver circuit 200A includes a sample and hold circuit 270 in addition to the motor driver circuit 200 of FIG. 1.

[0112] The sample and hold circuit 270 is connected between the D/A converter 230 and the driver 240. In a tracking state (through state), the sample and hold circuit 270 outputs the control signal V.sub.DAC as it is and samples the control signal V.sub.DAC through a sampling operation. In a hold state, the sample and hold circuit 270 outputs the sampled control signal V.sub.DAC_SH. When the output of the sample and hold circuit 270 is described as V.sub.SH, V.sub.SH=V.sub.DAC holds in the tracking state and during the sampling operation and V.sub.SH=V.sub.DAC_SH holds in the hold state.

[0113] The logic circuit 220 switches from the first state φ.sub.1 to the second state φ.sub.2 when the first code x exceeds a predetermined value x.sub.TH. x.sub.TH corresponds to x.sub.a and x.sub.b.

[0114] In the first state φ.sub.1 and the second state φ.sub.2, the sample and hold circuit 270 enters the tracking state in which V.sub.SH=V.sub.DAC. That is, the motor driver circuit 200A in the first state φ.sub.1 and the second state φ.sub.2 is equivalent to the motor driver circuit 200 of FIG. 1.

[0115] The configuration of the motor driver circuit 200A is as described above.

[0116] In order to clarify the advantages of the motor driver circuit 200A, an issue that may arise in the motor driver circuit 200 of FIG. 1 is described below.

[0117] In the motor driver circuit 200 of FIG. 1, the D/A converter 230 includes the converter 232 and the buffer 234. If the response speed of the buffer 234 is slow when the second code y generated by the logic circuit 220 changes discontinuously at the time of switching between the first state φ.sub.1 and the second state φ.sub.2, there is a possibility that overshooting, undershooting, or ringing occurs in the control signal V.sub.DAC, which is the output of the buffer 234. Overshooting, undershooting, or ringing of the control signal V.sub.DAC appears as a glitch in the drive current I.sub.DRV.

[0118] Based on the issue described above, an operation of the motor driver circuit 200A is described below.

[0119] FIG. 7 is a time chart for describing the operation of the motor driver circuit 200A of FIG. 6. When the first code x becomes the predetermined value x.sub.TH, the logic circuit 220 generates a trigger for transition from the first state φ.sub.1 to the second state φ.sub.2.

[0120] Before time to, the motor driver circuit 200A is in an initial state. The motor driver circuit 200A operates in the first state φ1. In other words, the gain of the driver 240 is g.sub.1, and the slope of the logic circuit 220 is a.sub.1. The second code y takes y=a.sub.1.Math.x.sub.TH. Note that b=0. At the time of transition from the first state φ.sub.1 to the second state φ.sub.2, the logic circuit 220 gradually changes the second code y from a.sub.1.Math.x.sub.TH to a.sub.2.Math.x.sub.TH (time t.sub.1 to t.sub.2).

[0121] The sample and hold circuit 270 samples the control signal V.sub.DAC corresponding to y=a.sub.1.Math.x.sub.TH prior to this gradual change period t.sub.1 to t.sub.2, and holds the sampled control signal V.sub.DAC during the gradual change period t.sub.1 to t.sub.2.

[0122] At time t.sub.2 when the gradual change period ends, the sample and hold circuit 270 is switched from the hold state to the tracking state, and at the same time, the gain of the driver 240 is switched from g.sub.1 to g.sub.2.

[0123] The transition from the first state φ.sub.1 to the second state φ.sub.2 is as described above. The transition from the second state φ.sub.2 to the first state φ.sub.1 is described next.

[0124] During the period from time t.sub.2 to time t.sub.3, the motor driver circuit 200A continues to operate in the second state φ.sub.2. During this period, the first code x takes a value corresponding to the position control data POS, and the drive current I.sub.DRV also changes.

[0125] At time t.sub.3, when the first code x becomes the predetermined value X.sub.TH, the logic circuit 220 generates a trigger for transition from the second state φ.sub.2 to the first state φ.sub.1.

[0126] During the transition from the second state φ.sub.2 to the first state φ.sub.1, the logic circuit 220 gradually changes the second code y from a.sub.2.Math.x.sub.TH to a.sub.1.Math.x.sub.TH (time t.sub.4 to time t.sub.5).

[0127] The sample and hold circuit 270 samples the control signal V.sub.DAC corresponding to y=a.sub.2.Math.x.sub.TH prior to this gradual change period time t.sub.4 to t.sub.5, and holds the sampled control signal V.sub.DAC during the gradual change period time t.sub.4 to t.sub.5.

[0128] At time t.sub.5 when the gradual change period ends, the sample and hold circuit 270 is switched from the hold state to the tracking state, and at the same time, the gain of the driver 240 is switched from g.sub.2 to g.sub.1.

[0129] The transition from the second state φ.sub.2 to the first state φ.sub.1 is as described above.

[0130] The motor driver circuit 200A can suppress a glitch in the drive current I.sub.DRV at the time of switching from the first state φ.sub.1 to the second state φ.sub.2 and from the second state φ.sub.2 to the first state φ.sub.1.

[0131] FIG. 8 is a circuit diagram illustrating an example of a specific configuration of the motor driver circuit 200A. The configuration of the motor driver circuit 200A other than the sample and hold circuit 270 is similar to that of the motor driver circuit 200 illustrated in FIG. 5.

[0132] The sample and hold circuit 270 includes a capacitor C1, a buffer 272, and a first switch SW1 to a third switch SW3. An input node IN of the sample and hold circuit 270 is connected to an output of the D/A converter 230, while an output node OUT of the sample and hold circuit 270 is connected to the driver 240. The first switch SW1 is connected between the input node IN and the output node OUT. One end of the capacitor C1 is grounded. The second switch SW2 is connected between the other end of the capacitor C1 and the input node IN. The buffer 272 receives a voltage at the other end of the capacitor C1. The third switch SW3 is connected between an output of the buffer 272 and the output node OUT.

[0133] The sample and hold circuit 270 is switchable between the following three states. [0134] Tracking state [0135] First switch SW1: ON [0136] Second switch SW2: ON [0137] Third switch SW3: OFF [0138] Hold state [0139] First switch SW1: OFF [0140] Second switch SW2: OFF [0141] Third switch SW3: ON [0142] Through state [0143] First switch SW1: ON [0144] Second switch SW2: OFF [0145] Third switch SW3: OFF

[0146] The logic circuit 220 switches ON and OFF of the first switch SW1 to the third switch SW3, thereby controlling the state of the sample and hold circuit 270.

[0147] Next, an operation of the motor driver circuit 200A of FIG. 8 is described.

[0148] FIG. 9 is a diagram for describing the operation of the motor driver circuit 200A of FIG. 8. In FIG. 9, the control signal V.sub.DAC, an output voltage V.sub.BUF of the buffer 272, an output voltage V.sub.SH of the sample and hold circuit 270, the drive current I.sub.DRV, the gain “g” of the driver 240, and the state of the sample and hold circuit 270 are illustrated.

[0149] Before time t.sub.0, the motor driver circuit 200A is in the first state φ.sub.1. As in the situation of FIG. 7, when x=X.sub.TH, a trigger for transition from the first state φ.sub.1 to the second state φ.sub.2 is generated at time t.sub.0. The time t.sub.0 to t.sub.2 is a transition period.

[0150] At time t0, the sample and hold circuit 270 transitions from the tracking state to the through state. Accordingly, the sample and hold circuit 270 samples the control signal V.sub.DAC. After that, the sample and hold circuit 270 transitions to the hold state and outputs the sampled control signal V.sub.DAC.

[0151] After completion of the sampling operation of the sample and hold circuit 270 at time t.sub.1, the logic circuit 220 gradually changes the second code y. Due to the gradual change of the second code y, the control signal V.sub.DAC changes with time. At this time, since the sample and hold circuit 270 is in the hold state, the signal V.sub.SH input into the driver 240 is constant.

[0152] At time t.sub.2 after the completion of the gradual change of the second code y, the gain of the driver 240 changes from g.sub.1 to g.sub.2, and at the same time, the sample and hold circuit 270 transitions to the through state. Accordingly, the transition to the second state φ.sub.2 is complete. After that, at time t.sub.3, the sample and hold circuit 270 transitions to the tracking state and prepares for the next sampling operation.

[0153] The operation of the motor driver circuit 200A is as described above.

Application

[0154] FIG. 10 is a view of a hard disk device 900, which includes the motor driver circuit 200. The hard disk device 900 includes a platter 902, a swing arm 904, a head 906, a spindle motor 910, a seek motor 912, and a motor driver circuit 920. The motor driver circuit 920 drives the spindle motor 910 and the seek motor 912.

[0155] The seek motor 912 is a voice coil motor. The motor driver circuit 200 (or 200A) according to the embodiment of the present disclosure is built into the motor driver circuit 920 and drives the seek motor 912.

[0156] The seek motor 912 positions the head 906 through the swing arm 904. Low noise is required during hard disk read and write periods, that is, when the head 906 is positioned in a particular region. Therefore, x.sub.a and x.sub.b are defined such that (i) the motor driver circuit 200 (or 200A) enters the first state φ.sub.1 when the seek motor 912 is at a position where the head 906 is positioned in a valid region on the platter 902 and (ii) the motor driver circuit 200 (or 200A) enters the second state φ.sub.2 when the seek motor 912 is at a position where the head 906 is positioned in a region other than the valid region on the platter 902. With this configuration, it is possible to automatically suppress noise during read and write.

[0157] The embodiments are described above. The embodiments described above are for exemplary purposes only, and it is to be understood by those skilled in the art that various modifications can be made to combinations of the constituent components and processes of the embodiments and that such modifications also fall within the scope of the present disclosure. The following describes such modifications.

First Modification

[0158] The first state φ.sub.1 and the second state φ.sub.2 may be manually switchable from outside according to a command from the host controller 104.

Second Modification

[0159] When the position control data POS is changed by the host controller 104, the logic circuit 220 may instantaneously switch the value of the first code x without changing it gradually.

Third Modification

[0160] In association with the second embodiment, the configuration and operation of the sample and hold circuit 270 are not limited to those described above, and another form of a sample and hold circuit or a track hold circuit may also be used.

Fourth Modification

[0161] In the second embodiment, the logic circuit 220 gradually changes the second code y. However, the present disclosure is not limited thereto. For example, the logic circuit 220 may change the second code y stepwise or switch a.sub.1.Math.x.sub.TH and a.sub.2.Math.x.sub.TH instantaneously.

Fifth Modification

[0162] The configuration of the driver 240 is not limited to any of those illustrated in FIGS. 5 and 8. For example, the error amplifier 254 may have a positive gain. For example, the output stage 260 may be of a single-ended type, instead of a differential type.

Sixth Modification

[0163] The configuration and type of the linear motor to be driven are also not limited to any configuration and type. For example, the present disclosure can also be applied to the drive of spring-return type voice coil motors or other linear actuators.

Seventh Modification

[0164] The application of the positioning device 100 is also not limited to a hard disk device. For example, the positioning device 100 can also be applied to a positioning mechanism for a camera lens.