Abstract
IGBT includes an n-type drift layer, an n-type accumulation layer provided on the upper surface of the drift layer having higher impurity concentration than the drift layer, a base layer provided on the upper surface of the accumulation layer, a gate electrode embedded inside a striped gate trench penetrating the base layer and the storage layer through a gate insulating film, and a dummy electrode embedded inside a dummy trench provided to face the gate trench across the base layer and the accumulation layer through a dummy insulating film. The base layer has a p-type active base region and a p-type floating base region arranged alternately in the extending direction of the gate trench, and an n-type base isolation region isolating the active base region and the floating base region.
Claims
1. An insulated gate bipolar transistor comprising: a drift layer of a first conductivity type; an accumulation layer of the first conductivity type arranged on an upper surface of the drift layer, having an impurity concentration higher than an impurity concentration of the drift layer; a base layer arranged on an upper surface of the accumulation layer; a gate electrode embedded through a gate insulating film inside a stripe-shaped gate trench penetrating the base layer and the accumulation layer; a dummy electrode embedded through a dummy insulating film inside a stripe-shaped dummy trench penetrating the base layer and the accumulation layer; and an emitter region of the first conductivity type arranged in an upper portion of the base layer, having a higher impurity concentration than the drift region, wherein the base layer includes an active base region of a second conductivity type in which the emitter region is arranged in the upper portion, connected to emitter potential, a floating base region of the second conductivity type set at floating potential, and a base isolation region of the first conductivity type isolating the active base region and the floating base region, and in a mesa provided between the gate trench and the dummy trench, the active base region and the floating base region are alternately arranged via the base isolation region in an extending direction of the gate trench.
2. The insulated gate bipolar transistor according to claim 1, wherein the active base region faces the floating base region across the dummy trench.
3. The insulated gate bipolar transistor according to claim 1, wherein the active base region faces the other active base region across the gate trench.
4. The insulated gate bipolar transistor according to claim 1, wherein the active base region faces the floating base region across the gate trench.
5. The insulated gate bipolar transistor according to claim 1, wherein an impurity concentration of the base isolation region is higher than or equal to the impurity concentration of the drift layer and less than or equal to the impurity concentration of the accumulation layer.
6. The insulated gate bipolar transistor according to claim 5, wherein the impurity concentration of the base isolation region is more than or equal to 110.sup.16 cm.sup.3 and less than or equal to 110.sup.17 cm.sup.3.
7. The insulated gate bipolar transistor according to claim 1, wherein, the base layer further includes an extraction base region of the second conductivity type in which the emitter region is not arranged, connected to the emitter potential, and in a mesa provided between the dummy trenches adjacent to each other, the extraction base region and the floating base region are alternately arranged via the base isolation region in an extending direction of the dummy trench.
8. The insulated gate bipolar transistor according to claim 1, wherein the emitter region and a low-resistance base contact region of the second conductivity type having a higher impurity concentration than the active base region are selectively arranged on an upper portion of the active base region in contact with each other.
9. The insulated gate bipolar transistor according to claim 8, wherein both the emitter region and the low-resistance base contact region are in contact with the dummy trench and the gate trench.
10. The insulated-gate bipolar transistor according to claim 8, wherein, in plan view, only one side of the emitter region contacts the gate trench, and the low-resistance base contact region contacts the dummy trench and the gate trench to cover other sides of the emitter region.
11. The insulated gate bipolar transistor according to claim 8, wherein in the extending direction of the gate trench, the low-resistance base contact region is arranged closer to the base isolation region than the emitter region.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) FIG. 1 is a schematic plan view illustrating an example of a layout of a base region of an IGBT according to an embodiment;
(2) FIG. 2 is a schematic cross-sectional view taken along line A-A in FIG. 1;
(3) FIG. 3 is a schematic cross-sectional view taken along line B-B in FIG. 1;
(4) FIG. 4 is a schematic perspective view illustrating a hole extraction path of the IGBT according to the embodiment;
(5) FIG. 5 is a schematic cross-sectional view illustrating an example of an IGBT of a comparative example 1;
(6) FIG. 6 is a schematic cross-sectional view illustrating an example of an IGBT of comparative example 2;
(7) FIG. 7 is a circuit diagram illustrating an example of a measurement circuit for switching characteristics of the IGBT;
(8) FIG. 8 is a graph illustrating an example of relationship between a rate of voltage change and a gate resistance of the IGBT according to the embodiment;
(9) FIG. 9 is a graph illustrating an example of relationship between a switching loss and the gate resistance of the IGBT according to the embodiment;
(10) FIG. 10 is a graph illustrating another example of relationship between the rate of voltage change and the gate resistance of the IGBT according to an embodiment;
(11) FIG. 11 is a graph illustrating another example of relationship between the switching loss and the gate resistance of the IGBT according to the embodiment;
(12) FIG. 12 is a graph illustrating an example of a turn-on waveform of the IGBT according to an embodiment;
(13) FIG. 13 is a graph illustrating another example of the turn-on waveform of the IGBT according to an embodiment;
(14) FIG. 14 is a table illustrating an example of evaluation results of the IGBT according to the embodiment;
(15) FIG. 15 is a schematic plan view illustrating another example of the layout of the source regions of the IGBT according to the embodiment;
(16) FIG. 16 is a schematic plan view illustrating another example of the layout of the base region of the IGBT according to the embodiment;
(17) FIG. 17 is a schematic cross-sectional view taken along line C-C in FIG. 16; and
(18) FIG. 18 is a schematic plan view illustrating another example of the layout of the base region of the IGBT according to the embodiment.
DETAILED DESCRIPTION
(19) Exemplary embodiments of the present invention will be described below with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, the relationship between the thickness and the planar dimension, the ratio of the thickness of each device and each member, etc. may be different from the actual one. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. In addition, it should also be understood that the respective drawings are illustrated with the dimensional relationships and proportions different from each other.
(20) In the following descriptions, the terms relating to directions, such as left and right and top and bottom are merely defined for illustration purposes, and thus, such definitions do not limit the technical spirit of the present invention. Therefore, for example, when the paper plane is rotated by 90 degrees, the left and right and the top and bottom are read in exchange. When the paper plane is rotated by 180 degrees, the top is changed to the bottom, and the bottom is changed to the top. In the following description, the case where the first conductivity type is n type and the second conductivity type is p type will be described as an example. However, the conductivity type may be selected in an inverse relationship so that the first conductivity type may be p type and the second conductivity type may be n type. In addition, + or attached to n or p means that the semiconductor region is relatively high or low in impurity density as compared with the semiconductor region to which + and are not added. However, even semiconductor regions with the same n and n do not mean that the impurity densities of the respective semiconductor regions are strictly the same.
(21) FIG. 1 is a schematic plan view illustrating a layout of a base layer (5a, 5b), a base isolation region 5c and a trench (9a, 9b) of the IGBT according to the first embodiment of the present invention. As illustrated in FIG. 1, the trench (9a, 9b) is composed of a stripe-shaped gate trench 9a and a stripe-shaped dummy trench 9b disposed in parallel with the gate trench 9a, in plan view. The gate trench 9a and the dummy trench 9b are alternately disposed side by side, and the base layer (5a, 5b) and the base isolation region (5c) are disposed between the gate trench 9a and the dummy trench 9b. In the base layer (5a, 5b) and the base isolation region (5c), in plan view, an active base region and a floating base region 5b are alternately disposed in an extending direction of the trench (9a, 9b), and the active base region 5a and the floating base region 5b are isolated by the base isolation region 5c. That is, in a mesa provided between the gate trench 9a and the dummy trench 9b adjacent to the gate trench 9a, the active base region 5a and the floating base region 5b are alternately disposed via the base isolation region 5c. In a direction perpendicular to the extending direction of the trench (9a, 9b), the active base region 5a faces the adjacent active base region 5a across the gate trench 9a and the floating base region 5b across the dummy trench 9b. In addition, the active base region 5a may be arranged to face the floating base region across the dummy trench 9b and to face the floating base region 5b across the gate trench 9a. The location of the active base region 5a projected in the direction perpendicular to the extending direction of the trench (9a, 9b) is included within the floating base region 5b.
(22) As illustrated in FIG. 1, an emitter region 6 and a low-resistance base contact region 7 are selectively arranged in an upper portion of the active base region 5a. Both the emitter region 6 and the low-resistance base contact region 7 are arranged in contact with opposing sides of the gate trench 9a and the dummy trench 9b, respectively. The base isolation region 5c is arranged to face the low-resistance base contact region 7 through the active base region 5a in the extending direction of the trench (9a, 9b). In other words, in the extending direction of the trench (9a, 9b), the low-resistance base contact region 7 is provided to cover both sides of the emitter region 6 and to be closer to the base isolation region 5c than the emitter region 6. In FIG. 1, two emitter regions 6 sandwiched between the low-resistance base connection regions 7 are placed in the extending direction of the trench (9a, 9b). The number of emitter regions 6 is not limited, and may be three or more, or a single. In addition, neither the emitter region 6 nor the low-resistance base contact region 7 is placed in the floating base region 5b. A contact region is formed to partially contact the emitter region 6 and enclose the low-resistance base contact region 7, in which an ohmic junction is formed between an emitter electrode 13 and a semiconductor surface.
(23) FIG. 2 is a cross-sectional view cut in the direction perpendicular to the extending direction of the trench (9a, 9b), and FIG. 3 is a cross-sectional view cut in the extending direction of the trench (9a, 9b). As illustrated in FIGS. 2 and 3, a first conductivity type (n-type) accumulation layer 4 having a higher impurity concentration than an n.sup.-type drift layer 3 is located on an upper surface of the drift layer 3, and the base layer (5a, 5b) and the base isolation region 5c are located on an upper surface of the accumulation layer 4. The base layer (5a, 5b) has a second conductivity type (p-type) active base region 5a and the p-type floating base region 5b. The base isolation region 5c is of the first conductivity type (n-type). The n-type base isolation region 5c has an impurity concentration higher than or equal to the impurity concentration of the drift layer 3 and less than or equal to the impurity concentration of the accumulation layer 4. For example, the drift layer 3 has the impurity concentration of about 310.sup.13 cm.sup.3 and the accumulation layer 4 has the impurity concentration in a range of 510.sup.15 cm.sup.3 or more and 110.sup.17 cm.sup.3 or less, preferably in a range of 110.sup.16 cm.sup.3 or more and 110.sup.17 cm.sup.3 or less. In the upper portion of the active base region 5a, the n.sup.+-type emitter region 6 having a higher impurity concentration than the drift layer 3 and the p.sup.+-type low-resistance base contact region 7 having a higher impurity concentration than the active base region 5a are arranged. As illustrated in FIG. 1, the emitter region 6 and the low-resistance base contact region 7 are alternately disposed in the extending direction in which the trench (9a, 9b) extends in parallel. The emitter region 6 and the low-resistance base contact region 7 are connected to emitter potential. More specifically, the active base region 5a is connected to the emitter potential via the low-resistance base contact region 7. In addition, the floating base region is set at floating potential.
(24) The trench (9a, 9b) is provided from upper surfaces of the base layer (5a, 5b) and the base isolation region (5c) penetrating the accumulation layer 4. The base layer (5a, the base isolation region (5c) and the accumulation layer 4 are in contact with each side of the trench (9a, 9b), and a part of the drift layer 3 is also in contact with each side of the trench (9a, 9b). As illustrated in FIG. 2, a gate insulating film 10a is formed on a bottom and the sides of the gate trench 9a. A gate electrode 11a connected to the gate potential is embedded inside the gate trench 9a via the gate insulating film 10a. A dummy insulating film 10b is formed on a bottom and the sides of the dummy trench 9b. A dummy electrode 11b connected to the emitter potential is embedded inside the dummy trench 9b via the dummy insulating film 10b.
(25) For the gate insulating film 10a and the dummy insulating film 10b, in addition to a silicon dioxide (SiO.sub.2) film, a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si.sub.3N.sub.4) film, an aluminum oxide (Al.sub.2O.sub.3) film, a magnesium oxide (MgO) film, a yttrium oxide (Y.sub.2O.sub.3) film, a hafnium oxide (HfO.sub.2) film, a zirconium oxide (ZrO.sub.2) film, a tantalum oxide (Ta.sub.2O.sub.5) film, a bismuth oxide (Bi.sub.2O.sub.3) film and the like, may be adopted. Moreover, a single-layer film of any one of the above-mentioned dielectric films or a composite film in which the plural dielectric films are laminated, may be adopted. For each material of the gate electrode 11a and the dummy electrode 11b, for example, a polysilicon layer, or a doped polysilicon layer doped with impurities such as phosphorus (P) and boron (B) at a high concentration, can be used.
(26) As illustrated in FIGS. 2 and 3, an interlayer insulating film 12 is arranged on each of the gate electrode 11a and the dummy electrode 11b. The interlayer insulating film 12 extends to cover the floating base region 5b and the base isolation region 5c. The emitter electrode 13 is placed to cover the interlayer insulation film 12. The emitter electrode 13 is physically in contact with the emitter region 6 and the low-resistance base contact region 7 through contact holes formed in the interlayer insulating film 12, as illustrated in FIGS. 2 and 3. For the interlayer insulating film 12, a silicon oxide film to which boron (B) and phosphorus (P) are added, that is BPSG, is used. The interlayer insulating film 12 may be a silicon oxide film with phosphorus (P) added, that is PSG, a non-doped silicon oxide (SiO.sub.2) film called NSG, in which phosphorus (P) or boron (B) is not contained, a silicon oxide film with boron (B) added, that is BSG, a Si.sub.3N.sub.4 film or the like. In addition, a laminated film of the above-mentioned dielectric films, may be used. The emitter electrode 13 may be composed of, for example, a nickel silicide (NiSi.sub.x) film, a titanium nitride (TiN) film or a titanium (Ti) film, an aluminum (Al) film or an aluminum-silicon (AlSi) film, and the like.
(27) An n-type field stop layer (FS layer) 2 is located on a lower surface of the drift layer 3, and a p.sup.+-type collector region 1 is located on a lower surface of the FS layer 2. A collector electrode 14 is formed on a lower surface of the collector region 1. For the collector electrode 14, for example, a single-layer metallic film made of gold (Au) or a metallic film laminated in the order of Ti, nickel (Ni) and Au may be used. The IGBT according to the embodiment can be realized using a silicon (Si) semiconductor substrate as a basis and a conventional semiconductor device manufacturing process.
(28) During operation of the IGBT according to the embodiment, for example, a positive voltage is applied to the collector electrode 14 with the emitter electrode 13 as the ground potential. When the positive voltage above a threshold, such as +15 V, is applied to the gate electrode 11a, an inversion layer (channel) is created on the surface of the active base region 5a, which serves as an interface between the gate insulating film 10a in the gate trench 9a and the active base region 5a. A bipolar transistor implemented by the p-type active base region 5a, n-type layers of the accumulation region 4, the drift layer 3, and the FS layer 2, and the p-type collector region 1 operates using electrons supplied to the drift layer 3 via the inversion layer as a base current. When the IGBT is thus turned on, a current flows in the on-state from the collector electrode 14 to the emitter electrode 13 via the collector region 1, the FS layer 2, the drift layer 3, the accumulation layer 4, the inversion layer of the active base region 5a and the emitter region 6. When the voltage applied to the gate electrode 11a is below the threshold, no current flows from the collector electrode 14 to the emitter electrode 13 because no inversion layer is created in the active base region 5a.
(29) In the IGBT according to the embodiment, the floating base region 5b is set at the floating potential, and no inversion layer is created in the floating base region 5b in contact with the gate trench 9a even in the on-state. In addition, since the dummy electrode 11b in the dummy trench 9b is electrically connected to the emitter potential, no inversion layer is created on the surface of the active base region 5a in contact with the side of the dummy trench 9b. Therefore, a channel density of the IGBT can be reduced and hole extraction can be suppressed. Furthermore, since the n-type accumulation layer 4 is arranged under the p-type active base region 5a, the accumulation of holes in the drift layer 3 is promoted. As a result, the on-voltage can be decreased.
(30) In the on-state of the IGBT according to the embodiment, as illustrated in FIG. 4, an extraction path Hp.sub.on is formed in the base isolation region 5c in contact with the side of the dummy trench 9b and in the drift layer 3 in contact with the bottom of the dummy trench 9b, respectively. Holes accumulated in the floating base region 5b are extracted through the extraction path Hp.sub.on to the low-resistance base contact region 7 in the active base region 5a. When a negative voltage below the threshold, such as 15 V, is applied to the gate electrode 11a to turn to off-state, an inversion layer that is a p-type channel is created on the surface of the base isolation region 5c in contact with the side of the gate trench 9a. Therefore, as illustrated in FIG. 4, an extraction path Hp.sub.off is formed in the base isolation region 5c along the side of the gate trench 9a. As a result, the excess holes accumulated in the floating base region 5b can be extracted via the extraction path Hp.sub.off during turn-on, and via the extraction path Hp.sub.off during turn-off. Thus, in the IGBT according to the embodiment, the potential change in the floating base region 5b can be suppressed to be moderated during the switching process, making it possible to easily control the voltage change dV/dt and preventing an increase in switching loss.
(31) In the IGBT according to the embodiment, values of a capacitance C.sub.GC between gate and collector and a capacitance C.sub.GE between gate and emitter can be easily adjusted by adjusting a spacing between the active base region 5a and the floating base region 5b sandwiching the base isolation region 5c. The voltage change dV/dt is also easily controlled and a wide range of usages may be applicable. Furthermore, the IGBT according to the embodiment can achieve the low switching loss in a wide range of fixed driving conditions such as gate resistance in hard switching. Therefore, it can be used in a wide range of applications, for example, when the current capacity of the gate drive circuit is limited on the premise of satisfying noise specification or when only the IGBT of the power element is updated.
(32) As an example, in the structure of the IGBT according to the embodiment, the turn-on characteristics have been evaluated with the impurity concentration of the accumulation layer 4 as 910.sup.15 cm.sup.3 and 910.sup.16 cm.sup.3, respectively. As a comparative example 1 and a comparative example 2, IGBTs with the structures illustrated in FIGS. 5 and 6 have been fabricated to evaluate the turn-on characteristics. As illustrated in FIGS. 5 and 6, in the comparative examples 1 and 2, a base layer (5a, 5b, 55) is formed on the upper surface of the accumulation layer 4. The p-type active base region 5a, the p-type floating base region 5b and a p-type intermediate region 55 in the base layer (5a, 5b, 55) are defined by the stripe-shaped trenches (9a, 9b) and formed into stripes, respectively. The active base region 5a is formed between the gate trenches 9a, and the emitter region 6 is formed separately in contact with each sidewall of the opposing gate trenches 9a. The floating base region 5b is formed between the gate trench 9a and the dummy trench 9b. The intermediate region 55 is formed between the dummy trenches 9b. In the comparative example 1, as illustrated in FIG. 5, each of the emitter region 6, the active base region 5a, and the intermediate region 55 is physically connected to the emitter electrode 13 through an opening formed in the interlayer insulating film 12, and the floating base region 5b is at floating potential. On the other hand, as illustrated in FIG. 6, in the comparative example 2, in addition to the emitter region 6, the active base region 5a and the intermediate region 55, the floating base region 5b is also physically connected to the emitter electrode 13 through an opening formed in the interlayer insulating film 12 and connected to the emitter potential.
(33) FIG. 7 illustrates a measurement circuit for evaluating the turn-on characteristics of the IGBT. As illustrated in FIG. 7, a freewheeling diode Di is connected in antiparallel to a transistor Tr to-be-measured. A pulse signal is applied from a gate drive circuit to a gate electrode of the transistor Tr to-be-measured via a gate resistance Rg. Each of the transistors Tr to-be-measured in the example, the comparative example 1 and the comparative example 2 used for the measurement, has been fabricated in the same way for all respective elements, such as an area of the active base region 5a, an area of the floating base region 5b and the base isolation region 5c or the intermediate region 55 in a minimum layout unit, except for the layout of the surface area, and each maximum rating is also the same.
(34) FIGS. 8 and 9 illustrate relationships between the voltage changes dV/dt.sub.on and the switching losses (E.sub.on+E.sub.rr) of the transistors Tr to-be-measured and the gate resistances Rg.sub.on in the example, the comparative example 1 and the comparative example 2 for the case where an impurity concentration n.sub.SC in the accumulation layer 4 is 910.sup.15 cm.sup.3. The switching loss (E.sub.on+E.sub.rr) is expressed as a sum of a turn-on loss E.sub.on of the transistor Tr to-be-measured and a reverse-recovery loss E.sub.rr of the freewheeling diode Di. As illustrated in FIG. 8, when driving with the voltage change dV/dt.sub.on controlled to 5 kV/s or less, the gate resistance Rg.sub.on needs to be in a range of about 16 or more in the example and the comparative example 2, and about 8 or more in the comparative example 1. As illustrated in FIG. 9, the switching loss (E.sub.on+E.sub.rr) is smaller in the example than in the comparative example 1 and the comparative example 2, in a range of the gate resistance Rg.sub.on of about 16 or more. In the comparative example 1 and the comparative example 2, the switching loss (E.sub.on+E.sub.rr) is smaller than that in the example when the gate resistance Rg.sub.on is in a range of about 8 to about 12.
(35) FIGS. 10 and 11 illustrate relationships between the voltage changes dV/dt.sub.on and the switching losses (E.sub.on+E.sub.rr) of the transistors Tr to-be-measured and the gate resistances Rg.sub.on in the example, the comparative example 1 and the comparative example 2 for the case where the impurity concentration n.sub.SC in the accumulation layer 4 is 910.sup.16 cm.sup.3. As illustrated in FIG. 10, when driving with the voltage change dV/dt.sub.on controlled to 5 kV/s or less, the gate resistance Rg.sub.on needs to be in the range of about 16 or more in the example, and about 10 or more in the comparative examples 1 and 2. As illustrated in FIG. 11, the switching loss (E.sub.on+E.sub.rr) is smaller in the example than in the comparative examples 1 and 2 in a range of the gate resistance Rg.sub.on of about 16 or more. In the comparative examples 1 and 2, the voltage change dV/dt.sub.on is larger than kV/s in a range of gate resistance Rg.sub.on of about 8 to 10, but the switching loss (E.sub.on+E.sub.rr) is smaller than that in the example. As illustrated in FIGS. 8 to 11, in the comparative examples 1 and 2, the range of gate resistance Rg.sub.on where the switching loss (E.sub.on+E.sub.rr) can be reduced compared with the example, decreases as the impurity concentration in the accumulation layer 4 increases. Thus, in the structure of the IGBT according to the embodiment, it is possible to reduce the switching loss (E.sub.on+E.sub.rr) in a wide range of the fixed gate resistor Rg.sub.on.
(36) FIG. 12 illustrates turn-on waveforms of the example and the comparative example 1 when the gate resistances Rg.sub.on are 16 ohms, where the impurity concentration n.sub.SC of the accumulation layer 4 is 910.sup.16 cm.sup.3. As illustrated in FIG. 12, the waveform of the gate voltage V.sub.GE in the comparative example 1 shows a hump at the rise of the charging period of the gate-emitter capacitance. This hump is due to the potential of the floating base region 5b illustrated in FIG. 5. On the other hand, in the waveform of the gate voltage V.sub.GE in the example, the hump is suppressed and the turn-on voltage change dV/dt.sub.on is faster, reducing switching loss (E.sub.on+E.sub.rr). The switching loss (E.sub.on+E.sub.rr) has been 20.8 mJ in the example and 27.1 mJ in the comparative example 1.
(37) FIG. 13 illustrates the turn-on waveforms of the example and the comparative example 1 when the voltage changes dV/dt.sub.on are 5 kV/s where the impurity concentration n.sub.SC of the accumulation layer 4 is 910.sup.16 cm.sup.3. The switching losses (E.sub.on+E.sub.rr) have been similar, but the gate voltage change dV.sub.GE/dt in the example has been lower. Thus, compared to the comparative example 1, the gate drive circuit in the example has a lower requirement for peak gate current.
(38) FIG. 14 illustrates evaluation results of the example, the comparative example 1, and the comparative example 2 when the impurity concentration in the accumulation is 910.sup.16 cm.sup.3 and 910.sup.15 cm.sup.3. As illustrated in the table of FIG. 14, when the impurity concentration in the accumulation layer 4 is as low as 910.sup.15 cm.sup.3, the on-voltages V.sub.on are 1.715 V for the example, and 1.695 V and 1.836 V for the comparative examples 1 and 2, respectively. The switching losses (E.sub.on+E.sub.rr) at the same voltage change dV/dt.sub.on of 5 kV/has are 24.99 mJ/pulse in the example, and 20.27 mJ/pulse and 26.95 mJ/pulse in the comparative examples 1 and 2, respectively. Both the on-voltage and the voltage change in the example are intermediate values between the comparative examples 1 and 2. When the impurity concentration in the accumulation layer 4 is 910.sup.16 cm.sup.3, the on-voltage V.sub.on is 1.56 V in the example, and 1.513 V and 1.604 V in the comparative examples 1 and 2, respectively, and thus, the on-voltage in the example is an intermediate value between the comparative examples 1 and 2. On the other hand, the switching losses (E.sub.on+E.sub.rr) at the same voltage change dV/dt.sub.on of 5 kV/s, are 20.8 mJ/pulse in the example and 20.1 mJ/pulse in both the comparative examples 1 and 2, and thus, the example is equivalent to the comparative examples 1 and 2. However, as illustrated in FIGS. 9, 11 and 12, the switching loss (E.sub.on+E.sub.rr) for the same gate resistance Rg.sub.on is smaller in the example than in the comparative examples 1 and 2. In the IGBT according to the embodiment, the switching loss can be reduced while suppressing the on-voltage.
(39) As described above, both the emitter region 6 and the low-resistance base contact region 7 located in the upper portion of the active base region 5a are in contact with the opposing sides of the gate trench 9a and the dummy trench 9b, respectively. However, the layout of the emitter region 6 and the low-resistance base contact region 7 is not limited. For example, as illustrated in FIG. 15, in plan view, the emitter region 6 may be divided into two sections, each of which may be arranged so that only one side contacts the sidewall of the gate trench 9a and the other side is covered by the low-resistance base contact region 7 that contacts the respective sides of the gate trench 9a and dummy trench 9b. The emitter region 6 is provided with dividing into two sections in the low-resistance base contact region 7 in FIG. 15, but the emitter region 6 may be divided into three or more sections, or may be single without dividing.
(40) In addition, as illustrated in FIG. 16, a plurality of, for example, two dummy trenches 9b may be arranged adjacent to each other between the gate trenches 9a. A base layer (5b, 5d) between adjacent dummy trenches 9b has the p-type floating base region 5b and a p-type extraction base region 5d. The base isolation region 5c is the n-type semiconductor layer. In the extending direction of the dummy trench 9b, the extraction base region 5d and the floating base region are alternately located so as to face each other through the base isolation region 5c. The active base region 5a between the gate trench 9a and the dummy trench 9b faces the floating base region 5b between the dummy trenches 9b. The floating base region 5b between the gate trench 9a and the dummy trench 9b faces the extraction base region 5d between the dummy trenches 9b. As illustrated in FIG. 17, the extraction base region 5d is separated from the floating base region 5b by the base isolation region 5c. In an upper portion of the extraction base region 5d, the p.sup.+-type low-resistance base contact region 7 is selectively placed, which is physically connected to the emitter electrode 13 through a contact hole opened in the interlayer insulation film 12. Thus, the extraction base region 5d is connected to the emitter potential.
(41) In the on-state of the IGBT according to the embodiment, the extraction path Hp.sub.on is formed in each of the base isolation regions 5c in contact with the sides of the respective dummy trenches 9b, as illustrated in FIG. 16. Holes accumulated in the floating base region 5b between the gate trench 9a and the dummy trench 9b are extracted through the extraction paths Hp.sub.on facing the gate trench 9b to the low-resistance base contact region 7 in the active base region 5a. Holes accumulated in the floating base region 5b between the dummy trenches 9b are extracted through the extraction path Hp.sub.on facing the adjacent dummy trench 9b to the low-resistance base contact region 7 in the extraction base region 5d. Thus, since the density of the extraction paths Hp.sub.on formed on the sides of the dummy trench 9b increases, the excess holes accumulated in the floating base region 5b can be efficiently extracted via the extraction path Hp.sub.on on both sides of the dummy trench 9b. In the off-state, the extraction path Hp.sub.off is formed on the side of the gate trench 9a. As a result, in the IGBT according to the embodiment, the potential change in the floating base region can be suppressed to be moderated during the switching process, making it possible to easily control the voltage change dV/dt and preventing an increase in switching loss.
(42) In addition, as illustrated in FIG. 18, a plurality of, for example, two gate trenches 9a may be arranged adjacent to each other between the dummy trenches 9b. The floating base region 5b sandwiched by the adjacent gate trenches 9a faces the active base region 5a sandwiched by the gate trench 9a and the dummy trench 9b. The active base region 5a sandwiched by the adjacent gate trenches 9a faces the floating base region 5b sandwiched by the gate trench 9a and the dummy trench 9b. In the on-state of the IGBT, the extraction path Hp.sub.on is formed on the side of the dummy trench 9b. In the off-state, the extraction paths Hp.sub.off are formed on the sides of the gate trenches 9a. The extraction path Hp.sub.off is formed not only between the gate trench 9a and the dummy trench 9b but also between the gate trenches 9a, and the density of the extraction paths Hp.sub.off increases. Therefore, holes remaining in the floating base region 5b in the off-state can be efficiently extracted via the extraction path Hp.sub.off. As a result, in the IGBT according to the embodiment, the potential change in the floating base region can be suppressed to be moderated during the switching process, making it possible to easily control the voltage change dV/dt and preventing an increase in switching loss.
Other Embodiments
(43) While the present invention has been described by the above disclosed embodiments, it should be understood that the present invention is not intended to be limited to the descriptions of the Specification and the drawings implementing part of this disclosure. Various alternative embodiments, examples, and technical applications will be apparent to those skilled in the art according to this disclosure.
(44) Although silicon (Si) has been used as the material of the semiconductor substrate in the embodiments described above, the semiconductor material is not limited and may be a wide bandgap semiconductor such as silicon carbide (SiC) or gallium nitride (GaN). The IGBT is not limited to a single IGBT, but may be a reverse-conducting IGBT integrated with a freewheeling diode.
(45) As described above, it should be noted that the present invention includes various embodiments which are not disclosed herein. Therefore, the scope of the present invention is defined only by the technical features specifying the invention prescribed by the claims reasonably derived from the description heretofore.
