VOLTAGE-CONTROLLED OSCILLATOR (LC VCO) AND METHOD OF OPERATION THEREOF

Abstract

A dual tank LC-tuned Voltage Controller Oscillator (LC VCO) comprising a differential pair of cross-coupled transistors (M.sub.1, M.sub.2, M.sub.3, M.sub.4) produces a negative impedance by keeping a lower drain swing and a sufficient gate swing. The gate terminals of first and second transistors M.sub.1, M.sub.2 and third and fourth transistors M.sub.3, M.sub.4 are separated through a series of two inductors L.sub.1, L.sub.2 and two cross-coupled capacitors are connected between the drain and gate terminals of cross-coupled transistors to attenuate the output swing. The VCO tank further comprises two R2R Digital to Analog Converters (DAC) to bias both NMOS and PMOS cross-coupled pairs of transistors, to produce a common mode noise.

Claims

1. A dual-tank LC-tuned voltage-controlled oscillator (LC VCO) comprising: a negative impedance circuit comprising: a lower pair of transistors comprising a first (M.sub.1) and second (M.sub.2) transistors; an upper pair of transistors comprising a third (M.sub.3) and fourth (M.sub.4) transistors; a drain terminal of the third transistor (M.sub.3) coupled to a drain terminal of said first transistor (M.sub.1), a drain terminal of said fourth transistor (M.sub.4) coupled to a drain terminal of said second transistor (M.sub.2); a gate terminal of the first transistor (M.sub.1) is coupled to a gate terminal of second transistor (M.sub.2) through a pair of serially connected inductors (L.sub.1, L.sub.2) and a gate terminal of the third transistor (M.sub.3) is coupled to a gate terminal of fourth transistor (M.sub.4) through a pair of serially connected inductors (L.sub.1, L.sub.2); and a swing extension circuit comprising: AC coupling of each transistor pair, wherein each transistor pair is cross coupled through individual capacitors, C.sub.1, C.sub.2, C.sub.3 and C.sub.4; a Voltage controlled Oscillator (VCO) tank circuit (101) comprising: an inductive element (L.sub.T) and a pair of capacitive element coupled (C.sub.5T, C.sub.6T) across the drains of the lower pair of transistors and the drain terminals of the upper pair of transistors; a biasing circuit comprising: a first DAC (D.sub.1) is applied to a centre tap of the serially connected inductors (L.sub.1, L.sub.2) positioned between the gate terminal of the first transistor (M.sub.1) and the gate terminal of second transistor (M.sub.2); and a second DAC (D.sub.2) is applied to a centre tap of the serially connected inductors (L.sub.1, L.sub.2) positioned between the gate terminal of the third (M.sub.3) and the gate terminal of the fourth transistor (M.sub.4); wherein the swing extension circuit and the biasing circuit maintain the negative impedance circuit in saturation region; and wherein the swing extension circuit cause the VCO tank circuit to generate two output, V.sub.OP and V.sub.ON, which have a 180-degree phase shift with each other, wherein the V.sub.OP and V.sub.ON are directly connected to the drain terminals of the transistors (M.sub.1, M.sub.2) and (M.sub.3, M.sub.4), respectively.

2. The oscillator (LC VCO) as claimed in claim 1, wherein the inductor (L.sub.1) has a value of 100 Pico Henry (pH) and the inductor (L.sub.2) has a value of 500 Pico Henry (pH), configured to achieve a frequency of 12 GHz; and wherein, the frequency is tuned with a design equation of f=(1)/(2*pi*sqrt(LC))

3. The oscillator (LC VCO) as claimed in claim 1, wherein the capacitor C.sub.2 couples the gate of the first transistor to the drain of the second transistor, the capacitor C.sub.1 couples the drain of the first transistor to the gate of the second transistor, the capacitor C.sub.4 couples the gate of a third transistor to the drain of a fourth transistor, and the capacitor C.sub.3 couples the drain of the third transistor to the gate of the fourth transistor.

4. The oscillator (LC VCO) as claimed in claim 1, wherein the capacitors (C.sub.5T, C.sub.6T) values varies from 200 fF-500 fF.

5. The oscillator (LC VCO) as claimed in claim 1, wherein first DAC is configured to bias the lower pair of transistors and the second DAC is configured to bias the upper pair of transistors, to reduce common mode noise in the VCO tank.

6. The oscillator (LC VCO) as claimed in claim 1, wherein the inductive element (L.sub.T) of the VCO tank circuit is connected in parallel to the pair of capacitive elements (C.sub.5T, C.sub.6T).

7. The oscillator (LC VCO) as claimed in claim 1, wherein the inductive element (L.sub.T) and the capacitive elements (C.sub.5T, C.sub.6T) are configured to a. determine the frequency of the VCO and b. setting the oscillation frequency of the VCO

8. The oscillator (LC VCO) as claimed in claim 1, wherein said upper pair of transistors is a cross-coupled PMOS transistor pair, and the lower pair of transistors is a cross-coupled NMOS transistor pair.

9. The oscillator (LC VCO) as claimed in claim 1, wherein the cross coupled capacitors C.sub.1-C.sub.4, are configured to attenuate output swing of the negative impedance circuit.

10. The oscillator (LC VCO) as claimed in claim 1, wherein the serially connected inductors (L.sub.1, L.sub.2) placed in series between the gate terminals of the NMOS and PMOS transistors (M.sub.1, M.sub.2, M.sub.3, M.sub.4), ensures that the gate and drain terminals of the transistors experience different swings.

11. A method for operating a dual-tank LC-tuned voltage-controlled oscillator (LC VCO), comprising the steps of: a. providing a negative impedance circuit comprising: i. a lower pair of transistors comprising a first (M1) and second (M2) transistors; ii. an upper pair of transistors comprising a third (M3) and fourth (M4) transistors; iii. connecting a drain terminal of the third transistor (M3) to a drain terminal of the first transistor (M1), and connecting a drain terminal of the fourth transistor (M4) to a drain terminal of the second transistor (M2); iv. coupling a gate terminal of the first transistor (M1) to a gate terminal of the second transistor (M2) through a pair of serially connected inductors (L1, L2), and coupling a gate terminal of the third transistor (M3) to a gate terminal of the fourth transistor (M4) through another pair of serially connected inductors (L1, L2); b. providing a swing extension circuit comprising: i. AC coupling of each transistor pair through individual capacitors (C1, C2, C3, C4); c. providing a Voltage Controlled Oscillator (VCO) tank circuit (101) comprising: i. an inductive element (LT) and a pair of capacitive elements (C.sub.5T, C.sub.6T) coupled across the drains of the lower pair of transistors and the drain terminals of the upper pair of transistors; d. providing a biasing circuit comprising: i. applying a first Digital-to-Analog Converter (DAC) (D1) to a center tap of the serially connected inductors (L1, L2) positioned between the gate terminal of the first transistor (M1) and the gate terminal of the second transistor (M2); ii. applying a second Digital-to-Analog Converter (DAC) (D2) to a center tap of the serially connected inductors (L1, L2) positioned between the gate terminal of the third transistor (M3) and the gate terminal of the fourth transistor (M4); e. maintaining the negative impedance circuit in the saturation region using the swing extension circuit and the biasing circuit; f. generating two outputs, VOP and VON, from the VCO tank circuit with a 180-degree phase shift, wherein VOP and VON are directly connected to the drain terminals of the transistors (M1, M2) and (M3, M4), respectively.

Description

BRIEF DESCRIPTION OF DRAWING

[0024] The foregoing summary, as well as the following detailed description of embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the disclosure, there is shown in the present document example constructions of the disclosure, however, the disclosure is not limited to the specific methods and device disclosed in the document and the drawing. The detailed description is described with reference to the following accompanying figures.

[0025] FIG. 1: illustrates the prior art consisting of a circuit diagram of the 3.sup.rd order Integer-N phase-locked loop (PLL).

[0026] FIG. 2: illustrates the prior art consisting of conventional LC-tuned voltage-controlled oscillators (LC VCO) comprising transistors, inductor (L.sub.T), and capacitor (C.sub.T).

[0027] FIG. 3: illustrates the proposed LC-tuned voltage-controlled oscillators (LC VCO) circuit comprising cross-coupled transistors, inductors (L.sub.T, L.sub.1), capacitors (C.sub.1, C.sub.V), and R2R DAC circuit.

[0028] FIG. 4: illustrates the simulation response of voltage swings at the drain and gate terminals of the LC VCO tank.

[0029] FIG. 5: illustrates the simulation response of the phase noise between the proposed and conventional LC VCO tank.

[0030] The figures depict various embodiments of the present disclosure for purposes of illustration only. One skilled in the art will readily recognize from the following discussion that alternative embodiments of the structures illustrated herein may be employed without departing from the principles of the disclosure described herein.

DETAILED DESCRIPTION OF THE INVENTION

[0031] Some embodiments of this disclosure, illustrating all its features, will now be discussed in detail. The words comprising, having, and including, and other forms thereof, are intended to be equivalent in meaning and be open ended in that an item or items following any one of these words is not meant to be an exhaustive listing of such item or items, or meant to be limited to only the listed item or items. It must also be noted that as used herein and in the appended claims, the singular forms a, an, and the include plural references unless the context clearly dictates otherwise. Although any devices and methods similar or equivalent to those described herein can be used in the practice or testing of embodiments of the present disclosure, the exemplary, devices and methods are now described. The disclosed embodiments are merely exemplary of the disclosure, which may be embodied in various forms.

[0032] Various modifications to the embodiment will be readily apparent to those skilled in the art and the generic principles herein may be applied to other embodiments. However, one of ordinary skill in the art will readily recognize that the present disclosure is not intended to be limited to the embodiments illustrated, but is to be accorded the widest scope consistent with the principles and features described herein.

[0033] Following is a list of elements and reference numerals used to explain various embodiments of the present subject matter.

TABLE-US-00001 Reference Numeral Element Description (LC VCO) Dual tank LC-tuned voltage-controlled oscillator 100 Negative impedance circuit: Upper pair 101 Voltage controlled Oscillator (VCO) tank circuit 102 Negative impedance circuit: Lower pair (M.sub.1, M.sub.2) Cross-coupled NMOS transistors or First transistor and second transistor (M.sub.3, M.sub.4) Cross-coupled PMOS transistors or third transistor and fourth transistor (L.sub.1) & (L.sub.2) Serially connected Inductor (C.sub.1, C.sub.2, C.sub.3, C.sub.4) Cross coupled Capacitors (L.sub.T) Inductor of the VCO tank (C.sub.5T and C.sub.6T) Capacitors of the VCO tank (D.sub.1, D.sub.2) R2R Digital-to-analog converters (DAC) (V.sub.OP) Output (V.sub.OP) (V.sub.ON) Output (V.sub.ON) 400 Voltage waveforms at the Drain and Gate terminal 402 Drain swing 404 Gate swing 500 Phase noise graph 502 Conventional phase noise graph 504 Phase noise graph of dual tank LC VCO circuit

[0034] FIG. 1 illustrates a prior art showing a simplified diagram of a 3.sup.rd order Integer-N phase-locked loop (PLL). The PLL circuit comprising a phase frequency detector (PFD) receives input from the reference clock (CLK_REF), a charge pump (CP), capacitors (C.sub.1, C.sub.2, C.sub.P), resistors (R.sub.1, R.sub.2), a voltage-controlled oscillator, output clock (CLK_.sub.OUT), and a low pass filter within its loop.

[0035] Phase Frequency Detector (PFD)Phase Frequency Detector is a component within a Phase-Locked Loop (PLL) system that compares the phase and frequency of two input signals and generates an output signal representing their phase difference. The Phase Frequency Detector typically has two input signals. Reference SignalThis is typically the input signal that the PLL is trying to lock onto or synchronize with. It could be an external clock signal or a reference oscillator signal. Feedback SignalThis is the output signal generated by the PLL's Voltage-Controlled Oscillator (VCO) or another element of the feedback loop. It represents the PLL's current output frequency and phase. Phase evaluation and locking a significant feature of a frequency-tracking circuit. The PFD analyses the output signal phase with the reference signal phase and generates a control signal proportional to the phase error.

[0036] Charge Pump (CP)The charge pump converts the phase difference between the reference input signal and the feedback signal (usually from a Voltage-Controlled Oscillator or VCO) into a control voltage. It consists of a pair of switches and a capacitor. While the polarity of the current varies based on the value of the UP and DOWN signals, the current's amplitude never changes. The loop filter is a low-pass filter that smoothens the output of the charge pump, converting the pulsed output from the charge pump into a continuous control voltage.

[0037] Loop-FilterThe loop filters remove high-frequency components from the charge pump output, allowing only the DC component to pass through it. This DC voltage serves as the control voltage for the VCO, adjusting its frequency to minimize the phase difference between the reference and feedback signals. The low-pass filter removes high-frequency elements in the PFD output, enabling the DC value to adjust the voltage-controlled oscillator frequency (VCO). A loop filter consists of a passive RC network.

[0038] Voltage Controlled Oscillator (VCO)Voltage-controlled oscillators are an essential part of the PLL architecture. A VCO's fundamental idea is to give a clock by following the Barkhausen criteria for oscillation. Barkhausen criteria say that the VCO's transfer function magnitude at the oscillation frequency is one while the phase is at 180 degrees. VCO's output frequency is linearly related to the input voltage applied. In LC-VCO, phase noise performance is good, but it takes a larger area to implement. LC VCO will be used for better phase noise performance.

[0039] Frequency dividerA frequency divider in the PLL is required for the multiple rations output frequency signals. The frequency divider gives the divided clock signal to be locked with the reference signals. This operation is done with the 1/N divider. The clock is divided by multiple factors to synchronize the reference clock signal.

[0040] FIG. 2 illustrates a prior art showing a simplified diagram of a conventional voltage controller oscillator (VCO). The VCO comprises a CMOS cross-coupled pair of transistors (M.sub.1 and M.sub.2). The transistors M.sub.1 and M.sub.2 form the differential pair, and the gates and drain of M.sub.1 and M.sub.2 transistors are cross-coupled. The cross-coupling of M.sub.1 and M.sub.2 transistors produces the negative resistance to compensate for the loss of VCO tank. The negative resistance is expressed as follows (where g.sub.m1 and gm.sub.2 represent NMOS and PMOS transconductance.

[00003]$\begin{array}{cc}{R}_{\mathrm{neg}}=\frac{-1}{g_{m1}+g_{m2}}& \left(1\right)\end{array}$

The VCO circuit further comprises the inductor (L.sub.T) and capacitor (C.sub.T) are connected parallelly to produce frequency-stable oscillations. The frequency and parallel resistance can be expressed as follows.

[00004]$\begin{array}{cc}{W}_{\mathrm{osc}}=\frac{1}{\sqrt{L_T{C}_T}}& \left(2\right)\end{array}$$R_{\mathrm{eq}}={\mathrm{QL}}_T{W}_{\mathrm{osc}}$

[0041] Further, if the parallel loss component is greater than the negative resistance produced by the cross-coupled pair, then the oscillator will produce sustainable oscillations. To produce sustainable oscillations, either the VCO circuit is increasing the bias current by improving the gm or improving the Quality factor (Q) of the inductor to reduce the tank loss. The amplitude of the output (o/p) waveform depends on the VCO tank resistance and bias current. The output oscillations are of sinusoidal waveforms and if the current is much more than required then the waveform will saturate, and a square wave will be produced. The phase noise of the VCO depends on the output amplitude, which will increase the amplitude. A larger swing will push the operating region of M.sub.1, and M.sub.2 transistors out of the saturation region. At the maximum peak point of the voltage, PMOS will move into the triode region, whereas at the minimum voltage, NMOS will move into the triode region. Triode region-based operation will be creating loading onto the tank and hence degrade the Quality factor of the tank.

[0042] The circuit shown in FIG. 2 is a very simple and reliable architecture. The phase noise practice is to increase the signal swing to improve the as explained in Lesson's formula shown in (3).

[00005]$\begin{array}{cc}L\left(f\right)=\frac{4\mathrm{KTFR}}{V_{\mathrm{rms}}^2}{\left(\frac{w_o}{2QW}\right)}^2& \left(3\right)\end{array}$

[0043] In an embodiment, the high swing leads to degradation in the noise and supply sensitivity in this architecture because the devices will be pushed out of the saturation region and the tank inductor is shunted to the supply/ground. Therefore, the tank loses its reactive power to the ground. The present invention improves the VCO phase noise from this aspect.

[0044] FIG. 3 illustrates a circuit diagram of the proposed LC tuned voltage controlled oscillator (LC VCO). FIG. 1 depicts a schematic diagram of the dual-tank LC-tuned voltage-controlled oscillator (LC VCO) according to an embodiment of the present invention. The LC VCO comprises a negative impedance circuit, a swing extension circuit, and a VCO tank (101) circuit. The negative impedance circuit includes a lower pair of transistors (M.sub.1, M.sub.2) and an upper pair of transistors (M.sub.3, M.sub.4). The source terminal of the third transistor (M.sub.3) is coupled to the drain terminal of the first transistor (M.sub.1), and the source terminal of the fourth transistor (M.sub.4) is coupled to the drain terminal of the second transistor (M.sub.2). The gate terminals of the first and third transistors (M.sub.1, M.sub.3) are coupled to the gate terminals of the second and fourth transistors (M.sub.2, M.sub.4), respectively, through pairs of serially connected inductors (L.sub.1, L.sub.2). This configuration facilitates cross coupling between the transistors, enabling stable oscillations.

[0045] The swing extension circuit comprises AC coupling of each transistor pair through individual capacitors (C.sub.1, C.sub.2, C.sub.3, C.sub.4). This circuitry aids in maintaining the negative impedance circuit in the saturation region, ensuring stable operation of the LC VCO. The VCO tank circuit (101) includes an inductive element (L.sub.T) and a pair of capacitive elements (C.sub.5T and C.sub.6T) coupled across the drains of the lower pair of transistors and the drain terminals of the upper pair of transistors. These components determine the oscillation frequency of the LC VCO and generate two output signals, V.sub.OP and V.sub.ON, with a 180-degree phase shift. The V.sub.OP and V.sub.ON signals are directly connected to the drain terminals of the transistors M.sub.1, M.sub.3, and M.sub.2, M.sub.4, respectively.

[0046] In one embodiment, the inductor (L.sub.1) has a value of 100 pico farads (pF), and the inductor (L.sub.T) has a value of 500 pF. Additionally, the capacitors C.sub.1, C.sub.2, C.sub.3, and C.sub.4 are configured to facilitate cross-coupling between the transistors, attenuate output swing, and reduce common-mode noise.

[0047] Furthermore, in certain embodiments, the LC VCO may include digital-to-analog converters (DACs) (D.sub.1, D.sub.2) configured to bias the transistors, thereby reducing common-mode noise in the VCO tank. These DACs (D.sub.1, D.sub.2) can be applied to the centre taps of the serially connected inductors (L.sub.1, L.sub.2) to provide precise biasing control.

[0048] In an embodiment, the required resolution of the required bias voltages to the negative impedance circuit (100, 101), the DAC can be used with its overall number of bits (N). For an oscillation with very low amplitude, 5 bits of DAC are sufficient enough for the proposed structure, however, N bits can be determined with the required resolution of the bias voltage. The DAC may be any suitable structure of current, voltage, and charge depending on the requirement. For the LC VCO structure, the resistive DAC generates DC Levels.

[0049] The output terminals are directly connected to the drain terminals of the cross-coupled transistors of the VCO. The output swing is being attenuated by the capacitive divider formed by C.sub.1 and C.sub.gs of the transistors as shown in equation (4).

[00006]$\begin{array}{cc}{V}_x=V_{\mathrm{on}}\frac{C_1}{C_1+c_{\mathrm{gs}}}& \left(4\right)\end{array}$

[0050] In an embodiment, due to the swing reduction at the terminal, the phase noise is improved because there is no Quality factor degradation over the signal swing. The DAC voltage affects the output swing. Therefore, the swing control doesn't require complicated capacitive bank tuning.

[0051] The main issue with the conventional VCO is the gate and drain swings are too high, however, the gate swing is very important but not the drain swing. The proposed LC VCO circuit (300) is having lower drain swing and a large gate swing (enough to steer the current).

[0052] The oscillator phase noise is improved by enhancing the loaded quality factor (Q) of the LC VCO tank (300). Inductor Q will increase with the frequency and varactor Q will decrease with the frequency, hence overall LC VCO tank Q will be dominated by the inductor at a lower frequency. This can be increased by the following techniques. [0053] 1. Redesigning the inductor with a single turn and a larger area [0054] 2. Increasing the VCO capacitors (C.sub.5T and C.sub.6T) width and decreasing the length [0055] 3. Using a very small inductor (L.sub.1) such that small series resistance to achieve the largest Q.

[0056] In an embodiment, every wireless or wireline system requires a precise and accurate clock system to assist the timing. To mitigate the setup and hold timing violations, the jitter of the clock should be as low as possible. The jitter of the clock system is decided by the clock generation system. A frequency synthesizer or phase-locked loop (PLL) will generate the required high-frequency clock by using the accurate reference clock (from the Crystal oscillator). The phase noise of the PLL decides the jitter of the clocking system. The Voltage Controlled Oscillator (VCO) and better phase with lower power consumption dominate the phase.

[0057] FIG. 4 illustrates the simulation graph (400) showing gate and drain voltage swings. LC VCO tank achieves the lower drain swing (402) and higher gate swing (404). The Drain swing (404) and gate swing (402) have a 180-degree phase shift with each other. The ratio of swing attenuation is (1:3) for a typical process corner at room temperature (27 deg).

[0058] FIG. 5 illustrates the simulation graph (500) showing the comparison of the phase noise between the conventional (502) and proposed (LC VCO) circuit (505). The proposed LC VCO circuit (300) shows 3 dB improvement (114 dBc/Hz) at 1 MHz frequency offset from the carrier frequency. The LC VCO circuit improves a phase jitter up to 19 femtoseconds (fs). The Phase jitter is calculated from the phase noise through the following integration expression.

[00007]$\begin{array}{cc}\mathrm{Jitter}=1/\left(2.Math.\mathrm{f\_}0\right)^2\left(\mathrm{\_l}^h2\mathrm{S\_}\left(f\right)\right)& \left(5\right)\end{array}$

[0059] In some embodiments, the dual-tank LC-tuned voltage-controlled oscillator (LC VCO) is proposed, to operate at 1 MHz frequency with an improved phase noise, phase jitter, figure of merit (FOM), and a quality factor.

[0060] In some embodiments, the value of the inductor L.sub.1 is 100 picofarad (pF) and the inductor (L.sub.T) is 500 picofarad (pF).

[0061] In some embodiments, the two outputs (V.sub.op) and (V.sub.on) of the VCO tank have a 180-degree phase shift with each other.

[0062] In some embodiments, the dual tank LC-tuned voltage-controlled oscillator (LC VCO) improves the phase noise of the VCO by 3 dB without increasing the power consumption.

[0063] In some embodiments, the dual tank LC-tuned voltage-controlled oscillator (LC VCO) improves the Figure of merit (FOM) by 2.3 dB.

[0064] In some embodiments, the dual tank LC-tuned voltage-controlled oscillator (LC VCO) improves phase jitter by 19 femtoseconds (fs).

[0065] In some embodiments, the dual tank LC-tuned voltage-controlled oscillator (LC VCO) improves the phase noise because there is no Quality factor degradation over the signal swing due to the swing reduction at the transistor terminal.

[0066] In some embodiments, the dual tank LC-tuned voltage-controlled oscillator (LC VCO) improves oscillator phase noise by enhancing the loaded quality factor (Q) of the tank.

[0067] In some embodiments, the dual tank LC-tuned voltage-controlled oscillator (LC VCO) redesigns the inductor with a single turn and a larger area.

[0068] In some embodiments, the dual tank LC-tuned voltage-controlled oscillator (LC VCO) increases the capacitor width and decreases the length of capacitor of the VCO tank.

[0069] In some embodiments, the dual tank LC-tuned voltage-controlled oscillator (LC VCO) provides a very small value inductor to achieve the largest Q.

[0070] With respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for the sake of clarity.

[0071] It will be understood by those within the art that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as open terms (e.g., the term including should be interpreted as including but not limited to, the term having should be interpreted as having at least, the term includes should be interpreted as includes but is not limited to, etc.). It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present.

[0072] Although implementations for the dual-tank LC-tuned voltage controller oscillator (LC VCO) have been described in language specific to structural features and/or methods, it is to be understood that the appended claims are not necessarily limited to the specific features described. Rather, the specific features are disclosed as examples of implementation for the dual-tank LC-tuned voltage controller oscillator (LC VCO).