SWITCHING DEVICE WITH PASSIVE OVERCURRENT PROTECTION

Abstract

A switching device includes a semiconductor power switch and a temperature sensitive element (TSE). The power switch has a normal operating temperature range and an active area. The TSE is connected to the power switch proximate the active area, and configured such that conduction of an electric current through the TSE is negligible when a temperature of the TSE is within the normal operating temperature range. Conduction increases when a temperature of the TSE is above the normal operating temperature range. This continues to a level sufficient for turning off the semiconductor power switch, e.g., by shorting the gate and source of the power switch. The TSE thus protects the power switch from thermal damage during an overcurrent event. An inverter circuit includes a direct current link capacitor and multiple switching pairs of the switching devices.

Claims

1. A switching device, comprising: a semiconductor power switch having a normal operating temperature range; and a temperature sensitive element (TSE) connected to the semiconductor power switch, wherein the TSE is configured such that conduction of an electric current through the TSE is (i) negligible when a temperature of the TSE is within the normal operating temperature range, and (ii) increases above the normal operating temperature range to a level sufficient for turning off the semiconductor power switch, thereby protecting the semiconductor power switch from thermal damage during an overcurrent event.

2. The switching device of claim 1, wherein: the semiconductor power switch is a power metal-oxide semiconductor field-effect transistor (MOSFET).

3. The switching device of claim 2, wherein: the MOSFET is a silicon carbide (SiC) power MOSFET.

4. The switching device of claim 3, wherein the TSE includes a lateral junction field-effect transistor (JFET) having a source contact and a gate contact, and wherein the source contact and the gate contact of the lateral JFET are respectively connected to a source contact and a gate contact of the SiC power MOSFET.

5. The switching device of claim 3, wherein the TSE includes a lateral junction field-effect transistor (JFET) having a source contact and a gate contact that are each connected to the source contact of the SiC power MOSFET, and a drain contact that is connected to a gate contact of the SiC power MOSFET.

6. The switching device of claim 5, wherein the lateral JFET is a gated lateral JFET having a top gate structure that spans a channel region of the lateral JFET.

7. The switching device of claim 6, further comprising: a control circuit configured to set the gate contact of the gated lateral JFET to a predetermined electric potential to thereby adjust a current-to-temperature sensitivity level of the gated lateral JFET.

8. The switching device of claim 7, wherein the control circuit includes a voltage divider circuit coupled to the source and the gate of the gated lateral JFET and the SiC power MOSFET.

9. The switching device of claim 6, wherein the top gate structure is constructed of a polysilicon material.

10. The switching device of claim 3, wherein the semiconductor switch has a stripe layout and the lateral JFET is implemented in an adjacent parallel stripe.

11. The switching device of claim 3, wherein the semiconductor switch has a stripe layout and the lateral JFET is implemented along a same stripe as the SiC power MOSFET.

12. A switching device, comprising: a silicon carbide (SiC) power metal-oxide semiconductor field-effect transistor (MOSFET) having a source contact, a gate contact, a drain contact, a normal operating temperature range, and an active area; and a lateral junction field-effect transistor (JFET) that is monolithically integrated with the SiC power MOSFET and positioned proximate the active area, wherein the lateral JFET is configured such that a conduction of current through an N-channel region of the lateral JFET is: (i) less than about 1 milliamp (mA) when a temperature of the lateral JFET is within a predetermined normal operating temperature range of the SiC power MOSFET; and (ii) increases above the normal operating temperature range to at least about 10 mA to short the gate contact and the source contact of the SiC power MOSFET and thereby turn off the SiC power MOSFET during an overcurrent event.

13. The switching device of claim 12, wherein the lateral JFET is a gated lateral JFET having a top gate structure spanning an N-channel channel region.

14. The switching device of claim 13, wherein a source of the lateral JFET and the top gate structure are electrically connected to the source of the SiC power MOSFET, and a drain of the lateral JFET is connected to a gate of the SiC power MOSFET.

15. The switching device of claim 13, further comprising: a control circuit configured to adjust a current-to-temperature sensitivity level of the gated lateral JFET.

16. The switching device of claim 15, wherein the control circuit is connected to the gate contact of the gated lateral JFET and configured to set the top gate structure of the gated lateral JFET at a predetermined electric potential to adjust the current-to-temperature sensitivity level.

17. The switching device of claim 15, wherein the control circuit includes a voltage divider circuit.

18. The switching device of claim 13, wherein the top gate structure is constructed of a polysilicon material.

19. An inverter circuit for use with a direct current (DC) voltage supply and a polyphase motor, the inverter circuit comprising: a positive voltage rail; a negative voltage rail; a DC link capacitor connected to the positive voltage rail and the negative voltage rail, and configured to receive a DC voltage waveform from the DC voltage supply; and plurality of switching devices arranged in multiple switching pairs, each of the multiple switching pairs being connectable to the DC link capacitor and a corresponding phase lead of the polyphase motor, wherein each respective one of the switching devices includes a semiconductor power switch that is monolithically integrated with a temperature sensitive element (TSE), the TSE being configured such that conduction of an electric current through the TSE is: (i) negligible when a temperature of the TSE is within a normal operating temperature range of the semiconductor power switch; and (ii) increases above the normal operating temperature range to a level sufficient for turning off the semiconductor power switch, thereby protecting the semiconductor power switch during an overcurrent event.

20. The inverter circuit of claim 19, wherein each respective one of the semiconductor power switches is a silicon carbide power metal-oxide semiconductor field-effect transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings described herein are for illustrative purposes only, are schematic in nature, and are intended to be exemplary rather than to limit the scope of the disclosure.

[0012] FIG. 1 illustrates an exemplary inverter circuit for a polyphase electric machine, with the inverter circuit using one or more switching devices equipped with passive overcurrent protection feature in accordance with the present disclosure.

[0013] FIG. 2 is a schematic illustration of a switching device in which a semiconductor power switch is monolithically integrated with a temperature-sensitive element (TSE).

[0014] FIG. 2A is a plot of voltage, current, and temperature for a representative lateral junction field effect transistor (JFET).

[0015] FIG. 3 is a schematic illustration of a switching device using a gated lateral JFET according to another embodiment.

[0016] FIG. 3A is a plot of voltage, current, and temperature for the representative gated lateral JFET shown in FIG. 3.

[0017] FIG. 4 is a schematic illustration of a switching device in which a voltage divider is used to reduce a gate voltage for control of the gated lateral JFET.

[0018] FIG. 4A is a plot of voltage, current, and temperature for the representative gated lateral JFET shown in FIG. 4.

[0019] FIG. 5 is a schematic plan view illustration of a possible layout for implementing the switching device of FIGS. 3 and 4.

[0020] FIG. 6A is a schematic plan view illustration of a possible layout for implementing the switching device of FIG. 2.

[0021] FIGS. 6B and 6C are schematic plan view illustrations of possible layouts for implementing the switching device of FIGS. 3 and 4.

[0022] FIG. 7 is a schematic illustration of a possible layout of the switching device having a temperature-controlled (TC) gate switch according to yet another embodiment.

[0023] FIGS. 8A, 8B, and 8C illustrate representative embodiments of a TC gate switch as shown in FIG. 7.

[0024] The present disclosure may be modified or embodied in alternative forms, with representative embodiments shown in the drawings and described in detail below. Inventive aspects of the present disclosure are not limited to the disclosed embodiments. Rather, the present disclosure is intended to cover alternatives falling within the scope of the disclosure as defined by the appended claims.

DETAILED DESCRIPTION

[0025] The components of the embodiments described and illustrated herein may be arranged and designed in a variety of different configurations. Thus, the following detailed description is not intended to limit the scope of the disclosure as claimed, but is instead representative of possible embodiments thereof. In addition, while numerous specific details are set forth in the following description in order to provide a thorough understanding of the embodiments disclosed herein, some embodiments can be practiced without some of these details. Moreover, for the purpose of clarity, certain technical material that is understood in the related art has not been described in detail in order to avoid unnecessarily obscuring the disclosure.

[0026] For purposes of convenience and clarity only, directional terms such as top, bottom, left, right, up, over, above, below, beneath, rear, and front, may be used with respect to the drawings. These and similar directional terms are not to be construed to limit the scope of the disclosure. Furthermore, the disclosure, as illustrated and described herein, may be practiced in the absence of an element that is not specifically disclosed herein. The use of ordinals such as first, second and third does not necessarily imply a ranked sense of order, but may only distinguish between multiple instances of an act or structure.

[0027] With reference to the drawings, wherein like reference numbers refer to the same or similar components throughout the several views, an inverter circuit 10 is illustrated in FIG. 1 for use with an exemplary polyphase rotary electric machine (ME) 12. The inverter circuit 10 may include switching devices 20 configured to passively protect elements of the inverter circuit 10 from thermal damage during a transient overcurrent condition as summarized above. Various implementations of the switching devices 20 are set forth in detail below with reference to FIGS. 2-8C. Although the switching devices 20 may be used as part of the exemplary inverter circuit 10 of FIG. 1, those skilled in the art will appreciate that other power electronic devices may benefit from use of the switching devices 20, including voltage rectifiers, DC-DC converters, and the like, and therefore the present teachings are not limited to the representative use illustrated in FIG. 1.

[0028] The electric machine 12, e.g., an electric traction motor for powering a load in a stationary or mobile system in one or more embodiments, includes the phase leads 14, with each of the phase leads 14 being connectable to the inverter circuit 10. For example, a typical three-phase embodiment of the electric machine 12 includes three phase leads 14, which in turn are individually labeled a, b, and c to indicate nominal a, b, and c phases. The inverter circuit 10 also includes a positive voltage rail 16.sup.+, a negative voltage rail 16.sup. (electrical ground), and a direct current (DC) link capacitor 17. The DC link capacitor 17 is connected to the respective positive and negative voltage rails (16.sup.+, 16.sup.) and configured to receive a DC voltage waveform from a DC voltage supply 18, for instance a multi-cell electrochemical battery pack of an application-suitable battery chemistry such as lithium-ion, lithium-metal, nickel-metal hydride, etc.

[0029] Within the inverter circuit 10 of FIG. 1, a plurality of the semiconductor switching devices 20, also individually labeled S1, S2, S3, S4, S5, and S6 in the illustrated example construction, are arranged in multiple switching pairs SP1, SP2, and SP3, i.e., power switches (S1, S2), (S3, S4), and (S5, S6), respectively. Each respective switching pair SP1, SP2, and SP3 is connected to the DC link capacitor 17 and a corresponding phase lead 14 of the electric machine 12. That is, the switching pairs SP1, SP2, and SP3 are respectively connected to the nominal a, b, and c phase leads 14 at nodes N.sub.1, N.sub.2, and N.sub.3.

[0030] In a normal switching operation when energizing the phase leads 14 to generate motor output torque (To) on a rotary output member 120 via the electric machine 12, the switching devices 20 connected to the positive voltage rail 16.sup.+, which are also referred to in the art as upper switches, have an opposite conductive state than the switching devices 20 connected to the negative voltage rail 16.sup. or ground (lower switches). However, factors such as timing imprecision in a switching control process may lead to a transient overcurrent conditions in one or more of the switching devices 20. This can occur when both switching devices 20 of a given switching pair SP1, SP2, or SP3, normally commanded to opposite conductive states, are simultaneously commanded to turn on and thereby conduct electric current.

[0031] The resulting overcurrent condition is typically transient, lasting on the order of several microseconds (s). In spite of the transiency of the overcurrent condition, however, the local temperature within an affected switching device 20 can rapidly spike to 500 degrees Celsius ( C.) or more. Protective measures may be taken as set forth herein with reference to the remaining Figures to respond to the rapidly manifesting local overtemperature condition, e.g., for short-circuit faults or other overcurrent conditions.

[0032] Referring to FIG. 2, each respective one of the switching devices 20 of FIG. 1 includes a semiconductor power switch 22 that is connected to or monolithically integrated with a temperature sensitive element (TSE) 24. As part of the switching device 20, the TSE 24 is configured such that conduction of an electric current through the TSE 24 is negligible when an actual operating temperature of the TSE 24 is within a predetermined normal operating temperature range of the power switch 22. Electric conduction increases when the actual operating temperature of the power switch 22 exceeds an upper limit of a defined normal operating temperature range of the power switch 22. The current increase through the TSE 24 occurs rapidly, by orders of magnitude, to a level sufficient for quickly turning off the power switch 22. In this manner, use of the TSE 24 protects the power switch 22 from thermal damage during the contemplated overcurrent condition.

[0033] As alluded to above, the present disclosure facilitates a more rapid response when protecting the power switch 22 from local overtemperature conditions, i.e., relative to actively commanded or controller-based solutions such as desaturation. During desaturation, for instance, processing time is required to monitor saturation voltage of the power switch 22 against calibrated voltage thresholds to detect when the power switch 22 is no longer operating in its saturation region, as well as to command affected switches to turn off or performing a reset operation to clear the short-circuit fault. In one or more embodiments, the present passive approach can be used in conjunction with such methods, for example as an added measure of protection before resorting to active methods.

[0034] The TSE 24 of FIG. 2 as envisioned herein is positioned in close proximity to an active area 36 of the power switch 22. Due to this proximity, which may be only a few micrometers (m), heat from the rapidly heated active area 36 will quickly transfer to the TSE 24. In turn, the resulting rapid heating of the TSE 24 will cause the conductive state of the TSE 24 to change from a blocking or non-conducting/OFF state to a conducting/ON state. This thermally-triggered conductive state change of the TSE 24 will cause the power switch 22 to turn off and no longer conduct, thereby protecting the power switch 22 from thermal damage.

[0035] Continuing with this discussion, the power switch 22 may have a normal operating temperature range of about 25 C. to about 200 C. in a representative embodiment. The threshold temperature for triggering a transition to a conductive state of the TSE 44 may therefore be the upper limit of this defined range, the values of which may be expected to vary with the construction of the power switch 22 and TSE 24. Using the above-noted threshold of 200 C. as an illustrative example, therefore, the TSE 24 would conduct a negligible current when the actual operating temperature of the power switch 22 remains close to 25 C., nominally room temperature. However, the TSE 24 would begin to conduct more current as its temperature rises to and above 200 C. Above the upper threshold of 200 C. in keeping with this non-limiting working example, the TSE 24 would conduct a significant amount of electric current, with significant in a practical application being on the order of 10 mA to several hundred mA, e.g., at least 100 mA.

[0036] The power switch 22 in the non-limiting example construction of FIG. 2 is embodied as a metal-oxide semiconductor field-effect transistor (MOSFET), for instance a silicon carbide (SiC) power MOSFET as shown, a trench MOSFET, a superjunction/charge balance MOSFET, etc. Other power switches 22 may be used within the scope of the disclosure, including but not limited to insulated gate bipolar transistors (IGBTs), and therefore the depicted SiC MOSFET implementations are representative and non-limiting of the present teachings.

[0037] As appreciated in the art, MOSFETs include a gate contact 350G, a source contact 360S, and a drain contact 380D. In the exemplary embodiment of FIG. 2, a silicon carbide (SiC) substrate 26 is disposed between the drain contact 380D and the source contact 360S-1 of the power switch 22. An insulating layer 28, e.g., of silicon dioxide (SO2), is disposed between the gate contact 350G and the SiC substrate 26. The SiC substrate 26 is doped, in this exemplary instance with an n-type impurity, in a first SiC substrate region 26A (N+) adjacent the drain terminal 380D.

[0038] A second SiC substrate region 26B (N) (drift region) extends between the first SiC substrate region 26A and the insulating layer 28 below the gate contact 350G. Adjacent the source contact 360S-1, p-type and n-doped regions 30, 32 (P+ and N+) are partially surrounded by a p-type body region (PBody) 34, such that a PN junction is formed between the PBody 34 and the second SiC substrate region 26B. A channel region 35 adjacent the active area 36 is thus formed between each Pbody 34 of the power switch 22 as shown.

[0039] With continued reference to FIG. 2, the TSE 24 in this embodiment is connected to the source contact 360S-1 and the gate contact 350G of the power switch 22 in the latter's exemplary configuration as a SiC power MOSFET. The passively-activated TSE 24 in one or more implementations may include or be embodied as a lateral junction field-effect transistor (JFET) 140. Another source contact 360S-2 that is shared by the lateral JFET 140 and the power switch 22 is connected to the source contact 360S-1 via a conductor 40A, e.g., a wire trace. A similar conductor 40B connects a gate contact 150G of the lateral JFET 140 to the gate contact 350G of the power switch 22 in this embodiment. As appreciated in the art, most of the area of a die implementing the switching device 20 would be occupied by the power switch 22, such that FIG. 2 is not drawn to scale. Rather, the TSE 24 is enlarged to show its internal detail. The effect of implementing the TSE 24 on the on-state resistance or Rdson of the switching device 20 thus remains minimal, as the lateral JFET 140 contributes essentially no conduction absent an overcurrent fault.

[0040] During normal operating conditions of the switching device 20 of FIG. 2, the conductive state of the power switch 22 may be controlled via a driver circuit (Driver) 50. That is, the driver circuit 50 provides a gate-to-source voltage (V.sub.GS) across a gate terminal (T.sub.G) and source terminal (T.sub.S), with a resistor (R.sub.G) connected to the gate terminal (T.sub.G) to represent the internal resistance of the power switch 22 (SiC power MOSFET). The applied gate-to-source voltage causes the power switch 22 to conduct/turn on. A gate voltage signal that is less than a calibrated threshold voltage (Vth), typically 3V to 5V (or 3V to 5V) causes the power switch 22 to not conduct/turn off. Thus, in an exemplary use case in which the power switch 22 is used in a power electronic device such as an inverter circuit 10 of FIG. 1, the driver circuit 50 is used to shape an input (or output) waveform to/from the inverter circuit 10, for instance pulse width modulation, pulse density modulation, or other suitable switching control processes. As this occurs, the TSE 24 does not conduct current, and thus is seen as a slight parasitic loss element.

[0041] When the TSE 24 is embodied as the illustrated lateral JFET 140 as shown in FIG. 2, the lateral JFET 140 includes an N-channel 42 extending between two positively n-doped (N.sup.+) regions 32. A p-doped well region (PWell) 38 is located adjacent to the second SiC substrate region 26B such that the n-doped regions 32 are disposed between the respective gate and source contacts 150G and 360S-2. Under normal operating conditions, i.e., when a temperature of the lateral JFET 140 remains below an upper limit of the normal operating temperature of the power switch 22, an electric current does not flow in the N-channel 42 between the n-doped regions 32. The lateral JFET 140 instead acts in a blocking mode. As appreciated, the concentration of electrons and holes in the constituent semiconductor materials of the lateral JFET 140 increases exponentially with temperature. The depletion region of the lateral JFET is quickly reduced, which has the effect of widening the N-channel 42 and allowing more electric current to flow therethrough.

[0042] Under a concurrent high-voltage/high-current condition indicative of a short circuit fault and other possible electrical faults, however, a high power density must be dissipated as intense heat flowing laterally from the active area 36 of the power switch 22 to the N-channel 42 of the illustrated lateral JFET 140. The lateral JFET 140 responds by heating up within several S. This causes an electric current to conduct a current laterally across the N-channel 42 from the gate contact 150G of the lateral JFET 140 to the source contact 360-2. Because the respective source contacts 360S-1 and 360S-2 are interconnected by the conductor 40A, the gate and source contacts 350G and 360S-1 of the power switch 22 are effectively shorted together, thus causing the power switch 22 to turn off.

[0043] In a possible variation, an optional positively-doped p-type (P.sup.+) electrode 52 contacting the Pwell 38 of the lateral JFET 140 may be used to tune performance of the lateral JFET 140. For example, a driver circuit 500 of FIG. 2 may be used to apply a small negative voltage (V.sup.) to the PWell 38 to affect conductive performance of the PN junction formed between the PWell 38 and the N-channel 42. The lateral JFET 140 of FIG. 2 in one or more embodiments may be configured to conduct an electric current of less than about 1 milliamp (mA), i.e., a negligible current. This occurs when the semiconductor power switch 22 operates in its defined normal operating temperature range. The lateral JFET 140 may be configured to conduct a current of at least about 10 mA to several hundred mA in a characteristic temperature range of the overcurrent event contemplated herein, which would coincide with the power switch 22 operating well above about 200 C. in the above-stated example.

[0044] Referring briefly to FIG. 2A, which illustrates current flow traces I, II, and III across the N-channel 42 of the lateral JFET 140 shown in FIG. 2 on a logarithmic scale for different representative operating temperature curves, i.e., 25 C., 200 C., and 525 C. respectively in a non-limiting implementation. As the respective gate contacts 350G, 150G and source contacts 360S-1 and 360S-2 are connected together as shown in FIG. 2, the gate-to-source voltage of the power switch 22 (V.sub.GS_MOSFET) is equal to the voltage provided to the lateral JFET 140 (V.sub.JFET).

[0045] For an exemplary scenario where V.sub.GS_MOSFET18V, therefore, the lateral JFET 140 conducts negligible current through the normal operating temperature range of the power switch 22, which is about 25 C. to about 200 C. in this non-limiting example. As temperatures rise during a local overtemperature event, the lateral JFET 140 begins to conduct significantly more current across the N-channel 42, thus shorting the gate contact 350G and source contact 360S-1 of the power switch 22. Use of the TSE 24 as a protective switch as contemplated herein therefore enables the TSE 24 to conduct when the power switch 22 is operating well outside of its defined normal operating temperature range, thus forcing the power switch 22 to turn off.

[0046] Referring now to FIG. 3, a switching device 20A may be alternatively constructed using a gated lateral JFET 240. Here, the power switch 22 may be monolithically integrated with the gated lateral JFET 240 as with the embodiment of FIG. 2. The source terminal (T.sub.S) in this implementation is connected to the source contact 360S-1 of the power switch 22. The gate terminal (T.sub.G) is connected to the gate contact 350G. A top gate structure 250G spans the insulator 28 covering the N-channel 42. In one or more implementations, the top gate structure 250G is electrically connected to the source contact 360S-1 of the power switch 22. A drain terminal 280D of the gated lateral JFET 240 is connected to the gate contact 350G of the power switch 22 via a conductor 400B, with a conductor 400A connecting the source contact 360S-1 to the source contact 360S-2 in this embodiment.

[0047] In one or more optional embodiments, an external connection is provided between the top gate structure 250G of the gated lateral JFET 240 and an alternatively connected driver circuit (Driver) 50A. The driver circuit 50A may be configured as with the driver circuit 50 in FIG. 2, as well as to control a potential (V.sup.) to the top gate structure 250G of the gated lateral JFET 240 to achieve a desired gate leakage current through the N-channel 42 during normal operating conditions, i.e., absent a short-circuit condition.

[0048] As shown in FIG. 3A, the switching device 20A of FIG. 3 may be used to enhance current sensitivity with respect to changing temperature, as demonstrated by the relatively concentrated grouping 51 of the temperature traces I, II, and III in contrast to how the same traces are shown in FIG. 2A. Among other attendant benefits, the switching device 20A of FIG. 3 may be relatively easy to manufacture, with its layout enabling placement of the TSE 24 close to the active area 36 of the semiconductor power switch 22. This in turn facilitates thermal energy transfer to the TSE 24 for a more rapid protection response.

[0049] In another alternative switching device 20B as illustrated in FIG. 4, the switching device 20B may include a control circuit 58 configured to adjust a current-to-temperature sensitivity level of the gated lateral JFET 24-0. For instance, the control circuit may include a voltage divider circuit coupled to the sources contacts 360S-1 and 360S-2 and the top gate structure 250G and gate contact 350G. As appreciated in the art, voltage dividers such as the schematically illustrated control circuit 58 of FIG. 3 typically arrange multiple series-connected resistors connected across a voltage source (not shown). The voltage drop across each resistor is proportional to its resistance value. The control circuit 58 may also be constructed as a capacitive divider in one or more embodiments, with a plurality of capacitors used in lieu of resistors to provide a desired reduced output gate-to-source voltage (V.sub.GS_JFET) to the top gate structure 250G and the source contact 360S-2 of the gated lateral JFET 240, e.g., about 0.5V to about 1V. Such an approach provides another control degree of freedom. That is, V.sub.GS_JFET may be controlled with only a portion of the total gate-to-source voltage (V.sub.GS), as represented by boxed area 60 of FIG. 4A. Such an embodiment may be used to maintain a high current sensitivity with respect to temperature and also increase current conduction, thus requiring a smaller die area for implementing the gated lateral JFET 240.

[0050] LAYOUT: A representative layout of the switching device 20 is shown in FIG. 5 for an embodiment in which the TSE 24 is configured as a lateral JFET 140 and the semiconductor power switch 22 is configured as a MOSFET, e.g., an SiC MOFSET. Here, the lateral JFET 140 when monolithically formed with the power switch 22 may be constructed as a continuation of layout stripes for the power MOSFET, either (i) in a transition area between active areas, or (ii) by producing interruptions within the active area. The switching device 20 taken along cut line 1-1 thus corresponds to the lateral JFET 140 illustrated in FIG. 2, with the power switch 22 of FIG. 2 taken along cut line 2-2 and with the lateral JFET 140 positioned adjacent to the power switch 22 from the perspective of FIG. 5. In the FIG. 3 embodiment in which the gated lateral JFET 240 is used, the optional poly-Si top gate structure 250G may be positioned above the PWell 38 as shown.

[0051] FIG. 6A schematically illustrates a die area 62 for a representative switching device 20 as shown in FIGS. 2-4 in which the semiconductor power switch 22 is constructed on the die area with the above-noted stripe layout. As appreciated in the art, the illustrated stripe layout is commonly used when fabricating power MOSFETs and other semiconductor power switches 22. In a stripe layout, the power switches 22 are arranged in a series of parallel stripes. In this case, the lateral JFET 140 described above may be implemented in an adjacent parallel stripe to help ensure proximity to active regions of the power switches 22. FIGS. 6B and 6C likewise use a stripe layout, but instead situate the lateral JFETs 140 along an axis of each power stripe, either at the ends of the power stripes (FIG. 6B) or at the approximate midpoint of each stripe (FIG. 6C). In either case, the lateral JFET 140 is implemented along a same stripe as the power MOSFET. Such an approach may be suggested by the construction of FIG. 5.

[0052] Referring now to FIG. 7, which generally corresponds to the same stripe construction of FIG. 6C, implementations may be contemplated in which the TSE 24 described above is embodied as a temperature-controlled (TC) switch 65 situated between a polysilicon (poly-Si) gate 66 and source contact 360S-1. Here, the active area 36 of the semiconductor power switch 22 is positioned in proximity to the TC switch 65 acting as a PN diode. In such an implementation, the TC switch 65 conducts an electric current in response to elevated local temperature during a short-circuit event to thereby short the poly-Si gate 66 and the source contact 360S-1. The power switch 22 thus turns off as described above.

[0053] In this construction, the poly-Si gate 66 may be encapsulated in an application specific interlayer dielectric oxide 68 and metal pad 69, e.g., aluminum (Al). The TC switch 65 may be connected by conductors 61 extending between the gate 66 and the source contact 360S-1. When a chip experiences rapid localized heating from an electron current during a short-circuit condition, as indicated by arrows HH, the TC switch 65 heats up rapidly by several hundred C. In this case, the TC switch 65 closes to short the gate 66 and source contact 360S-1.

[0054] An arbitrary number of the TC switches 65 may be integrated into a given chip in different embodiments, with dimensions and doping concentrations of the TC switch 65 chosen to obtain turn-on at an application suitable temperature to achieve the desired short-circuit protection. Possible turn-on temperatures within the scope of the disclosure may fall within the range of about 300 C. to about 600 C., or about 400 C. to about 450 C.

[0055] As shown in FIGS. 8A, 8B, and 8C, for instance, the TC switch 65 may be variously implemented as a layer of high-resistive poly-Si material 70 having low levels of n-type impurities (TC switch 65A of FIG. 8A), which is then connected to the poly-Si gate 66 and the source contact 360S-2 as shown in FIG. 7. For instance, the poly-Si gate 66 may be connected to other poly-Si elements formed in the same deposited layer as the poly-Si gate 66, or in other deposited layers. An intrinsic, very lowly-doped poly-Si resistor, i.e., one in which the electrons gain sufficient energy to break free from their atomic bonds (through thermal excitation in this instance) and contribute to conductivity, has a low leakage current at normal operating temperatures. However, thermal generation as experienced during an overcurrent condition causes low resistance as the material becomes intrinsic at higher temperatures. The TC switch 65A thus turns on as a result of this temperature-induced change.

[0056] Alternatively as illustrated in FIG. 8B, the poly-Si gate 66 may be connected to a reverse-biased PN junction 71 formed from adjacent layers of poly-Si n-doped and p-doped layers 72 and 74. Such a PN junction 71 has a very low leakage current at normal temperatures, but loses its blocking capability as the n-layer or p-layer becomes intrinsic and the built-in potential disappears. This causes the TC switch 65B to turn on. Here, the p-doped layer 72 is connected to the source(S) and the n-doped layer 74 is connected to the poly-Si gate 66.

[0057] FIG. 8C and the TC switch 65C for its part illustrates yet another implementation in which a thyristor 75 is constructed from alternating p-doped and n-doped layers 76 and 78 to form a PNPN device. The thyristor 75 is connected between the metal pad 69 (FIG. 7) and the source 360S-1 in this embodiment. The triggering of a thyristor has a strong temperature dependence. Doping concentrations and length of the doped regions selected for implementing the thyristor 75 may be therefore configured to trigger at a suitable turn-on temperature.

[0058] As will be appreciated by those skilled in the art having the benefit of the present teachings, the inverter circuit 10 of FIG. 1 and other power electronic devices may benefit from use of SiC MOSFETs. However, existing SCWT requirements may be challenging to meet using purely active response techniques such as desaturation. Rather than penalizing Rdson as noted above, the solutions described herein allow for tradeoff between Rdson and SCWT by providing a passively-triggered response to local overtemperature conditions in active regions of the semiconductor power switch 22. These and other attendant benefits will be readily appreciated by those of ordinary skill in the art in view of the foregoing disclosure.

[0059] While several modes for carrying out the many aspects of the present teachings have been described in detail, those familiar with the art to which these teachings relate will recognize various alternative aspects for practicing the present teachings that are within the scope of the appended claims. The above description and accompanying drawings are illustrative and exemplary of the entire range of alternative embodiments that an ordinarily skilled artisan would recognize as implied by, structurally and/or functionally equivalent to, or otherwise rendered obvious based upon the included content, and not as limited solely to those explicitly depicted and/or described embodiments. Moreover, the present concepts expressly include combinations and sub-combinations of the described elements and features. The detailed description and the drawings are supportive and descriptive of the present teachings, with the scope of the present teachings defined solely by the claims.