Method of manufacturing a redistribution layer, redistribution layer and integrated circuit including the redistribution layer

Abstract

A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.

Claims

1. A method, comprising manufacturing a redistribution layer for an integrated circuit, the manufacturing including: forming a dielectric layer on an interconnection layer covering the interconnection layer with the dielectric layer; forming a first passivation layer on the dielectric layer covering the dielectric layer with the first passivation layer; forming a spacing layer on the first passivation layer covering the first passivation layer with the spacing layer; forming a trench extending through the spacing layer; forming a barrier layer in the trench and on a surface of the spacing layer; forming a conductive layer in the trench and on the barrier layer covering the barrier layer with the conductive layer; forming a first coating region extending around, being on, and contacting the conductive layer and the barrier layer, the first coating region contacting the surface of the spacing layer; after forming the first coating region, partially etching the spacing layer forming a gap between the first coating region and the first passivation layer, and forming a spacer from the spacing layer physically contacting the barrier layer and physically contacting the first passivation layer; and after forming the gap and the spacer, forming a second coating region being around the first coating region, in the gap, and physically contacting the spacer.

2. The method according to claim 1, wherein: forming the first coating region comprises coating the conductive layer and the barrier layer by electroless deposition of conductive material, and forming the second coating region comprises coating the first coating region by electroless deposition of conductive material.

3. The method according to claim 1, wherein forming the first coating region comprises depositing a layer of nickel.

4. The method according to claim 1, wherein: forming the barrier layer in the trench comprises partially filling the trench with the barrier layer, the barrier layer being a titanium tungsten layer; and forming the conductive layer in the trench and on the barrier layer comprises partially filling the trench with the conductive layer, the conductive layer being a copper layer.

5. The method according to claim 1, wherein the dielectric layer is a silicon dioxide layer and the first passivation layer is a silicon nitride layer.

6. The method according to claim 1, wherein forming the conductive layer in the trench further comprising forming a direct conductive path between the interconnection layer and the conductive layer by depositing conductive material in the trench.

7. The method according to claim 6, further comprising: forming a second passivation layer extending around and on the second coating region; forming an opening in the second passivation layer exposing a surface of the second coating region; and coupling a wire bond to the surface of the second coating region.

8. A method, comprising: manufacturing a redistribution layer for an integrated circuit, the manufacturing including: forming an insulating layer having a first surface and a second surface opposite to the first surface; forming a spacing layer on the second surface of the insulating layer; forming a conductive body on the spacing layer; forming a first coating region around and on the conductive body, contacting the conductive body, and contacting the spacing layer; after forming the first coating region, completely exposing a third surface of the first coating region spaced apart from the second surface of the insulating layer by forming a gap between the third surface of the first coating region and the second surface of the insulating layer, forming the gap includes recessing the spacing layer between the third surface of the first coating region and the second surface of the insulating layer, the third surface directly facing the second surface, the recessing of the spacing layer including: leaving a portion of the spacing layer between a portion of the conductive body and the second surface of the insulating layer; and forming an end surface of the portion of the spacing layer transverse to the second surface and the third surface, and extending from the portion of the conductive body to the second surface of the insulating layer; after recessing the spacing layer, filling the gap completely sealing the first coating region from the insulating layer by forming a second coating region extending around the first coating region, the second coating region covering the end surface of the portion of spacing layer and the third surface of the first coating region.

9. The method according to claim 8, wherein recessing the spacing layer comprises etching the spacing layer with an etchant chemical removing portions of the spacing layer at a higher etch rate than the first coating region and the insulating layer.

10. The method according to claim 9, wherein: the etchant chemical is hydrofluoridic acid; forming the insulating layer further including depositing a dielectric layer of an insulating material on a wafer and a passivation layer of silicon nitride on the dielectric layer; and the spacing layer is chosen between either a silicon dioxide layer and a silicon nitride layer having a higher etching rate in hydrofluoridic acid than the passivation layer.

11. The method according to claim 8, wherein forming the spacing layer further including forming the spacing layer having a thickness ranging from 10-nanometers (nm) to 100-nm.

12. The method according to claim 8, wherein: forming the first coating region further including coating the conductive body by electroless deposition of conductive material, and forming the second coating region further including coating the first coating region by electroless deposition of conductive material.

13. The method according to claim 8, wherein forming the first coating region further including depositing a layer of nickel.

14. The method according to claim 8, wherein forming the conductive body further including: forming a barrier layer of titanium tungsten on the spacing layer; and forming a conductive layer further including forming the conductive layer of a copper material on the barrier layer.

15. The method according to claim 8, wherein manufacturing the redistribution layer further including: forming the insulating layer further including forming the insulating layer on an interconnection layer of a wafer; forming a trench completely through the spacing layer and the insulating layer extending to the interconnection layer; and forming the conductive body further including depositing conductive material in the trench forming a direct conductive path between the interconnection layer and the conductive body.

16. The method according to claim 15, further comprising: forming a passivation layer extending around and being on the second coating region; and forming an opening in the passivation layer exposing a surface of a second coating layer that includes the second coating region, the surface of the second coating layer being configured to be coupled to a wire bonding.

17. A method, comprising: forming a trench extending through a spacing layer at a first surface of a wafer and extending through a passivation layer of the wafer covered by the spacing layer; forming a conductive body in the trench including: forming a conductive barrier layer within the trench, forming the conductive barrier layer including overlapping a portion of the spacing layer at the first surface of the wafer with the conductive barrier layer; and forming a conductive portion on the conductive barrier layer, forming the conductive portion including overlapping the portion of the spacing layer at the first surface of the wafer with the conductive portion; after forming the conductive body, forming a first coating layer covering a plurality of first side surfaces of the conductive body, covering a first end surface of the conductive body transverse to the plurality of first side surfaces, and being on the spacing layer; after forming the first coating layer, partially removing the spacing layer leaving behind the portion of the spacing layer and forming a gap between the first coating region and the passivation layer; after partially removing the spacing layer, forming a second coating region covering a plurality of second side surfaces of the first coating region, covering a second end surface of the first coating region, and sealing the gap.

18. The method of claim 17, wherein partially removing the spacing layer further includes partially etching the spacing layer.

19. The method of claim 17, further comprising wherein forming the conductive barrier layer includes forming the conductive barrier layer with physical vapor deposition (PVD).

20. The method of claim 17, wherein forming the trench further includes: forming the trench extending through a dielectric layer of the wafer covered by the passivation layer; and forming the trench extending to an interconnection layer of the wafer covered by the dielectric layer.

21. The method of claim 20, wherein forming the conductive barrier layer further includes forming the conductive barrier layer on a surface of the interconnection layer exposed by forming the trench.

22. A method, comprising: forming a trench extending through a spacing layer at a first surface of a wafer, extending through a passivation layer of the wafer covered by the spacing layer, extending through a dielectric layer of the wafer covered by the passivation layer, and extending to a surface of an interconnection layer of the wafer covered by the dielectric layer and exposing a portion of the surface of the interconnection layer; forming a conductive body in the trench and on the portion of the surface of the interconnection layer including: forming a conductive barrier layer within the trench, forming the conductive barrier layer including overlapping a portion of the spacing layer at the first surface of the wafer and overlapping the surface of the interconnection layer with the conductive barrier layer; and forming a conductive portion on the conductive barrier layer, forming the conductive portion including overlapping the portion of the spacing layer and overlapping the surface of the interconnection layer with the conductive portion; after forming the conductive body, forming a first coating layer covering a plurality of first side surfaces of the conductive barrier layer, covering a plurality of second side surfaces of the conductive portion, covering a first end surface of the conductive portion transverse to the plurality of first side surfaces and the plurality of second side surfaces, and being on the spacing layer; after forming the first coating layer, partially removing the spacing layer leaving behind the portion of the spacing layer and forming a gap between a surface of the first coating region and a surface of the passivation layer; and after partially removing the spacing layer, forming a second coating region covering a plurality of third side surfaces of the first coating region, covering a second end surface of the first coating region, and sealing off the gap.

23. The method of claim 22, further comprising forming an insulating layer covering a plurality of fourth side surfaces of the second coating layer.

24. The method of claim 22, further comprising: forming an insulating layer covering a plurality of fourth side surfaces of the second coating layer and covering a third end surface of the second coating layer; and forming an opening extending through the insulating layer exposing at least a portion of the third end surface of the second coating layer.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) For a better understanding of the present disclosure, preferred embodiments thereof are now described, purely by way of non-limiting example and with reference to the attached drawings, wherein:

(2) FIG. 1 is a cross-section view of a portion of an integrated circuit including a redistribution layer according to the prior art;

(3) FIG. 2 is a cross-section view of a portion of an integrated circuit including a redistribution layer according to an embodiment of the present disclosure;

(4) FIG. 3 is a cross-section view of another portion of the integrated circuit of FIG. 2, including the portion of FIG. 2;

(5) FIGS. 4A-4I are cross-section views of respective steps of a manufacturing method of the redistribution layer of FIG. 2;

(6) FIG. 5 is a cross-section view of a portion of an integrated circuit including a redistribution layer according to another embodiment of the present disclosure; and

(7) FIGS. 6A-6F are cross-section views of respective steps of a manufacturing method of the redistribution layer of FIG. 5.

DETAILED DESCRIPTION

(8) FIG. 2 shows schematically a cross-section view of a portion of an IC 21 including a redistribution layer 22 according to an embodiment of the present disclosure. In particular, the IC 21 of FIG. 2 is represented in a system of spatial coordinates defined by three axes x, y, z, orthogonal to one another and the cross-section view is taken on an xz plane, defined by the x axis and the z axis.

(9) The IC 21 includes an interconnection layer 23, made of conductive material, such as aluminum or copper. In particular, the interconnection layer 23 is the last metal line of the BEOL of IC 21.

(10) The redistribution layer 22 comprises a dielectric layer 24 extending above the interconnection layer 23 and a first passivation layer 26 extending above the dielectric layer 24. In the following, the term “insulating layer” refers to the stack composed of the dielectric layer 24 and the first passivation layer 26.

(11) In particular, the dielectric layer 24 is made of an insulating material, such as silicon dioxide (SiO.sub.2), and has thickness comprised for instance between 900 nm and 1200 nm.

(12) In particular, the first passivation layer 26 is made of an insulating material, such as silicon nitride (Si.sub.3N.sub.4), and has thickness comprised for instance between 500 nm and 650 nm. The first passivation layer 26 is delimited by a top surface 26a and a bottom surface 26b, the bottom surface 26b being in contact with the dielectric layer 24.

(13) The redistribution layer 22 further comprises a barrier region 28. A first portion of the barrier region 28 extends above the top surface 26a of the first passivation layer 26; a second portion of the barrier region 28, in contact with the first portion, extends below the top surface 26a of the first passivation layer 26, and across the whole depth of the first passivation layer 26 and of the dielectric layer 24, so as to be in contact with the interconnection layer 23.

(14) The redistribution layer 22 further comprises a conductive region 30, extending on top of the barrier region 28. In particular, in a top view of the IC 21, not shown in the figures, the conductive region 30 is extending only inside the area defined by the barrier region 28. As a consequence, the conductive region 30 is not in contact with the first passivation layer 26. In the following, the term “conductive body” refers to the stack composed of the barrier region 28 and the conductive region 30.

(15) Moreover, the thickness of the barrier region 28 is lower than the combined thickness of the dielectric layer 24 and the first passivation layer 26. As a consequence, a portion of the conductive region 30 extends below the top surface 26a of the first passivation layer 26. In other words, the barrier region 28 and the conductive region 30 form a via through the dielectric layer 24 and the first passivation layer 26, providing a conductive path from the interconnection layer 23 to the top surface 26a of the first passivation layer 26, extending further above the top surface 26a of the first passivation layer 26.

(16) In particular, the barrier region 28 is made of conductive material, such as titanium (Ti), or titanium-tungsten (TiW), or titanium nitride (TiN), and has thickness comprised for instance between 270 nm and 330 nm.

(17) In particular, the conductive region 30 is made of conductive material, such as copper (Cu), and has thickness comprised for instance between 8 μm and 12 μm.

(18) The redistribution layer 22 further comprises a first coating region 32, extending above the conductive region 30 and around the conductive region 30, in correspondence of sidewalls of the portion of the conductive region 30 above the top surface 26a of the first passivation layer 26.

(19) In particular, the first coating region 32 is made of conductive material, such as nickel (Ni), and has thickness comprised for instance between 1 μm and 1.8 μm.

(20) According to an aspect of the present disclosure, the first coating region 32 is not in contact with the first passivation layer 26. In particular, the portion of the first coating region 32 extending around the sidewalls of the conductive region 30 has a surface 32a directly facing the top surface 26a of the first passivation layer 26 and substantially parallel to the top surface 26a of the first passivation layer 26, at a distance H.sub.gap from the top surface 26a of the first passivation layer 26, said distance being comprised for instance between 10 nm and 50 nm (in particular, 25 nm) when measured along the z axis.

(21) The redistribution layer 22 further comprises a second coating region 34, extending above the first passivation layer 26, around the first coating region 32 and above the first coating region 32. The second coating region 34 is in contact with the first passivation layer 26 and the first coating region 32. In other words, the second coating region 34 completely covers the first coating region 32.

(22) In particular, the second coating region 34 is made of conductive material, such as palladium (Pd), and has thickness comprised for instance between 0.2 μm and 0.5 μm.

(23) According to an aspect of the present disclosure, the second coating region 34 extends between the first passivation layer 26 and the first coating region 32, filling a gap having height H.sub.gap between the first passivation region 26 and the first coating region 32. In other words, the second coating region 34 completely seals the first coating region 32. As a consequence, differently from the case of the redistribution layer 2 of FIG. 1 according to the prior art, the first coating region 32 is not exposed to environmental conditions, preventing the risk of corrosions. Therefore, the redistribution layer 22 of FIG. 2 according to the present embodiment has an improved reliability with respect to the prior art, especially in conditions of high temperature and high moisture rate.

(24) The redistribution layer 22 further comprises a second passivation layer 36, extending above the first passivation layer 26 and around the second coating region 34. In particular, the second passivation layer 36 is made of an insulating material, such as polyimide, PbO, epoxy, etc.

(25) FIG. 3 shows schematically a cross-section view of another portion of the IC 21, including the portion of FIG. 2, corresponding to the area inside the dashed lines in FIG. 3. Elements already shown in the view of FIG. 2 are designated by the same reference numerals and are not further described.

(26) FIG. 3 shows that the barrier region 28, the conductive region 30, the first coating region 32, and the second coating region 34 are respectively part of a barrier layer 38, a conductive layer 40, a first coating layer 42 and a second coating layer 44. The second passivation layer 36 extends above the second coating layer 44. Moreover, the second passivation layer 36 may include an opening 46 that partially exposes a contact 47, in order to allow a wire bonding by means of a wire 48, for instance made of copper. The contact 47 is formed by contact portions of the barrier layer 38, conductive layer 40, first coating layer 42, and second coating layer 44, and the wire 48 is connected to the contact portion of the second coating layer 44 by a conductive bond 49.

(27) As is clear from FIG. 3, depending on the routing layout of the interconnection layers and the redistribution layer 22 of the IC 21, a cross-section of the IC 21 may include areas wherein the barrier layer 38 and the conductive layer 40 do not form a via through the first passivation layer 26 and the dielectric layer 24 to reach the interconnection layer 23. In any case, there is always a gap having height H.sub.gap between the first coating layer 42 and the first passivation layer 26, said gap being filled by the second coating layer 44.

(28) Moreover, the IC 21 comprises further metal interconnection layers, insulating layers and vias formed in the BEOL extending below the interconnection layer 23 and collectively designated with the reference numeral 50. In addition, the IC 21 includes a semiconductor substrate 51 in which are formed circuit elements, such as transistors, diodes, resistors and capacitors.

(29) FIGS. 4A-4I show schematically a cross-section view of steps of a method of manufacturing a redistribution layer according to an embodiment of the present disclosure; in particular, the method of FIGS. 4A-4I is a method of manufacturing the redistribution layer 22 of FIG. 2. The redistribution layer is represented in a system of spatial coordinates defined by three axes x, y, z, orthogonal to one another and the cross-section view is taken on an xz plane, defined by the x axis and the z axis.

(30) With reference to FIG. 4A, there is provided a wafer 60, including an interconnection layer 63. In particular, the interconnection layer 63 is the outermost metallization layer of the back end of line of an integrated circuit. The lower layers of the integrated circuit, such as the other metallization layers 50 and the semiconductor substrate 51 of the wafer 60, are not shown in FIGS. 4A-4I.

(31) A dielectric layer 64 is formed above the interconnection layer 63. In particular, the dielectric layer 64 is made of an insulating material, such as silicon dioxide (SiO.sub.2), and has thickness comprised for instance between 900 nm and 1200 nm.

(32) A first passivation layer 66 is formed above the dielectric layer 64. In particular, the first passivation layer 66 is made of an insulating material, such as silicon nitride (Si.sub.3N.sub.4), and has thickness comprised for instance between 500 nm and 650 nm. In the following, the term “insulating layer” refers to the stack composed of the dielectric layer 64 and the first passivation layer 66.

(33) Then, FIG. 4B, a trench 67 is formed through the first passivation layer 66 and the dielectric layer 64, up to exposing a surface of the interconnection layer 63. For instance, the trench 67 is formed by convenient photolithography and dry etching steps of a known type, applied in correspondence of the exposed surface of the first passivation layer 66.

(34) Then, FIG. 4C, a barrier layer 68 is formed above the first passivation layer 66, for instance by physical vapor deposition (PVD). The barrier layer 68 partially fills the trench 67, covering the previously exposed sidewalls of the dielectric layer 64 and the first passivation layer 66 and the previously exposed surface of the interconnection layer 63.

(35) In particular, the barrier layer 68 is made of conductive material, such as titanium (Ti), or titanium-tungsten (TiW), or titanium nitride (TiN). Moreover, the thickness of the barrier layer 68 is lower than the combined thickness of the dielectric layer 64 and the first passivation layer 66, and in particular is comprised for instance between 270 nm and 330 nm. Then, a seed layer 69 is formed above the barrier layer 68, partially filling the trench 67. For instance, the seed layer 69 is deposited by PVD.

(36) In particular, the seed layer 69 is made of conductive material, such as copper (Cu), and has thickness comprised for instance between 180 nm and 220 nm, such that the trench 67 is only partially filled by the seed layer 69.

(37) Then, FIG. 4D, a photolithography mask 70′ is applied at the exposed surface of the seed layer 69. In particular, the layout of the photolithography mask 70′ is designed considering that openings in the mask define areas in which a layer will be formed in a following step of the manufacturing method.

(38) In particular, FIG. 4D shows an opening 70″ of the photolithography mask 70′, the opening 70″ being centered on the partially filled trench 67 so that the trench 67 is not covered by the photolithography mask 70′.

(39) Then, FIG. 4E, a conductive layer 70 is formed above the portions of the seed layer 69 not covered by the photolithography mask 70′. The thickness of the conductive layer 70 is high enough to completely fill the trench 67 and partially fill the opening 70″ of the photolithography mask 70′.

(40) In particular, the conductive layer 70 is made of the same conductive material of the seed layer 69, such as copper (Cu), and has thickness comprised for instance between 8 μm and 12 μm.

(41) In particular, the conductive layer 70 is formed by electrodeposition. Then, the photolithography mask 70′ is removed by a wet removal process, exposing portions of the seed layer 69 not covered by the conductive layer 70.

(42) Then, FIG. 4F, said exposed portions of the seed layer 69, not covered by the conductive layer 70, are removed, for instance by wet etching, up to exposing the portions of the barrier layer 68 underneath them. Thus, the remaining portions of the seed layer 69, covered by the conductive layer 70, form, together with the conductive layer 70, the conductive region 30 of the redistribution layer 22 of FIG. 2.

(43) Then, the exposed portions of the barrier layer 68 are removed, for instance by wet etching, up to exposing the portions of the first passivation layer 66 underneath, without affecting the portions of the barrier layer 68 below the conductive layer 70, for instance by employing standard photolithography techniques. As a consequence, the barrier region 28 of the redistribution layer 22 of FIG. 2 is formed.

(44) Then, FIG. 4G, a first coating layer 72 is formed by electroless deposition, in correspondence of the exposed surfaces of the barrier layer 68 and the conductive layer 70. Thus, the first coating layer 72 completely covers the conductive layer 70 and the barrier layer 68, and is in contact with the partially exposed surface of the first passivation layer 66, designated with the reference numeral 66a. In particular, the first coating layer 72 is in contact with the exposed surface 66a of the first passivation layer 66 in correspondence of a bottom surface 72a of the first coating layer 72.

(45) In particular, the first coating layer 72 is made of conductive material, such as nickel (Ni), and has thickness comprised for instance between 1 μm and 1.8 μm.

(46) Then, FIG. 4H, a thermal treatment is applied to the wafer 60 in order to create a gap 73 between said surface 66a of the first passivation layer 66 and the bottom surface of the first coating layer 72. In particular, the gap 73 has the height H.sub.gap in the range 10-50 nm.

(47) According to an aspect of the present disclosure, the thermal treatment comprises a first step of increasing the temperature of the wafer 60 from room temperature to a high temperature. Room temperature is comprised for instance between 20° C. and 25° C.; the high temperature is comprised for instance between 245° C. and 255° C. In particular, the increase in temperature occurs during a first time interval, comprised for instance between 10 s and 60 s.

(48) Then, in a second step, following the first step of the thermal treatment, the wafer is kept at the high temperature for a second time interval comprised for instance between 30 s and 180 s.

(49) Then, in a third step, following the second step of the thermal treatment, the temperature of the wafer 60 is decreased from the high temperature to room temperature over a third time interval, for example, lasting no more than 180 s.

(50) In particular, while applying the thermal treatment, the wafer 60 is kept in a nitrogen (N.sub.2) atmosphere at a pressure comprised between 1.0 and 5.0 Torr.

(51) The Applicant verified that by applying to the wafer 60 the thermal treatment described above, some mechanical properties of the barrier layer 68, of the conductive layer 70 and of the first coating layer 72 can be conveniently modified. In particular, the coefficient of thermal expansion and the Young modulus are modified with the thermal treatment, and the residual stress of said layers is modified, resulting, at the end of the thermal treatment, in the formation of the gap 73.

(52) Then, FIG. 4I, a second coating layer 74 is formed by electroless deposition, in correspondence of the exposed surfaces of the first coating layer 72. In particular, the second coating layer 74 grows starting from the first coating layer 72, extending above the first coating layer 72, around the sidewalls of the first coating layer 72, and inside the gap between the first coating layer 72 and the surface 66a of the first passivation layer 66. Thus, the second coating layer 74 completely seals the first coating layer 72 and the barrier layer 68, and is in contact with the surface 66a of the first passivation layer 66. As a consequence, the first coating layer 72 is not exposed to the environment.

(53) In particular, the second coating layer 74 is made of conductive material, such as palladium (Pd), and has thickness comprised for instance between 0.2 μm and 0.5 μm.

(54) Then, a second passivation layer is formed above the first passivation layer 26 and around the second coating region 94. In particular, the second passivation layer is made of an insulating material, such as polyimide. Thus, the redistribution layer 22 of FIG. 2 is obtained.

(55) The Applicant verified that a possible issue of the redistribution layer 22 of FIG. 2 consists in the risk of forming cracks in the first passivation layer 26 after applying the thermal treatment to the wafer 60, depending on the mechanical properties of the material used for the first passivation layer 26.

(56) FIG. 5 shows schematically a cross-section view of a portion of an IC 81 including a redistribution layer 82 according to another embodiment of the present disclosure; elements in common with the IC 21 and the redistribution layer 22 of FIG. 2 are designated by the same reference numerals and not further described.

(57) The redistribution layer 82 differs from the redistribution layer 22 of FIG. 2 for the presence of spacers 86. In particular, the redistribution layer 82 comprises spacers 86 extending above and in contact with the top surface 26a of the first passivation layer 26.

(58) In particular, the spacers 86 are of insulating material, such as silicon dioxide (SiO.sub.2) or silicon nitride (Si.sub.3N.sub.4), and have a thickness H.sub.gap2 comprised for instance between 10 nm and 100 nm (in particular, 25 nm).

(59) The redistribution layer 82 further comprises a barrier region 88, extending above the spacers 86 and across the whole depth of the first passivation layer 26 and of the dielectric layer 24, so as to be in contact with the interconnection layer 23.

(60) The redistribution layer 82 further comprises a conductive region 90, extending on top of the barrier region 88. In particular, in a top view of the IC 81, not shown in the figures, the conductive region 90 is extending only inside the area defined by the barrier region 88. As a consequence, the conductive region 90 is not in contact with the first passivation layer 26. In the following, the term “conductive body” refers to the stack composed of the barrier region 88 and the conductive region 90.

(61) Moreover, the thickness of the barrier region 88 is lower than the combined thickness of the dielectric layer 24 and of the first passivation layer 26. As a consequence, a part of the conductive region 90 extends below the top surface 26a of the first passivation layer 26. In other words, the barrier region 88 and the conductive region 90 form a via through the dielectric layer 24 and the first passivation layer 26, providing a conductive path from the interconnection layer 23 to the top surface 26a of the first passivation layer 26.

(62) In particular, the barrier region 88 is made of conductive material, such as titanium (Ti), or titanium-tungsten (TiW), or titanium nitride (TiN), and has thickness comprised for instance between 270 nm and 330 nm.

(63) In particular, the conductive region 90 is made of conductive material, such as copper (Cu), and has thickness comprised for instance between 8 μm and 12 μm.

(64) The redistribution layer 82 further comprises a first coating region 92, extending above the conductive region 90 and around the conductive region 90, in correspondence of sidewalls of the portion of the conductive region 90 above the top surface 26a of the first passivation layer 26. In other words, the first coating region 92 covers the surface of the conductive region 90 not already covered by the barrier region 88.

(65) In particular, the first coating region 92 is made of conductive material, such as nickel (Ni), and has thickness comprised for instance between 1 μm and 1.8 μm.

(66) According to an aspect of the present disclosure, the first coating region 92 is not in contact with the first passivation layer 26. In particular, the portion of the first coating region 92 extending around the sidewalls of the conductive region 90 has a surface 92a directly facing the top surface 26a of the first passivation layer 26 and substantially parallel to the top surface 26a of the first passivation layer 26, at a distance H.sub.gap2 from the top surface 26a of the first passivation layer 26 being equivalent to the height H.sub.gap2 of the spacers 86, said distance H.sub.gap2 being measured along the z axis.

(67) The redistribution layer 22 further comprises a second coating region 94, extending above the first passivation layer 26, around the first coating region 92 and above the first coating region 92. The second coating region 94 is in contact with the first passivation layer 26 and the first coating region 92. In other words, the second coating region 94 completely covers the first coating region 92.

(68) In particular, the second coating region 94 is made of conductive material, such as palladium (Pd), and has thickness comprised for instance between 0.2 μm and 0.5 μm.

(69) According to an aspect of the present disclosure, the second coating region 94 extends between the first passivation layer 26 and the first coating region 92, filling a gap between the first passivation region 26 and the first coating region 92. In other words, the second coating region 94 completely seals the first coating region 92. As a consequence, as in the case of the redistribution layer 22 of FIG. 2, the first coating region 92 is not exposed to environmental conditions, thus preventing the risk of corrosions. Therefore, the redistribution layer 82 according to the present embodiment has an improved reliability with respect to the prior art, especially in conditions of high temperature and high moisture rate.

(70) FIGS. 6A-6F show schematically a cross-section view of steps of a method of manufacturing a redistribution layer according to an embodiment of the present disclosure; in particular, the method of FIGS. 6A-6F is a method of manufacturing the redistribution layer 82 of FIG. 5. The redistribution layer is represented in a system of spatial coordinates defined by three axes x, y, z, orthogonal to one another and the cross-section view is taken on an xz plane, defined by the x axis and the z axis.

(71) With reference to FIG. 6A, there is provided a wafer 100, including an interconnection layer 103. In particular, the interconnection layer 103 is the outermost metallization layer of the back end of line of an integrated circuit. The lower layers of the integrated circuit are not shown in FIGS. 6A-6F.

(72) A dielectric layer 104 is formed above the interconnection layer 103. In particular, the dielectric layer 104 is made of an insulating material, such as silicon dioxide (SiO.sub.2), and has thickness comprised for instance between 900 nm and 1200 nm.

(73) A first passivation layer 106 is formed above the dielectric layer 104. In particular, the first passivation layer 106 is made of an insulating material, such as silicon nitride (Si.sub.3N.sub.4), and has thickness comprised for instance between 500 nm and 650 nm. In the following, it will be used the term “insulating layer” to refer to the stack composed of the dielectric layer 104 and the first passivation layer 106.

(74) A spacing layer 105 is formed above the first passivation layer 106. In particular, the spacing layer 105 is made of an insulating material, such as silicon dioxide (SiO.sub.2) or silicon nitride (Si.sub.3N.sub.4).

(75) According to an aspect of the present disclosure, the spacing layer 105 is employed as a sacrificial layer, being partially etched in a following step of the method of manufacturing. For this reason, preferably, the spacing layer 105 has a high selectivity in terms of etching with respect to the first passivation layer 106. As a consequence, the choice of the material employed for the spacing layer 105 depends on the material employed for the first passivation layer 106. For instance, if the first passivation layer 106 is made of Si.sub.3N.sub.4, the spacing layer 105 is preferably made of SiO.sub.2 or of a high etch-rate Si.sub.3N.sub.4. As is known, a higher etch-rate Si.sub.3N.sub.4 can be obtained by depositing the spacing layer 105 at a lower temperature than the one employed for depositing the first passivation layer 104. In particular, the spacing layer 105 has the thickness H.sub.gap2.

(76) Then, FIG. 6B, a trench 107 is formed through the dielectric layer 104 and the first passivation layer 106, up to exposing a surface of the interconnection layer 103. For instance, the trench 107 is formed by convenient photolithography and dry etching steps of a known type, in correspondence of the exposed surface of the spacing layer 105.

(77) Then, a barrier layer 108 is formed above the spacing layer 105, for instance by PVD. The barrier layer 108 partially fills the trench 107, covering the previously exposed sidewalls of the spacing layer 105, of the first passivation layer 106 and of the dielectric layer 104, and covering the previously exposed surface of the interconnection layer 103.

(78) In particular, the barrier layer 108 is made of conductive material, such as titanium (Ti), titanium-tungsten (TiW), or titanium nitride TiN). Moreover, the thickness of the barrier layer 108 is lower than the combined thickness of the dielectric layer 104, the first passivation layer 106 and the spacing layer 105, and in particular is comprised for instance between 270 nm and 330 nm. Then, a seed layer 109 is formed above the barrier layer 108, partially filling the trench 107. For instance, the seed layer 109 is deposited by PVD.

(79) In particular, the seed layer 109 is made of conductive material, such as copper (Cu), and has thickness comprised for instance between 180 nm and 220 nm, such that the trench 107 is only partially filled by the seed layer 109.

(80) Then, a photolithography mask (not shown in the figures) is applied at the exposed surface of the seed layer 109. In particular, the layout of the photolithography mask is designed considering that openings in the mask define areas in which a layer will be formed in a following step of the manufacturing method.

(81) In particular, the photolithography mask presents an opening in correspondence of the partially filled trench 107.

(82) Then, FIG. 6C, a conductive layer 110 is formed above the portions of the seed layer 109 not covered by the photolithography mask. In particular, the thickness of the conductive layer 110 is high enough to completely fill the trench 107.

(83) In particular, the conductive layer 110 is made of the same conductive material of the seed layer 109, such as copper (Cu), and has thickness comprised for instance between 8 μm and 12 μm.

(84) In particular, the conductive layer 110 is formed by electrodeposition. Then, the photolithography mask is removed by a wet removal process, exposing portions of the seed layer 109 not covered by the conductive layer 110.

(85) Then, said exposed portions of the seed layer 109, not covered by the conductive layer 110, are removed, for instance by wet etching, up to exposing the portions of the barrier layer 108 underneath. Thus, the remaining portions of the seed layer 109, covered by the conductive layer 110, form, together with the conductive layer 110, the conductive region 90 of the redistribution layer 82 of FIG. 5.

(86) Then, the exposed portions of the barrier layer 108 are removed, for instance by wet etching, up to exposing the portions of the spacing layer 105 underneath, without affecting the portions of the barrier layer 108 below the conductive layer 110. As a consequence, the barrier region 88 of the redistribution layer 82 of FIG. 5 is formed.

(87) Then, FIG. 6D, a first coating layer 112 is formed by electroless deposition, in correspondence of the exposed surfaces of the barrier layer 108 and the conductive layer 110. Thus, the first coating layer 112 completely covers the conductive layer 110 and the barrier layer 108, and is in contact with the partially exposed surface of the spacing layer 105. In particular, the first coating layer 112 is in contact with the spacing layer 105 in correspondence of a bottom surface 112a of the first coating layer 112.

(88) In particular, the first coating layer 112 is made of conductive material, such as nickel (Ni), and has thickness comprised for instance between 1 μm and 1.8 μm.

(89) Then, FIG. 6E, the spacing layer 105 is partially etched in order to create a gap 113 between a top surface 106a of the first passivation layer 106 and the first coating region 112, the top surface 106a being in contact with remaining portions of the spacing layer 105. In particular, the gap 113 has the height H.sub.gap2 in the range 10-100 nm.

(90) In particular, the spacing layer 105 is etched by wet etching, using chemicals that remove the spacing layer 105 selectively with respect to the first coating layer 112, the barrier layer 108 and the first passivation layer 106.

(91) For instance, the wafer 100 can be immersed in a hydrofluoric (HF) acid bath on in a buffered hydrofluoric (BHF) batch if the spacing layer 105 is made of silicon dioxide or a high etch rate silicon nitride, so that the spacing layer 105 is etched at a faster rate than the surrounding layers.

(92) In particular, the etching step proceeds at least until the gap 113 is completely formed, so that the remaining portions of the spacing layer 105 do not extend between the first passivation layer 106 and the first coating layer 112. In other words, at the end of the etching step of FIG. 6E, the bottom surface 112a of the first coating layer 112, directly facing the top surface 106a of the first passivation layer 106, is not in direct contact with the spacing layer 105.

(93) Then, FIG. 6F, a second coating layer 114 is formed by electroless deposition, in correspondence of the exposed surfaces of the first coating layer 112. In particular, the second coating layer 114 grows starting from said surfaces of the first coating layer 112, extending above the first coating layer 112, around the sidewalls of the first coating layer 112, and inside the gap between the first coating layer 112 and the top surface 106a of the first passivation layer 106. Thus, the second coating layer 114 completely seals the first coating layer 112, and is in contact with the top surface 106a of the first passivation layer 106. As a consequence, the first coating layer 112 is not exposed to the environment.

(94) In particular, the second coating layer 114 is made of conductive material, such as palladium (Pd), and has thickness comprised for instance between 0.2 μm and 0.5 μm.

(95) Then, a second passivation layer is formed above the first passivation layer 106 and around the second coating region 114. In particular, the second passivation layer is made of an insulating material, such as polyimide. Thus, the redistribution layer 82 of FIG. 5 is obtained.

(96) The advantages of the disclosure described previously, according to the various embodiments, emerge clearly from the foregoing description.

(97) In particular, since the first coating region is completely sealed by the second coating region, it is possible to use materials for the first coating region that are subject to corrosion when exposed to the environment, without compromising the reliability of the redistribution layer.

(98) The full sealing of the conductive material can also improve the electromigration performances of the device.

(99) Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present disclosure.

(100) The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.