Abstract
An apparatus for measuring a gate leakage current of a MOSFET. The apparatus includes a current mirror adapted to be connected to a gate of a MOSFET, a gate driver adapted to generate a driving signal for the MOSFET, and a sensing resistor connected to the current mirror. An input current path of the current mirror is adapted to receive a gate leakage current of the MOSFET. The current mirror provides a high sensitivity of the measurement because the voltage across the current mirror is nearly constant, which therefore caters for different situations no matter if the gate leakage current is high or low.
Claims
1. An apparatus for measuring a gate leakage current of a MOSFET, comprising: a) a current mirror adapted to be connected to a gate of a MOSFET; an input current path of the current mirror adapted to receive a gate leakage current of the MOSFET; b) a gate driver adapted to generate a driving signal for the MOSFET; and c) a sensing resistor connected to the current mirror; the sensing resistor being located on an output current path of the current mirror.
2. The apparatus of claim 1, further comprises a turn-on resistor and a turn-off resistor, both of which are adapted to be connected to the gate of the MOSFET.
3. The apparatus of claim 2, wherein the turn-on resistor is located on the input current path of the current mirror; the turn-off resistor having one end adapted to be connected to the MOSFET, and another end connected to the gate driver.
4. The apparatus of claim 1, wherein the current mirror comprises a first transistor and a second transistor having their base connected together; a collector of the first transistor adapted to be connected to the gate of the MOSFET; a collector of the second transistor connected to the sensing resistor.
5. The apparatus of claim 4, wherein the collector of the first transistor is connected directly to the base of thereof; the apparatus further comprising a diode that is connected between the collector and the base of the second transistor.
6. The apparatus of claim 4, wherein an emitter of the first transistor and an emitter of the second transistor are connected directly to the gate driver.
7. The apparatus of claim 1, further comprises a bypass switch connected in parallel to the current mirror; the bypass switch adapted to bypass the current mirror during a turn-on process of the MOSFET.
8. The apparatus of claim 1, wherein the bypass switch comprises a third transistor; the third transistor located on a current path from the gate driver to the MOSFET.
9. The apparatus of claim 8, wherein an emitter of the third transistor is connected to the gate driver; a collector of the third transistor adapted to connect to the MOSFET; a base of the third transistor connected to the gate driver through a RC circuit.
10. The apparatus of claim 4, further comprises a discharging circuit connected to the current mirror; the discharging circuit adapted to shorten a timer period required for the first transistor and the second transistor to transit from a saturation mode to a linear mode.
11. The apparatus of claim 10, wherein the discharging circuit comprises a comparator which has a first input connected to a reference voltage and a second input connected to the sensing resistor, a fourth transistor having a base connected an output of the comparator; a fourth resistor adapted to be connected between a collector of the fourth transistor and the gate of the MOSFET; and a third resistor connected between the base of the fourth transistor and a collector of the first transistor.
12. The apparatus of claim 11, further comprises a diode connected between the base and the collector of the fourth transistor.
13. The apparatus of claim 1, wherein one end of the sensing resistor is connected to the current mirror, and another end of the of the sensing resistor is connected to a source of the MOSFET.
Description
BRIEF DESCRIPTION OF FIGURES
[0022] The foregoing and further features of the present invention will be apparent from the following description of preferred embodiments which are provided by way of example only in connection with the accompanying figures, of which:
[0023] FIG. 1 shows a comparison of measured gate-source leakage current I.sub.gss of eight devices before and after undergoing 4000 cycles of short-circuit-current (SC) stress.
[0024] FIG. 2 shows an exemplary gate-driving circuit for a MOSFET.
[0025] FIG. 3a shows experimental results of the output of a MOSFET driver, vg, gate-source voltage, v.sub.gs, and gate current, i.sub.g for a brand new SiC MOSFET.
[0026] FIG. 3b is an enlarged view of steady-state waveforms as marked by the dash-lined block in FIG. 3a.
[0027] FIG. 3c shows experimental results of the output of a MOSFET driver, vg, gate-source voltage, v.sub.gs, and gate current, i.sub.g, after the SiC MOSFET of FIG. 3a has been aged for 4000 power cycles.
[0028] FIG. 3d is an enlarged view of steady-state waveforms as marked by the dash-lined block in FIG. 3c.
[0029] FIG. 4 shows a simplified circuit structure of an apparatus for measuring gate-leakage current according to one embodiment of the invention.
[0030] FIG. 5 shows a complete circuit structure an apparatus for measuring gate-leakage current according to another embodiment of the invention.
[0031] FIG. 6a shows the waveforms of v.sub.gs, v.sub.s and i.sub.g when R.sub.gss equals to , in a simulation of the circuit in FIG. 5.
[0032] FIG. 6b shows the waveforms of v.sub.gs, v.sub.s and i.sub.g when R.sub.gss equals to 300 k in the simulation.
[0033] FIG. 6c shows the waveforms of v.sub.gs, v.sub.s and i.sub.g when R.sub.gss equals to 200 k in the simulation.
[0034] FIG. 6d shows the waveforms of v.sub.gs, v.sub.s and i.sub.g when R.sub.gss equals to 150 k in the simulation.
[0035] FIG. 6e shows the waveforms of v.sub.gs, v.sub.s and i.sub.g when R.sub.gss equals to 100 k in the simulation.
[0036] FIG. 6f shows the waveforms of v.sub.gs, v.sub.s and i.sub.g when R.sub.gss equals to 47 k in the simulation.
[0037] FIG. 6g shows the waveforms of v.sub.gs, v.sub.s and i.sub.g when R.sub.gss equals to 15 k in the simulation.
[0038] FIG. 6h shows the waveforms of v.sub.gs, v.sub.s and i.sub.g when R.sub.gss equals to 10 k in the simulation.
[0039] FIG. 6i shows the waveforms of v.sub.gs, v.sub.s and i.sub.g when R.sub.gss equals to 4.7 k in the simulation.
[0040] FIG. 7 shows the schematic diagram of a test circuit for testing the performance of various circuits for measuring gate leakage current of a SiC MOSFET, according to an embodiment of the invention.
[0041] FIG. 8a shows one gate driving circuit used for comparison in the experimental setup.
[0042] FIG. 8b shows another gate driving circuit used for comparison in the experimental setup.
[0043] FIG. 9a shows measured waveforms of the drain-source voltage, v.sub.ds, gate-source voltage, v.sub.gs, output voltage of the gate driver, v.sub.g, and drain current, i.sub.d, upon turning on the SiC MOSFET for the circuit in FIG. 5 in the experiment.
[0044] FIG. 9b shows measured waveforms of the drain-source voltage, v.sub.ds, gate-source voltage, v.sub.gs, output voltage of the gate driver, v.sub.g, and drain current, i.sub.d, upon turning on the SiC MOSFET for the circuit in FIG. 8a in the experiment.
[0045] FIG. 9c shows measured waveforms of the drain-source voltage, v.sub.ds, gate-source voltage, v.sub.gs, output voltage of the gate driver, v.sub.g, and drain current, i.sub.d, upon turning on the SiC MOSFET for the circuit in FIG. 8b in the experiment.
[0046] FIG. 10a shows measured waveforms of the drain-source voltage, v.sub.ds, gate-source voltage, v.sub.gs, output voltage of the gate driver, v.sub.g, and drain current, i.sub.d, upon turning off the SiC MOSFET for the circuit in FIG. 5 in the experiment.
[0047] FIG. 10b shows measured waveforms of the drain-source voltage, v.sub.ds, gate-source voltage, v.sub.gs, output voltage of the gate driver, v.sub.g, and drain current, i.sub.d, upon turning off the SiC MOSFET for the circuit in FIG. 8a in the experiment.
[0048] FIG. 10c shows measured waveforms of the drain-source voltage, v.sub.ds, gate-source voltage, v.sub.gs, output voltage of the gate driver, v.sub.g, and drain current, i.sub.d, upon turning off the SiC MOSFET for the circuit in FIG. 8b in the experiment.
[0049] FIG. 11a shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.5, when R.sub.gss equals to , in a simulation of the circuit in FIG. 5.
[0050] FIG. 11b shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.5, when R.sub.gss equals to 300 k in the simulation.
[0051] FIG. 11c shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.5, when R.sub.gss equals to 200 k in the simulation.
[0052] FIG. 11d shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.5, when R.sub.gss equals to 150 k in the simulation.
[0053] FIG. 11e shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.5, when R.sub.gss equals to 100 k in the simulation.
[0054] FIG. 11f shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.5, when R.sub.gss equals to 47 k in the simulation.
[0055] FIG. 11g shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.5, when R.sub.gss equals to 15 k in the simulation.
[0056] FIG. 11h shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.5, when R.sub.gss equals to 10 k in the simulation.
[0057] FIG. 11i shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.5, when R.sub.gss equals to 4.7 k in the simulation.
[0058] FIG. 12a shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.2, when R.sub.gss equals to , in a simulation of the circuit in FIG. 5.
[0059] FIG. 12b shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.2, when R.sub.gss equals to 300 k in the simulation.
[0060] FIG. 12c shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.2, when R.sub.gss equals to 200 k in the simulation.
[0061] FIG. 12d shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.2, when R.sub.gss equals to 150 k in the simulation.
[0062] FIG. 12e shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.2, when R.sub.gss equals to 100 k in the simulation.
[0063] FIG. 12f shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.2, when R.sub.gss equals to 47 k in the simulation.
[0064] FIG. 12g shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.2, when R.sub.gss equals to 15 k in the simulation.
[0065] FIG. 12h shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.2, when R.sub.gss equals to 10 k in the simulation.
[0066] FIG. 12i shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.2, when R.sub.gss equals to 4.7 k in the simulation.
[0067] FIG. 13a shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.8, when R.sub.gss equals to , in a simulation of the circuit in FIG. 5.
[0068] FIG. 13b shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.8, when R.sub.gss equals to 300 k in the simulation.
[0069] FIG. 13c shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.8, when R.sub.gss equals to 200 k in the simulation.
[0070] FIG. 13d shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.8, when R.sub.gss equals to 150 k in the simulation.
[0071] FIG. 13e shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.8, when R.sub.gss equals to 100 k in the simulation.
[0072] FIG. 13f shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.8, when R.sub.gss equals to 47 k in the simulation.
[0073] FIG. 13g shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.8, when R.sub.gss equals to 15 k in the simulation.
[0074] FIG. 13h shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.8, when R.sub.gss equals to 10 k in the simulation.
[0075] FIG. 13i shows the waveforms of v.sub.ds, v.sub.gs, v.sub.s and i.sub.d under D=0.8, when R.sub.gss equals to 4.7 k in the simulation.
[0076] FIG. 14 shows the relationship between v.sub.s and I.sub.gss under the three duty cycle conditions.
[0077] In the drawings, like numerals indicate like parts throughout the several embodiments described herein.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0078] In the claims which follow and in the preceding description of the invention, except where the context requires otherwise due to express language or necessary implication, the word comprise or variations such as comprises or comprising is used in an inclusive sense, i.e. to specify the presence of the stated features but not to preclude the presence or addition of further features in various embodiments of the invention.
[0079] As used herein and in the claims, couple or connect refers to electrical coupling or connection either directly or indirectly via one or more electrical means unless otherwise stated. When describing a direct connection, it means two circuit components, nodes, or terminals are connected to each other without any intermediate components therebetween.
[0080] Before describing apparatuses for gate leakage current detection according to exemplary embodiments of the invention, the intrinsic characteristics of SiC MOSFETs in terms of gate-source leakage current will be discussed. FIG. 1 shows a comparison of the measured gate-source leakage current I.sub.gss of eight SiC MOSFET devices before and after undergoing 4000 cycles of short-circuit-current (SC) stress. The results reveal a notable increase in I.sub.gss, with a significant percentage increment observed from a few picoamperes (pA) to tens or even hundreds of mA.
[0081] FIG. 2 shows an exemplary gate-driving circuit, in which a MOSFET driver in the form of a gate driver IC 20 drives a SiC MOSFET 22 via a polarized resistive network. The input gate of the MOSFET 22 is modelled by a capacitor C.sub.gs to represent the gate-source capacitance and a resistor R.sub.gss to represent the gate-source leakage resistance. The gate driver IC 20 delivers a logical HIGH signal to turn on the MOSFET 22 via the diode D.sub.ON and the turn-on gate resistor R.sub.ON. Conversely, the gate driver IC 20 delivers a logical LOW signal to turn off the MOSFET 22 via the diode D.sub.OFF and the turn-off gate resistor R.sub.OFF. R.sub.ON and R.sub.OFF are sometimes of different values to control the turn-on and turn-off speeds. The polarized resistive network can be of other structures, but the objective of controlling the turn-on and turn-off profiles is the same. To reduce switching losses, the values of R.sub.ON and R.sub.OFF typically range from several ohms to tens of ohms.
[0082] FIGS. 3a-3d show the experimental results of the output of a MOSFET driver, v.sub.g, gate-source voltage, v.sub.gs, and gate current, i.sub.g. FIG. 3a shows the results for a brand new SiC MOSFET, and FIG. 3b shows the magnified steady-state waveforms. FIG. 3c and FIG. 3d show the corresponding results after aging the same SiC MOSFET for 4000 power cycles respectively. Upon turning on the SiC MOSFET, i.sub.g contains a high input current pulse through C.sub.gs because C.sub.gs is initially uncharged. When C.sub.gs has been fully charged, a relatively steady-state current will flow through R.sub.gss, i.e., the on-state gate-source leakage current as shown in FIG. 3b and FIG. 3d. One can see that the gate leakage current of the SiC MOSFET has an increase from nearly zero to 43 mA after the above-mentioned power cycling. This increase results in a loading effect on the MOSFET driver output, leading to a reduction in v.sub.g from 15.2V to 15.05V and v.sub.gs from 15.2V to 14.52V.
[0083] Various prior art techniques have been proposed to detect the leakage current or estimate the on-state gate-source resistance to perform real-time monitoring of gate oxide conditions. Since the gate current is proportional to the voltage across the gate resistor, the most straightforward method is based on measuring the voltage across R.sub.on to indirectly determine the leakage current. However, there are practical challenges in the voltage measurement circuit which include 1) the amplifier in the measurement circuit must have a wide common-mode voltage capability; 2) the amplifier should have wide bandwidth; 3) the input bias current of the amplifier should be at least one order of magnitude less than the target gate leakage current; and 4) input offset voltage of the amplifier should be at least one order of magnitude smaller than the minimum threshold voltage on the resistor. As a result, the direct measurement of voltage across R.sub.on is only suitable for measuring the gate leakage current of MOSFETs when they are close to their end of life, because by then the gate leakage current would have reached an extreme value.
[0084] Instead of directly measuring the leakage current, an alternative method involves employing capacitors to collect the charge derived from the leakage current. By observing the time taken for the capacitor voltage to reach a predetermined threshold, the magnitude of the leakage current can be indirectly determined. However, it's important to note that the capacitor voltage is influenced not only by the leakage current but also by the durations of the rise time and fall time of the gate-source voltage. Thus, calibration is necessary to mitigate the impact of these voltage transitions on the calculation of the leakage current. Additionally, the rate of change of the capacitor voltage varies with the duty cycle, so it's essential to consider the duty cycle when estimating the leakage current. Building upon the above approach, an extension of the approach has been proposed in which the measurement of the average gate-source voltage is introduced, aiming to eliminate the influence of the duty cycle. By calculating the ratio between the measured average gate-source voltage and the charge accumulated on the capacitor, the gate leakage resistance can be determined. However, calibration is still required in this extended approach to address the impact of voltage transitions on the accuracy of the measurement.
[0085] Inventors of the present invention have therefore realized that although in some prior art methods, measurement of the gate leakage current can be achieved by using a series resistor which is the most straightforward way, such methods did not consider the fluctuation of the gate leakage current. For improved output sensitivity, it is therefore preferable to use a large series resistor when the gate leakage current is low. Conversely, when the gate leakage current is high, a small series resistor is more suitable. This approach ensures accurate and effective measurement of the gate leakage current. However, it is crucial to note that using a large series resistor can influence the waveshape of the gate-source voltage negatively.
[0086] Instead of using a series resistor, one embodiment of the current invention which is an apparatus for measuring a gate leakage current of a MOSFET utilizing a current mirror, as depicted in FIG. 4, which is used to mirror the gate leakage current. FIG. 4 also shows a SiC MOSFET 122 that is to be tested by the apparatus. The current mirror in the current measurement circuit of FIG. 4 is formed by transistors Q.sub.1 and Q.sub.2 which in one example are both PNP transistors. Bases of Q.sub.1 and Q.sub.2 are connected together, and they are connected to the collector of Q.sub.1. In other words, the collector and the base of Q.sub.1 are shorted. The emitters of both Q.sub.1 and Q.sub.2 are connected to a voltage source 128 that functions as a gate driver and is able to generate a gate driving signal such as a square wave. The collector of Q.sub.2 is connected to a sensing resistor Rs, which in turn has a reference node 124 connected both to the voltage source 128 and to a source of the MOSFET 122. The collector of Q.sub.1 is connected to a first end of a turn-on resistor R.sub.on, and a second end of R.sub.on is connected to a gate of the MOSFET 122. For a turn-off resistor R.sub.off in the circuit, it has a first end connected to the voltage source 128 through a diode D.sub.off, and a second end connected to the gate of the MOSFET 122. The diode D.sub.off has a positive terminal connected to the turn-off resistor R.sub.off and a negative terminal connected to the voltage source 228.
[0087] The current mirror in FIG. 4 is adapted to mirror the current passing through an input current path of the current mirror, which is the path of the collector current i.sub.c1 of Q.sub.1. Q.sub.1 is thus in the input branch of the current mirror, while Q.sub.2 is in the output branch of the current mirror. The gate current i.sub.g flows through Q.sub.1 and the collector current i.sub.c1 is almost the same as i.sub.g as the base current of Q.sub.1 is much smaller than i.sub.c1. The collector current of Q.sub.2 is the mirrored current of i.sub.c1 and is therefore also almost the same as the gate current i.sub.g. The voltage across Rs can then reflect the gate current i.sub.g. The gate resistors R.sub.on and R.sub.off serve the same functions as those described above with respect to FIG. 2.
[0088] The voltage across the current mirror is nearly constant. Therefore, when the magnitude of the gate leakage current is small, the equivalent resistance is large. Conversely, when the magnitude of the gate leakage current is large, the equivalent resistance is small. The sensitivity of the apparatus in FIG. 4 as compared to conventional measuring circuits is therefore high, based on the analysis provided previously. In addition, in FIG. 4 the reference node 124 of the sensing resistor is directly connected to the source of the MOSFET 122, which eliminates the need for a differential measurement to measure the voltage across the series resistor. As the mirrored current i.sub.c2 is connected to the sensing resistor Rs, an operating range of the current measurement is set, without affecting the gate-source voltage v.sub.gs. This approach simplifies the measurement process, making it more efficient and straightforward.
[0089] Turning to FIG. 5, according to another embodiment of the invention there is provided an apparatus for measuring a gate leakage current of a SiC MOSFET 222. Similar to the circuit in FIG. 4, the core part of the current measurement circuit in FIG. 5 contains a current mirror that has a same configuration as that in FIG. 4, which will not be described herein again for the sake of brevity. Compared to the circuit of FIG. 4, the circuit in FIG. 5 additionally contains a bypass switch and a discharging circuit. As a steady-state leakage current could be observed only after the MOSFET 222 has been turned on completely, the bypass switch, which is implemented by transistor Q.sub.3, is connected in parallel with the current mirror. In particular, an emitter of the Q.sub.3, and those of the transistors Q.sub.1 and Q.sub.2, are connected to the voltage source 228 at the same time. Also, a collector of the transistor Q.sub.3 is connected, and those of the transistors Q.sub.1 and Q.sub.2, are all connected to the gate of the MOSFET 222 through the turn-on resistor R.sub.on. Upon turning on the MOSFET 222, the bypass transistor Q.sub.3 will be turned on to drive the MOSFET 222, so that the gate-source voltage v.sub.gs is increased in a short time. Afterwards, the current mirror is engaged to perform the steady-state gate leakage current measurement.
[0090] The bypass switch includes the transistor Q.sub.3, and additionally a first resistor R.sub.1, a second resistor R.sub.2, and a capacitor C.sub.1. The resistors R.sub.1, R.sub.2 and the capacitor C.sub.1 form a RC circuit, which connects the base of the transistor Q.sub.3 to the voltage source 228. A first end of R.sub.1 is connected to the voltage source 228 and the emitter of the transistor Q.sub.3. A first end of R.sub.2 is connected to the base of the transistor Q.sub.3. Second ends of R.sub.1 and R.sub.2 are connected to a first end of the capacitor C.sub.1, while a second end of C.sub.1 is connected to the reference node 224 of the sensing resistor Rs to which the source of the MOSFET 222 is also connected.
[0091] The discharging circuit includes a fourth transistor Q.sub.4 in the circuit, a comparator 226, resistors R.sub.3 and R.sub.4, and diodes D.sub.1 and D.sub.2. The diode D.sub.1 has a positive terminal connected to a collector of Q.sub.2, and a negative terminal connected to the base and a collector of Q.sub.1 (the two of which are connected together as mentioned above). The positive terminal of the diode D.sub.1 also connects to an end of the sensing resistor Rs. The comparator 226 has a first input connected to a reference voltage VREF and a second input connected to the collector of Q.sub.2 (and thus also to the sensing resistor Rs and the positive terminal of the diode D.sub.1). The output of the comparator 226 is connected to a base of the transistor Q.sub.4, and also to a first end of the resistor R.sub.3 as well as a positive terminal of the diode D.sub.2. A second end of the resistor R.sub.3 is connected to the voltage source 228. A negative end of the diode D.sub.2 is connected to a collector of Q.sub.4, and to a first end of the resistor R.sub.4. A second end of R.sub.4 is connected to the gate of the MOSFET 222. Finally, an emitter of Q.sub.4 is connected to the reference node 224.
[0092] Having described the circuit components in the apparatus of FIG. 5, now the working principle of the circuit will be described. When v.sub.g is changed from logical HIGH to logical LOW, the voltage level of v.sub.g will change from positive to zero or negative in order to turn off the MOSFET. However, at this moment v.sub.gs is still at a high potential because of the gate-source capacitance C.sub.gs that contains charges. Thus, v.sub.gs>v.sub.g, and D.sub.off is forwardly biased. C.sub.gs will be discharged via R.sub.off and the voltage source 228. The base voltages of Q.sub.1, Q.sub.2, and Q.sub.3 are thus both positive, and Q.sub.1, Q.sub.2, and Q.sub.3 operate in the cut off region. When C.sub.gs has been fully discharged, v.sub.gs=v.sub.g, which is zero or negative. Again, Q.sub.1, Q.sub.2, and Q.sub.3 are still in the cut off region. In other words, the current mirror does not operate when the MOSFET is off. The voltage across R.sub.s, which is v.sub.s, is zero.
[0093] When v.sub.g is changed from logical LOW to logical HIGH, the voltage level of v.sub.g will change from zero or negative to positive to turn on the SiC MOSFET. However, v.sub.gs is still zero or negative because of the presence of the gate-source capacitance C.sub.gs. Thus, the base-emitter voltages of Q.sub.1 and Q.sub.2 are thus both negative, and Q.sub.1 and Q.sub.2 momentarily saturate. The voltage across C.sub.1 at this moment is still zero or negative. Thus, the base-emitter voltages of Q.sub.3 is negative. Q.sub.3 saturates and the duration of such saturation is controlled by the values of R.sub.1, R.sub.2 and C.sub.1. A high current pulse will flow through the gate resistor R.sub.ON, Q.sub.3, and C.sub.gs. The gate current i.sub.g can be approximated by
[00001]
where v.sub.CE,sat is the collector-emitter saturation voltage of Q.sub.1, Q.sub.2 and Q.sub.3.
[0094] The voltage across R.sub.s, which is v.sub.s, is
[00002]
[0095] As C.sub.gs is charged up, the gate current and v.sub.s drop. Q.sub.1 and Q.sub.2 will gradually change from operating in the saturation mode to the cutoff mode. They will enter into the linear mode when C.sub.gs discharges to a certain voltage level, at which the gate current will then be equal to the gate-source leakage current. Such duration is thus dependent on the discharging impedance across C.sub.gs, such as gate-source leakage resistance, leakage current of Q.sub.1 and Q.sub.2, etc. In order to shorten the transition of Q.sub.1 and Q.sub.2 from the saturation mode to linear mode, the discharging circuit is used. When the device is turned on, Q.sub.4 is also turned on by v.sub.g through R.sub.3. Thus, C.sub.gs will discharge through R.sub.4. Until the current mirror operates and v.sub.s rises. The comparator generates a LOW to turn off Q.sub.4. The discharging circuit therefore significantly shortens the time of measuring the gate-source leakage current.
[0096] Assume that the base currents of Q.sub.1 and Q.sub.2 are much smaller than their collector currents. The collector current of Q.sub.1, which is i.sub.c1, is close to the gate current. Thus,
[00003]
[0097] Q.sub.1 and Q.sub.2 have similar electrical characteristics. The collector current of Q.sub.2, which is i.sub.c2, is therefore
[00004]
[0098] The current through R.sub.s is the same as i.sub.g. v.sub.s is equal to
[00005]
[0099] Thus, the gate leakage current i.sub.ss can be estimated by sensing v.sub.s that
[00006]
[0100] With the current mirror, the current through R.sub.s, which is i.sub.s, mirrors i.sub.gss.
[0101] The diodes D.sub.1 and D.sub.2 are used to desaturate Q.sub.2 and Q.sub.4 at turn on.
[0102] Next, the simulation results of the circuit in FIG. 5 will be discussed. In the simulation, the output of the voltage source 228 is set to switch between-5V and +15V. The component part numbers and values are given in Table I below. With R.sub.s=4.7 k, FIGS. 6a-6i show the waveforms of v.sub.gs, v.sub.s and i.sub.g when R.sub.gss equals to , 300 k, 200 k, 150 k, 100 k, 47 k, 15 k, 10 k and 4.7 k, respectively. It can be observed that v.sub.s is 15V in a short period for all R.sub.gss because of the i.sub.g due to switching transient and then keeps at steady state voltage according to the value of R.sub.gss. After R.sub.gss decreases, the steady state voltage of v.sub.s increases. When R.sub.gss equals 4.7 k which means i.sub.gss equals to 3.2 mA, v.sub.s increases to 14.2V at a steady state.
TABLE-US-00001 TABLE I Component Part Nos. and Values Part no. / Part no. / Component Value Component Value R.sub.1 510 C.sub.1 120 pF R.sub.2 100 Q.sub.1 2N4126 R.sub.3 20 k Q.sub.2 2N4126 R.sub.4 2.7 k Q.sub.3 2N4126 R.sub.s 4.7 k Q.sub.4 2N3391 R.sub.ON 4.7 D.sub.1 1N4148 R.sub.OFF 4.7 D.sub.2 1N4148 D.sub.OFF 1N4148
[0103] Besides the simulation, the apparatus for measuring the gate leakage circuit in FIG. 5 has also been validated experimentally. FIG. 7 shows the test circuit used for the experiment, which includes a SiC MOSFET 322, a driving circuit 330 in FIG. 7, and a load resistor R.sub.L. The supply voltage to the SiC MOSFET 322 is V.sub.CC. The switching frequency is 50 kHz. A resistor R.sub.gss, which is connected across the gate and source of the SiC MOSFET, is used to adjust the steady-state gate current to emulate the gate leakage current of the SiC MOSFET. The emulated gate leakage current will be small when R.sub.gss is large. Conversely, it will be large when R.sub.gss is small. Three different driving circuits have been tested, which are respectively the circuit shown in FIG. 5, the circuit shown in FIG. 8a (which does not have a current mirror), and the circuit shown in FIG. 8b (which does not have a current mirror or a polarized resistive network, and includes simply a gate resistor). These three driving circuits individually represent the driving circuit 330 when they are implemented in the test circuit. The component part numbers and values of the three driving circuits are given in Table II. The measured waveforms of the drain-source voltage, v.sub.ds, gate-source voltage, v.sub.gs, output voltage of the gate driver, v, and drain current. i.sub.d, upon turning on the SiC MOSFET for the three circuits are given in FIGS. 9a-9c respectively. No R.sub.gss is connected to the driving circuit. The drain-source voltage before turning on is 20V. The transient and steady-state characteristics are given in Table II. The nomenclature of the symbols is given as follows: [0104] V.sub.ds,ON: Steady-state on-state value of v.sub.ds [0105] t.sub.ds,f: Fall time of v.sub.ds (From 90% to 10% of the steady-state value) [0106] V.sub.g,ON: Steady-state on-state value of v.sub.g [0107] t.sub.g,r: Rise time of v.sub.g (From 10% to 90% of the steady-state value) [0108] V.sub.gs,ON: Steady-state on-state value of v.sub.gs [0109] t.sub.gs,r: Rise time of v.sub.gs (From 10% to 90% of the steady-state value) [0110] I.sub.d,ON: Steady-state on-state value of i.sub.d [0111] t.sub.d,r: Rise time of i.sub.d (From 10% to 90% of the steady-state value)
TABLE-US-00002 TABLE II Component Part Nos. and Values Part no. / Part no. / Component Value Component Value For the circuit shown in FIG. 5: R.sub.1 510 C.sub.1 120 pF R.sub.2 100 Q.sub.1 2SA1978 R.sub.3 20 k Q.sub.2 2SA1978 R.sub.4 2.7 k Q.sub.3 2SA1978 R.sub.s 4.7 kQ Q.sub.4 MMBTH10 R.sub.on 4.7 D.sub.1 DB2731400L R.sub.off 4.7 D.sub.2 DB2731400L D.sub.off 1N4148 For the circuit shown in FIG. 8a: R.sub.on 4.7 R.sub.off 4.7 D.sub.off 1N4148 D.sub.off 1N4148 For the circuit shown in FIG. 8b: R.sub.g 4.7
TABLE-US-00003 TABLE III Transient and Steady-State Characteristics Circuit shown Circuit shown Circuit shown Parameter in FIG. 5 in FIG. 8a in FIG. 8b V.sub.ds, ON 0 V 0 V 0 V t.sub.ds, f 7 ns 7 ns 7 ns V.sub.g, ON 15 V 15 V 15 V t.sub.g, r 9.2 ns 8.4 ns 8.8 ns V.sub.gs, ON 14.3 V 14.5 V 15 V t.sub.gs, r 13.2 ns 12.6 ns 10.6 ns I.sub.d, ON 4.6 A 4.6 A 4.6 A t.sub.d, r 13.8 ns 13.6 ns 13.6 ns
[0112] Based on the measured parameters, it can be observed that the driving circuit/current measurement circuit in FIG. 5 slightly lengthen the rise time of v.sub.g and v.sub.gs, but the turn-on time of v.sub.ds and i.sub.d is nearly the same. The steady-state gate-source voltage slightly drops, because of the small voltage drop across the current mirror.
[0113] The measured waveforms of the drain-source voltage, v.sub.ds, gate-source voltage, v.sub.gs, output voltage of the gate driver, v.sub.g, and drain current. i.sub.d, upon turning off the SiC MOSFET for the three circuits are given in FIGS. 10a-10c respectively. The drain current before turning off is 4.6 A. The transient and steady-state characteristics are given in Table IV. The nomenclature of the symbols is given as follows: [0114] V.sub.ds,OFF: Steady-state off-state value of v.sub.ds [0115] t.sub.ds,r: Rise time of v.sub.ds (10% to 90% of the steady-state value) [0116] v.sub.g,OFF: Steady-state off-state value of v.sub.g [0117] t.sub.g,f: Fall time of v.sub.g (90% to 10% of the steady-state value) [0118] V.sub.gs,OFF: Steady-state off-state value of v.sub.gs [0119] t.sub.gs,f: Fall time of v.sub.gs (90% to 10% of the steady-state value) [0120] I.sub.d,OFF: Steady-state off-state value of i.sub.d [0121] t.sub.d,f: Fall time of i.sub.d (90% to 10% of the steady-state value)
TABLE-US-00004 TABLE IV Transient and Steady-State Characteristics Circuit shown Circuit shown Circuit shown Parameter in FIG. 5 in FIG. 8a in FIG. 8b V.sub.ds 20.9 V 20.9 V 20.9 V t.sub.ds, r 4.2 ns 4.2 ns 4.2 ns V.sub.g 6 6 6 t.sub.g, f 9.4 ns 9 ns 9.6 ns V.sub.gs 5.6 5.6 6 t.sub.gs, f 10.8 ns 10.8 ns 11 ns I.sub.d, OFF 0 A 0 A 0 A t.sub.d, f 3.2 ns 3.2 ns 3.4 ns
[0122] Since the turn-off process only involves R.sub.off and D.sub.off, based on the measured parameters, it can be observed that the fall time of v.sub.g and v.sub.gs and the turn-off time of v.sub.ds and i.sub.d of the circuit of FIG. 5 is nearly the same. The steady-state gate-source voltage slightly drops because of the small voltage drop across the diode.
[0123] The waveforms of v.sub.s under different values of R.sub.gss are observed. FIGS. 11a-11i show the waveforms of v.sub.s when R.sub.gss equals to 0, 300 k, 200 k, 150 k, 100 k, 47 k, 15 k, 10 k and 4.7 k, respectively. The switching frequency is 50 kHz and the duty cycle D of the SiC MOSFET is 0.5. v.sub.s takes approximately 500 ns before reaching the steady state. The steady-state value of v.sub.s against different R.sub.gss and gate leakage current I.sub.gss are tabulated in Table V.
TABLE-US-00005 TABLE V Steady-state value of v.sub.s against different R.sub.gss and duty cycle D v.sub.s R.sub.gss I.sub.gss D = 0.2 D = 0.5 D = 0.8 0 mA 0.6 0.6 0.6 300 k 0.05 mA 0.8 0.9 0.9 200 k 0.075 mA 1 1.1 1.1 150 k 0.1 mA 1.2 1.3 1.3 100 k 0.15 mA 1.5 1.7 1.6 47 k 0.32 mA 2.6 2.7 2.7 15 k 1.0 mA 6.4 6.4 6.4 10 k 1.5 mA 8.7 8.8 8.8 4.7 k 3.2 mA 14.1 14.1 14.1
[0124] With D=0.2 and D=0.8, the steady-state values of v.sub.s are given in Table V. The waveforms under these two duty cycle conditions are shown in FIGS. 12a-12i and FIGS. 13a-13i respectively. The relationships between v.sub.s and I.sub.gss are shown in FIG. 14. It can be observed that v.sub.s is nearly independent of the duty cycle and varies with R.sub.gss and thus I.sub.gss. It can be used to detect the gate leakage current. It can be sensed by a microcontroller to detect the gate leakage condition of the SiC MOSFET.
[0125] In summary, one can see that the circuit shown in FIG. 5 provides a gate driving circuit including a current mirror to perform switching operation and monitoring the gate source leakage current simultaneously. The basic structure is a current mirror that mirrors the gate leakage current i.sub.g to a sensing resistor R.sub.s. It includes the basic structure for measuring i.sub.g, a bypass circuit for improving the switching speed, and a discharge circuit to enhance the dynamic response. The circuit has been tested on a 100 W switching circuit. The experimental results show that the switching speed of the MOSFET when using the proposed circuit is nearly the same as using a polarized network or a single R.sub.g. Then, by inserting R.sub.gss, the results show that the proposed circuit can perform sensing of the current through R.sub.gss. Moreover, with the duty cycle of the MOSFET varying from 20% to 80%, the experimental results show that the sensing operation of the circuit of FIG. 5 is independent of the duty cycle of the gate signal.
[0126] The exemplary embodiments of the present invention are thus fully described. Although the description referred to particular embodiments, it will be clear to one skilled in the art that the present invention may be practiced with variation of these specific details. Hence this invention should not be construed as limited to the embodiments set forth herein.
[0127] While the invention has been illustrated and described in detail in the drawings and foregoing description, the same is to be considered as illustrative and not restrictive in character, it being understood that only exemplary embodiments have been shown and described and do not limit the scope of the invention in any manner. It can be appreciated that any of the features described herein may be used with any embodiment. The illustrative embodiments are not exclusive of each other or of other embodiments not recited herein. Accordingly, the invention also provides embodiments that comprise combinations of one or more of the illustrative embodiments described above. Modifications and variations of the invention as herein set forth can be made without departing from the spirit and scope thereof, and, therefore, only such limitations should be imposed as are indicated by the appended claims.
[0128] For example, although specific current mirror and discharging circuits are illustrated in FIGS. 4-5 with accompany descriptions, these are only those used in some embodiments of the invention. In a general sense, the current mirror structure can vary as long as its purpose remains consistent: to measure the gate current and mirror it to a sensing resistor. Similarly, the bypass switch can take on different structures as long as it effectively bypasses the current mirror during the turn-on process to drive the MOSFET. The specific design and structure of these modules/components can be adapted to suit the requirements and constraints of the system while still fulfilling their intended functions.
