Solid state imaging element and electronic apparatus

Abstract

A solid state imaging element according to an embodiment includes: a converter (14) that converts an analog pixel signal read out from a pixel into a bit value, successively for each of a plurality of bits, on the basis of a threshold voltage set according to a conversion history of the bit converted before a target bit; a plurality of voltage generation units (102a and 102b) that each generate a plurality of reference voltages; and a setting unit (12d) that sets the threshold voltage using the reference voltage selected from the reference voltages generated by each of the voltage generation units on the basis of a conversion result.

Claims

1. A solid state imaging element, comprising: a converter that converts an analog pixel signal read out from a pixel into a bit value, successively for each of a plurality of bits, on the basis of a threshold voltage set according to a conversion history of the bit converted before a target bit; a plurality of voltage generation units that each generate a plurality of reference voltages; and a setting unit that sets the threshold voltage using the reference voltage selected from the reference voltages generated by each of the voltage generation units on the basis of the conversion history.

2. The solid state imaging element according to claim 1, wherein the voltage generation units include: a first voltage generation unit that generates the reference voltages for conversion by the converter from the analog pixel signal into the bit value of the bit on a high order side; and a second voltage generation unit that generates the reference voltages for conversion by the converter from the analog pixel signal into the bit value of the bit on a low order side.

3. The solid state imaging element according to claim 2, wherein the second voltage generation unit generates a plurality of reference voltages having a voltage range overlapping with the reference voltages generated by the first voltage generation unit, and the setting unit sets the threshold voltage by changing the reference voltage selected on the basis of the conversion history on the basis of the reference voltage included in the voltage range.

4. The solid state imaging element according to claim 3, wherein the second voltage generation unit generates the reference voltages such that two or more reference voltages are included in the voltage range when a gain with respect to the analog pixel signal is equal to or larger than a certain value.

5. The solid state imaging element according to claim 3, wherein the second voltage generation unit generates the reference voltages such that a single reference voltage is included in the voltage range when a gain with respect to the analog pixel signal is smaller than a certain value.

6. The solid state imaging element according to claim 1, wherein, out of connection points from which the reference voltages generated by each of the voltage generation units are taken out, respectively, the connection points having identical potential are connected one another.

7. The solid state imaging element according to claim 1, further comprising a sample hold unit that samples the voltage generated by one of the voltage generation units and supplies the sampled voltage to another of the voltage generation units.

8. An electronic apparatus, comprising: a solid state imaging element that includes a converter that converts an analog pixel signal read out from a pixel into a bit value, successively for each of a plurality of bits, on the basis of a threshold voltage set according to a conversion history of the bit converted before a target bit, a plurality of voltage generation units that each generates a plurality of reference voltages, and a setting unit that sets the threshold voltage using the reference voltage selected from the reference voltages generated by each of the respective voltage generation units on the basis of the conversion history; and an image processing unit that performs image processing on a digital pixel signal converted by the converter from the analog pixel signal into a bit value for each bit.

9. The electronic apparatus according to claim 8, wherein the voltage conversion units include: a first voltage generation unit that generates the reference voltages for conversion by the converter from the analog pixel signal into the bit value of the bit on a high order side; and a second voltage generation unit that generates the reference voltages for conversion by the converter from the analog pixel signal into the bit value of the bit on a low order side.

10. The electronic apparatus according to claim 9, wherein the second voltage generation unit generates a plurality of reference voltages having a voltage range overlapping with the reference voltages generated by the first voltage generation unit, and the setting unit sets the threshold voltage by changing the reference voltage selected on the basis of the conversion history on the basis of the reference voltage included in the voltage range.

11. The electronic apparatus according to claim 10, wherein the second voltage generation unit generates the reference voltages such that two or more reference voltages are included in the voltage range when a gain with respect to the analog pixel signal is equal to or larger than a certain value.

12. The electronic apparatus according to claim 10, wherein the second voltage generation unit generates the reference voltages such that a single reference voltage is included in the voltage range when a gain with respect to the analog pixel signal is smaller than a certain value.

13. The electronic apparatus according to claim 8, wherein, in the solid state imaging element, out of connection points from which the reference voltages generated by each of the voltage generation units are taken out, respectively, the connection points having identical potential are connected one another.

14. The electronic apparatus according to claim 8, wherein the solid state imaging element further includes a sample hold unit that samples the voltage generated by one of the voltage generation units and supplies the sampled voltage to another of the voltage generation units.

15. The electronic apparatus according to claim 8, wherein the electronic apparatus is an indirect ToF method range image sensor.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a block diagram illustrating an exemplary structure of a solid state imaging element and an electronic apparatus using the solid state imaging element that are applicable to a first embodiment.

(2) FIG. 2 is a block diagram illustrating an exemplary structure of an AD conversion unit applicable to the first embodiment.

(3) FIG. 3 is a diagram illustrating an exemplary structure of a successive approximation type AD converter according to an existing technique, the successive approximation type AD converter including a DA converter that generates a plurality of reference voltages from a single voltage.

(4) FIG. 4 is a diagram illustrating a successive approximation type AD converter according to an existing technique, the successive approximation type AD converter including a DA converter that obtains a plurality of reference voltages from a single voltage and further divides the obtained reference voltages into a plurality of systems.

(5) FIG. 5 is a diagram for explaining an AD conversion range in the structure in which the voltages included in the multiple systems are generated from the single voltage.

(6) FIG. 6 is a diagram illustrating an exemplary basic structure of a successive approximation type AD converter according to the first embodiment.

(7) FIG. 7 is a diagram illustrating a more concrete structural example of the successive approximation type AD converter according to the first embodiment.

(8) FIG. 8 is a diagram for explaining the AD conversion range in the successive approximation type AD converter according to the first embodiment.

(9) FIG. 9A is a diagram for roughly explaining determination error correction using a redundant bit, the determination error correction being applicable to the first embodiment.

(10) FIG. 9B is a diagram for roughly explaining the determination error correction using the redundant bit, the determination error correction being applicable to the first embodiment.

(11) FIG. 9C is a diagram for roughly explaining the determination error correction using the redundant bit, the determination error correction being applicable to the first embodiment.

(12) FIG. 10 is a diagram illustrating an example of the AD conversion that can achieve high resolution and is applicable to the first embodiment.

(13) FIG. 11 is a diagram illustrating an example where the AD conversion is performed by expanding a redundant range, the AD conversion being applicable to the first embodiment.

(14) FIG. 12A is a diagram illustrating more specifically a structure of a reference voltage generator applicable to the first embodiment.

(15) FIG. 12B is a diagram illustrating more specifically a structure of another reference voltage generator applicable to the first embodiment.

(16) FIG. 13 is a diagram illustrating a first example of a structure that can reduce a variance among a plurality of systems and is applicable to the first embodiment.

(17) FIG. 14 is a diagram illustrating a second example of the structure that can reduce the variance among the multiple systems and is applicable to the first embodiment.

(18) FIG. 15 is a diagram roughly illustrating an exemplary structure of an indirect ToF method range image sensor applicable to a second embodiment.

(19) FIG. 16 is a circuit diagram illustrating an exemplary structure of a pixel applicable to the second embodiment.

DESCRIPTION OF EMBODIMENTS

(20) The following describes embodiments of the disclosure in detail with reference to the accompanying drawings. In the following embodiments, the same portions are labeled with the same numerals and duplicated descriptions thereof are omitted.

First Embodiment

(21) Exemplary structure of solid state imaging element and electronic apparatus that are applicable to first embodiment.

(22) FIG. 1 is a block diagram illustrating an exemplary structure of a solid state imaging element and an electronic apparatus using the solid state imaging element that are applicable to a first embodiment. In FIG. 1, an electronic apparatus 1000 applicable to the first embodiment includes a solid state imaging element 1, an image processing unit 1001, and a control unit 1002.

(23) The solid state imaging element 1 includes a pixel array unit 2, a row scan circuit 3, an analog to digital (AD) conversion unit 5, a timing control unit 6, a column scan circuit 7, and a signal processing unit 8.

(24) The pixel array unit 2 is provided with a plurality of scan lines and a plurality of signal lines. At each of the intersections of the scan lines and the signal lines, a pixel circuit is disposed. The multiple pixel circuits are provided in a two-dimensional grid shape. Under the control of the timing control unit 6, the row scan circuit 3 causes any one of the multiple scan lines to be active, and drives the pixel circuits of one row (corresponding to one column) included in the pixel array unit 2 corresponding to the scan line caused to be active to cause the pixel circuits to output pixel signals V.sub.SL.

(25) The timing control unit 6 controls timing at which each of the row scan circuit 3, the AD conversion unit 5, and the column scan circuit 7 operates on the basis of a clock signal supplied from the control unit 1002, for example.

(26) The AD conversion unit 5 has a plurality of AD converters, which are described later, and converts the pixel signals V.sub.SL, which are output from the pixel array unit 2 and analog signals, into pixel data, which are digital signals.

(27) The column scan circuit 7, which operates in synchronization with the operation of the row scan circuit 3 and the AD conversion unit 5 under the control of the timing control unit 6, sequentially transfers, to the signal processing unit 8, the pixel data that is AD converted from the pixel signal V.sub.SL by the AD conversion unit 5 for each signal line. The signal processing unit 8 performs signal processing such as noise removal and auto gain control (AGC) on the transferred pixel data.

(28) In the above description, the signal processing unit 8 is disposed in the solid state imaging element 1. The location is, however, not limited to this example. For example, the signal processing unit 8 can be provided separately outside the solid state imaging element 1. The circuits in the solid state imaging element 1 may be arranged on a single semiconductor substrate or arranged by being distributed on a plurality of layered semiconductor substrates.

(29) For example, image data of one frame is formed by the pieces of pixel data of the pixel circuits included in the pixel array unit 2 after having been subjected to signal processing by the signal processing unit 8. The image data is output from the solid state imaging element 1 and transferred to the image processing unit 1001, for example. The image processing unit 1001 can perform image processing such as demosaic processing, white balance adjustment processing, and gamma correction processing on the image data transferred from the solid state imaging element 1, for example. The image processing unit 1001 can also perform compression encoding processing on the image data after having been subjected to such image processing.

(30) The control unit 1002, which includes a central processing unit (CPU), a read only memory (ROM), a random access memory (RAM), a timer, and various interfaces, for example, controls the whole operation of the electronic apparatus 1000. For example, when the electronic apparatus 1000 is an imaging device that performs imaging in accordance with light entering the solid state imaging element 1 from a subject via an optical system, the control unit 1002 can perform control on the optical system and drive control on the solid state imaging element 1 (e.g., diaphragm control and exposure control).

(31) FIG. 2 is a block diagram illustrating an exemplary structure of the AD conversion unit 5 applicable to the first embodiment. In FIG. 2, the AD conversion unit 5 includes a plurality of AD converters 10.sub.1, 10.sub.2, . . . , 10.sub.n-1, and 10.sub.n (n is a natural number). In FIG. 2, the structure including pixels PX1 to PX34, which are on the upper side of the AD converters 10.sub.1, 10.sub.2, . . . , 10.sub.n-1, and 10.sub.n, corresponds to the pixel array unit 2 in FIG. 1.

(32) In the example illustrated in FIG. 2, the AD conversion unit 5 performs processing in a time division manner on eight columns for each AD converter. For simplified illustration, FIG. 2 illustrates n number of AD converters 10.sub.1 to 10.sub.n out of 2n number of provided AD converters (n is a natural number). Actually, n number of remaining AD converters are arranged on the upper side of output signal lines extending in the upper direction from the pixels.

(33) In this case, the AD converters 10.sub.1 to 10.sub.n, each of which is an AD converter of a successive approximation type (hereinafter, called a successive approximation type AD converter), each include a digital to analog (DA) converter 12, a preamplifier unit 13, a comparator 14, and a logic unit 15.

(34) In the example illustrated in FIG. 2, out of 16 pixels of pixels PX1 to PX4, pixels PX11 to PX14, pixels PX21 to PX24, and pixels PX31 to PX34, eight pixels, which are half of 16 pixels, are allocated for each of the successive approximation type AD converters 10.sub.1 to 10.sub.n.

(35) Specifically, for each of the illustrated successive approximation type AD converters 10.sub.1 to 10.sub.n, eight pixels of the pixels PX1, PX3, PX11, PX13, PX21, PX23, PX31, and PX33 are allocated. In the same manner, for each of the n number of AD converters (not illustrated), eight pixels of the pixels PX2, PX4, PX12, PX14, PX22, PX24, PX32, and PX3 are allocated.

(36) The following describes basic operation of the AD conversion unit 5 illustrated in FIG. 2. The successive approximation type AD converters 10.sub.1 to 10.sub.n, and the n number of AD converters (not illustrated) that are included in the AD conversion unit 5 perform processing in synchronization with and independently from one another. The basic operation is described using the successive approximation type AD converter 10.sub.1 as an example.

(37) The successive approximation type AD converter 10.sub.1 performs processing, for each reading of data, in the order from the pixel PX1, the pixel PX3, the pixel PX11, the pixel PX13, the pixel PX21, the pixel PX23, the pixel PX31, to the pixel PX33, for example.

(38) At a first processing timing, the DA converter 12 of the successive approximation type AD converter 101 generates, on the basis of a reference voltage, a threshold voltage V.sub.th corresponding to a bit position in accordance with a control signal having a digital value supplied from the logic unit 15. The threshold voltage V.sub.th generated by the DA converter 12 is input into one input end of the comparator 14 via the preamplifier unit 13.

(39) Into the other input end of the comparator 14, the pixel signal V.sub.SL is input from a pixel signal input terminal selected out of the pixel signal input terminals T.sub.SL1 to T.sub.SL8 in a time division control manner. The comparator 14 compares the threshold voltage V.sub.th input into the one input end with the pixel signal V.sub.SL input into the other input end to send the comparison result to the logic unit 15.

(40) The logic unit 15 holds a bit value of a target bit position in a register in accordance with the comparison result, for example. In accordance with the comparison result, the logic unit 15 generates a digital value for setting the threshold voltage V.sub.th corresponding to the next bit position to supply the digital value to the DA converter 12. The DA converter 12 performs DA conversion on the digital value to generate the threshold voltage V.sub.th. The generated threshold voltage V.sub.th is input into the other input end of the comparator 14 via the preamplifier unit 13.

(41) The successive approximation type AD converter 10.sub.1 successively repeats the processing described above from a most significant bit to a least significant bit for each bit to convert the pixel signal V.sub.SL into the digital pixel data. For example, when the logic unit 15 ends the processing up to the least significant bit, the successive approximation type AD converter 10.sub.1 outputs pixel data DV.sub.SL having a certain bit length held in a register of the logic unit 15, for example, from an output terminal T.sub.DOUT.

(42) In the same manner, at each of the processing timings from a second processing timing to an eighth processing timing under the time division control, the successive approximation type AD converter 10.sub.1 performs processing on the input pixel signals V.sub.SL that are input from the input pixel signal input terminals T.sub.VSL2 to T.sub.VSL8 and correspond to the respective pixels PX3, PX11, PX13, PX21, PX23, PX31, and PX33.

(43) The successive approximation type AD converters 10.sub.2 to 10.sub.n and the n number of AD converters (not illustrated) perform the same processing simultaneously in parallel.

(44) More specific example of AD conversion processing according to the first embodiment

(45) Structure according to existing technique and example of processing thereby

(46) The following describes a structure of the successive approximation type AD converters 10.sub.1 to 10.sub.n, according to the first embodiment and AD conversion processing thereby. In the following description, the successive approximation type AD converters 10.sub.1 to 10.sub.n, are collectively described as the successive approximation type AD converters 10 unless otherwise specifically described. Prior to the description about the first embodiment, a structure of the successive approximation type AD converter according to an existing technique and an example of processing thereby, which corresponds to the successive approximation type AD converters 10.sub.1 to 10.sub.n, according to the first embodiment, are described for the purpose of making it easy to understand the description.

(47) The successive approximation type AD converter successively compares, by binary search, a voltage of the input signal with the threshold voltage V.sub.th that is generated for each bit on the basis of voltage values that are generated from the reference voltage, increase in a binary manner, and correspond to the number of bits, thereby converting the input signal, which is an analog signal, into a digital signal. The threshold voltage V.sub.th is generally generated by a capacitive DA converter using capacitors having capacitances increasing in a binary manner. When a single reference voltage is used, the capacitance of the capacitors required by the capacitive DA converter becomes large, resulting in the circuit area being increased.

(48) A successive approximation type AD converter has been proposed that uses a capacitive DA converter having a plurality of reference voltages. FIG. 3 is a diagram illustrating an exemplary structure of a successive approximation type AD converter 10a according to an existing technique. The successive approximation type AD converter 10a includes a DA converter 12a that generates a plurality of reference voltages of an upper limit voltage VRT, an intermediate voltage VRC, and a lower limit voltage VRB from a single voltage. In the example illustrated in FIG. 3, the upper limit voltage VRT, the intermediate voltage VRC, and the lower limit voltage VRB are generated by resistance voltage division from a single voltage V.sub.DD-ref. A voltage VREF that is a difference between the upper limit voltage VRT and the lower limit voltage VRB is an AD conversion range of the successive approximation type AD converter 10a.

(49) In the successive approximation type AD converter 10a illustrated in FIG. 3, the preamplifier unit 13 and the logic unit 15 that are illustrated in FIG. 2 are omitted.

(50) In the successive approximation type AD converter 10a illustrated in FIG. 3, a voltage V.sub.ref of the voltage V.sub.DD-ref is divided into voltages by resistors R212.sub.1 to R212.sub.6 that form a ladder resistance circuit. The upper limit voltage VRT, the intermediate voltage VRC, and the lower limit voltage VRB are taken out from the connection points 204.sub.1 to 204.sub.3, respectively.

(51) In the successive approximation type AD converter 10a, the pixel signal V.sub.SL is input into the other input end of a comparator 200 (corresponding to the comparator 14 in FIG. 2) via a coupling capacitor 201.

(52) To one input end of the comparator 200, one ends of capacitors C210.sub.1, C210.sub.2, C210.sub.3, and C210.sub.4, which are used for generating the threshold voltage V.sub.th and have capacitances C, 2C, 4C, and 8C, respectively, the capacitances increasing in a binary manner (by two times), via a connection line 202. The other ends of the capacitors C210.sub.1 to C210.sub.4 are connected to terminals x of switches SW211.sub.1 to SW211.sub.4, respectively. The switches SW211.sub.1 to SW211.sub.4 are each controlled such that one of terminals a, b, and c is connected to the terminal x by a control signal output from the logic unit 15 (not illustrated).

(53) In each of the switches SW211.sub.1 to SW211.sub.4, the terminal a is connected to the connection point 204.sub.1 to receive supply of the upper limit voltage VRT, the terminal b is connected to the connection point 204.sub.2 to receive supply of the intermediate voltage VRC, and the terminal c is connected to the connection point 204.sub.3 to receive supply of the lower limit voltage VRB. A voltage VREF that is a potential difference between the upper limit voltage VRT and the lower limit voltage VRB is an AD conversion range of the successive approximation type AD converter 10a.

(54) A capacitance Cp represents a stray capacitance of the connection line 202.

(55) In the structure, a voltage taken out from the connection point between the capacitor selected by the switches SW211.sub.1 to SW211.sub.4 out of the capacitors C210.sub.1 to C210.sub.4 and a capacitor C210.sub.0 is input into one input end of the comparator 200 as the threshold voltage V.sub.th.

(56) As for the operation, the terminals x and the terminals b are connected in the switches SW211.sub.1 to SW211.sub.4, respectively, resulting in the intermediate voltage VRC being applied to the ends of the capacitors C210.sub.1 to C210.sub.4 on the side of the terminals x of the switches SW211.sub.1 to SW211.sub.4, and then a specific potential is applied to the connection line 202 connected to the one input end of the comparator 200, thereby resetting the capacitors C210.sub.1 to C210.sub.4.

(57) The comparator 200 compares the pixel signal V.sub.SL input into the one input end with the threshold voltage V.sub.th input into the other input end. As a result of the comparison, when the voltage value of the pixel signal V.sub.SL is higher than the voltage value of the threshold voltage V.sub.th, the comparator 200 determines the bit value to be “1” while when the voltage value of the pixel signal V.sub.SL is lower than the voltage value of the threshold voltage V.sub.th, the comparator 200 determines the bit value to be “0”, for example. When the determination of the most significant bit (MSB) is “1” as the determination result at the reset of the respective capacitors C210.sub.1 to C210.sub.4, for example, the terminal a and the terminal x are connected in the switch SW211.sub.4. As a result, the threshold voltage V.sub.th is increased by the capacitor C210.sub.4 having the capacitance 8C. When the determination result at the reset is “0”, the terminal c and the terminal x are connected in the switch SW211.sub.4 to reduce the threshold voltage V.sub.th.

(58) For the determination of the next bit, the threshold voltage V.sub.th is used that is changed in accordance with the determination result of the previous bit. When the previous determination result is “1”, the terminal x and the terminal a are connected in the switch SW211.sub.3. As a result, the threshold voltage V.sub.th is reduced by the capacitor C210.sub.3 that has the capacitance 4C and is connected to the one input end of the comparator 200 via the connection line 202. When the previous determination result is “0”, the terminal x and the terminal c are connected in the switch SW211.sub.3. As a result, the threshold voltage V.sub.th is reduced by the capacitor C210.sub.3 connected to the one input end of the comparator 200 via the connection line 202. In the same manner as described above, the comparator 200 compares the pixel signal V.sub.SL with the threshold voltage V.sub.th. When the voltage value of the pixel signal V.sub.SL is higher than the voltage value of the threshold voltage V.sub.th, the comparator 200 determines the bit value to be “1” while when the voltage value of the pixel signal V.sub.SL is lower than the voltage value of the threshold voltage V.sub.th, the comparator 200 determines the bit value to be “0”.

(59) The successive approximation type AD converter 10a repeatedly performs the processing described above up to the final bit to convert the pixel signal V.sub.SL into the pixel data having a digital value. As described above, the successive approximation type AD converter 10a successively performs conversion of the input voltage, for each bit, from the high order side bit to the low order side bit using the threshold voltage V.sub.th set based on the conversion result of the high order bit.

(60) When the AD conversion is performed on the pixel signal, a voltage width of the voltage VREF needs to be set larger in consideration of distribution variation in precharge phase (P phase), an offset voltage of the comparator 200, and further gain loss in the DA conversion due to the stray capacitance and a redundant bit capacitance in the capacitive DA converter. The size of 1LSB is determined by an input range of the pixel signal V.sub.SL input into the comparator 200 and the number of bits in the AD conversion. For increasing the voltage width of the voltage VREF without changing 1LSB, it is necessary to increase the number of bits of the DA converter 12a.

(61) When a DA conversion range is increased by one bit in the DA converter 12a, the voltage value of the voltage VREF needs to be doubled. The upper limit of the voltage VREF is determined by a power source voltage. As the voltage increases, power consumption of a reference voltage generation circuit increases. In order to reduce the voltage value of the voltage VREF, a method exists in which capacitances of the capacitors used for generating the threshold voltage V.sub.th in the DA converter 12a are increased, thereby reducing the gain loss in the DA conversion. This method, however, causes an increase in circuit area and occurrence of settling deterioration in the DA converter 12a.

(62) Particularly, the connection point 204.sub.2, from which the intermediate voltage VRC is taken out and which is an intermediate node in the ladder resistance circuit composed of the resistors R212.sub.1 to R212.sub.6, has a high output impedance. This causes long time settling in the DA conversion. When the resistance value of the ladder resistance circuit is reduced so as to achieve short time settling in the DA conversion, a current needs to be increased for securing a necessary DA conversion range, resulting in an increase in power consumption of the reference voltage generation circuit.

(63) FIG. 4 is a diagram illustrating an exemplary structure of a successive approximation type AD converter 10b according to an existing technique. The successive approximation type AD converter 10b includes a DA converter 12b that obtains, from the single voltage V.sub.DD-ref, a plurality of reference voltages (the upper limit voltages VRT and VRT.sub.2, the intermediate voltage VRC, and the lower limit voltages VRB.sub.2 and VRB) and divides the obtained reference voltages into a plurality of systems.

(64) Specifically, in the example illustrated in FIG. 4, the respective voltages obtained from the voltage V.sub.DD-ref are divided into two systems, that is, a reference voltage system composed of the upper limit voltage VRT, the intermediate voltage VRC, and the lower limit voltage VRB, and a reference voltage system composed of the upper limit voltage VRT.sub.2, the intermediate voltage VRC, and the lower limit voltage VRB.sub.2. In FIG. 4, the stray capacitance of the connection line 202 is omitted.

(65) In the successive approximation type AD converter 10b illustrated in FIG. 4, the upper limit voltages VRT and VRT.sub.2, the intermediate voltage VRC, and the lower limit voltages VRB.sub.2 and VRB, which are divided by the resistors R217.sub.1 to R217.sub.6 forming the ladder resistance circuit, are taken out from the connection points 2181 to 2185, respectively.

(66) To one input end of the comparator 200, one ends of capacitors C213.sub.1 and C213.sub.2 used for generating the threshold voltage V.sub.th are connected via the connection line 202. The capacitors C213.sub.1 and C213.sub.2 have a capacitance C and a capacitance 2C, respectively, which increase in a binary manner (by two times). The capacitors C213.sub.1 and C213.sub.2 correspond to the conversion on the low order bit side in the AD conversion by the successive approximation type AD converter 10b.

(67) To the one input end of the comparator 200, one ends of capacitors C214.sub.1 and C214.sub.2 that have the capacitance C and the capacitance 2C, respectively, in the same manner as the capacitors C213.sub.1 and C213.sub.2 are further connected via the connection line 202. The capacitors C214.sub.1 and C214.sub.2 correspond to the conversion on the high order bit side in the AD conversion by the successive approximation type AD converter 10b.

(68) In the successive approximation type AD converter 10b, to the one input end of the comparator 200, a capacitor C215 having a capacitance 4C and being used for generating the threshold voltage V.sub.th is further connected via the connection line 202. The capacitor C215 is provided for a redundant bit.

(69) The other ends of the capacitors C213.sub.1, C213.sub.2, C214.sub.1, C214.sub.2, and C215 are connected to the terminals x in the switches SW216.sub.1 to SW216.sub.5, respectively. The switches SW216.sub.1 to SW216.sub.5 are each controlled such that one of terminals a, b, and c is connected to the terminal x by a control signal output from the logic unit 15 (not illustrated).

(70) In the example illustrated in FIG. 4, let a potential difference between the connection points 218.sub.1 and 218.sub.5 (the potential difference between the upper limit voltage VRT and the lower limit voltage VRB) be the voltage VREF, a potential difference between the connection points 2182 and 2184 (the potential difference between the upper limit voltage VRT.sub.2 and the lower limit voltage VRB.sub.2) is a voltage ¼VREF. The connection points 218.sub.1 and 218.sub.5 are connected to the terminals c of the switches SW216.sub.3 to SW216.sub.5. The connection points 218.sub.2 and 218.sub.4 are connected to the terminals c of the switches SW216.sub.1 and SW216.sub.2. The connection point 218.sub.3 is connected to the terminal b of each of the switches SW216.sub.1 to SW216.sub.5.

(71) In the structure illustrated in FIG. 4, the voltage used for generating the threshold voltage V.sub.th includes the two systems, that is, the reference voltage system corresponding to the voltage VREF applying the voltage to the capacitors C214.sub.1, C214.sub.2, and C215, and the reference voltage system corresponding to the voltage ¼VREF applying the voltage to the capacitors C213.sub.1 and C213.sub.2.

(72) This structure allows the capacitors C213.sub.1 and C213.sub.2 in the voltage ¼VREF system and the capacitors C214.sub.1 and C214.sub.2 in the voltage VREF system to have the same capacitance, thereby making it possible to reduce the whole capacitance of the DA converter 12b. The capacitor C215 for the redundant bit needs to have a capacitance double of that of the capacitor C214.sub.2. The capacitance of the capacitor C215, however, can be reduced because the capacitance of the capacitor C214.sub.2 is the same as that of the capacitor C213.sub.2 on the low order bit side.

(73) The AD conversion operation based on the structure illustrated in FIG. 4 is the same as that described with reference FIG. 3. The description thereof is, thus, omitted.

(74) FIG. 5 is a diagram for explaining the AD conversion range in the structure illustrated in FIG. 4 in which the voltages included in the multiple systems are generated from the single voltage. On the left side in FIG. 5, an example of the AD conversion range when the analog gain is high (at a high analog gain) is illustrated. On the right side in FIG. 5, an example of the AD conversion range at a low analog gain is illustrated. In FIG. 5, the ineffective region, which is a value region due to characteristic variations of the pixels and the AD converter, cannot be used for the AD conversion. The ineffective region exists as a circuit characteristic regardless of the AD conversion range. The ineffective region has an equivalent value region both at the low analog gain and at the high analog gain. In general, the AD converters applied to image sensors have a redundant range in the AD conversion range so as to correspond to the value region of the ineffective region.

(75) At the high analog gain, a small voltage range of the pixel signal V.sub.SL is AD converted into a necessary gradation (e.g., 4 bits). The value of 1LSB is small. At the low analog gain, a large voltage range of the pixel signal V.sub.SL is converted while the gradation of the AD conversion is not changed. The value of 1LSB is large. In FIG. 5, 1LSB at the high analog gain and 1LSB at the low analog gain are comparatively illustrated on the left and the right sides.

(76) In the successive approximation type AD converter 10b illustrated in FIG. 4, in each of the switches SW216.sub.1 to SW216.sub.5, the terminal b is connected to the terminal x, thereafter, the connection is switched such that the terminal a is connected to the terminal x, for example. As a result, a voltage (⅛VREF), which is a difference between the intermediate voltage VRC and the upper limit voltage VRT.sub.2, is applied to the capacitors C213.sub.1 and C213.sub.2, resulting in the threshold voltage V.sub.th being increased. To the capacitors C214.sub.1, C214.sub.2, and C215, a voltage (½VREF), which is a difference between the intermediate voltage VRC and the upper limit voltage VRT, is applied, resulting in the threshold voltage V.sub.th being increased.

(77) At the low analog gain, in each of the switches SW216.sub.1 to SW216.sub.5, the terminal c is connected to the terminal x, thereafter, the connection is switched such that the terminal a is connected to the terminal x, for example. As a result, the voltage ¼VREF is applied to the capacitors C213.sub.1 and C213.sub.2 while the voltage VREF is applied to the capacitors C214.sub.1, C214.sub.2, and C215.

(78) In the successive approximation type AD converter 10b illustrated in FIG. 4, the multiple reference voltages (the upper limit voltages VRT and VRT.sub.2, the intermediate voltage VRC, and the lower limit voltages VRB and VRB.sub.2) are generated from the single voltage VDD-ref. At the high analog gain, the redundant range is seen large with respect to an effective signal region (obit V.sub.SL Range), the range of the AD converter is set in such a manner to include a range combining the effective signal region and the redundant range at the high analog gain so as to secure the necessary AD conversion gradation at any analog gain (5 bit ACDC Range). As a result, a redundant range including an extra range and the value region of the ineffective region is set at the low analog gain (refer to the right side in FIG. 5), resulting in the value of the voltage VREF being increased.

(79) In the structure illustrated in FIG. 4, when the capacitances connected to the upper limit voltages VRT and VRT.sub.2, and the lower limit voltages VRB and VRB.sub.2 are connected to the intermediate voltage VRC for resetting the DA converter 12b, and when the capacitances are connected to the upper limit voltages VRT and VRT.sub.2, and the lower limit voltages VRB and VRB.sub.2 from the intermediate voltage VRC in accordance with the control signal from the logic unit 15, the charges of the capacitances are charged and discharged via the switches SW216.sub.1 to SW216.sub.4 and the resistors R217.sub.1 to R217.sub.6 forming the ladder resistance circuit. The structure illustrated in FIG. 3 also operates likewise. As a result, a settling time of the DA converter 12b is determined by the resistances and the capacitances of the charge-discharge path. Particularly, the connection point 218.sub.3, from which the intermediate voltage VRC is taken out and which is the intermediate node of the ladder resistance circuit composed of the resistors R217.sub.1 to R217.sub.6, has a high output impedance. As a result, the settling time of the DA conversion is large.

(80) Exemplary structure of successive approximation type AD converter according to the first embodiment and exemplary processing thereby

(81) The following describes an exemplary structure of a successive approximation type AD converter according to the first embodiment and exemplary processing thereby. FIG. 6 is a diagram illustrating an exemplary basic structure of the successive approximation type AD converter according to the first embodiment. In FIG. 6, this successive approximation type AD converter 10c, which corresponds to each of the successive approximation type AD converters 10.sub.1, 10.sub.2, . . . , 10.sub.n-1, and 10.sub.n illustrated in FIG. 2, includes a plurality of structures each of which generates a plurality of voltages for setting the threshold voltage V.sub.th. The multiple structures each can perform voltage control independently.

(82) In the example illustrated in FIG. 6, the successive approximation type AD converter 10c includes a DA converter 12c, the comparator 14, the logic unit 15, a coupling capacitor 101, and reference voltage generators 102a and 102b. The DA converter 12c includes capacitors C110.sub.1, C110.sub.2, C110.sub.3, and C110.sub.4, and switches SW111.sub.1, 111.sub.2, 111.sub.3, and 111.sub.4. In FIG. 6, the preamplifier unit 13 illustrated in FIG. 2 is omitted. In FIG. 6, the stray capacitance of a connection line 102 is omitted.

(83) The reference voltage generator 102a outputs a voltage VREF-A and generates an upper limit voltage VRT-A, an intermediate voltage VRC-A, and a lower limit voltage VRB-A on the basis of the voltage VREF-A. The reference voltage generator 102b outputs a voltage VREF-B and generates an upper limit voltage VRT-B, an intermediate voltage VRC-B, and a lower limit voltage VRB-B on the basis of the voltage VREF-B. In FIG. 6, the reference voltage generators 102a and 102b are also denoted as a reference voltage generator (A) and a reference voltage generator (B), respectively.

(84) In the reference voltage generator 102a, the voltage VREF-A is supplied to one ends of resistors R1121, R112.sub.2, R112.sub.3, and R112.sub.4 that form a ladder resistance circuit while the other ends of the resistors R112.sub.1, R112.sub.2, R112.sub.3, and R112.sub.4 have ground potential (GND). The upper limit voltage VRT-A, the intermediate voltage VRC-A, and the lower limit voltage VRB-A are taken out from connection point 113.sub.1, 113.sub.2, and 113.sub.3, respectively, connecting the resistors R112.sub.1, R112.sub.2, R112.sub.3 and R112.sub.4.

(85) In the example illustrated in FIG. 6, the reference voltage generator 102b has the same structure as the reference voltage generator 102a. In the reference voltage generator 102b, the voltage VREF-B is supplied to the one ends of resistors R114.sub.1, R114.sub.2, R114.sub.3, and R114.sub.4 that form the ladder resistance circuit while the other ends of the resistors R114.sub.1, R114.sub.2, R114.sub.3, and R114.sub.4 have the ground potential (GND). The upper limit voltage VRT-B, the intermediate voltage VRC-B, and the lower limit voltage VRB-B are taken out from connection point 115.sub.1, 115.sub.2, and 115.sub.3, respectively, connecting the resistors R114.sub.1, R114.sub.2, R114.sub.3 and R114.sub.4.

(86) The capacitors C110.sub.1 and C110.sub.2, each of which is used for generating the threshold voltage V.sub.th, have a capacitance C and a capacitance 2C, respectively, the capacitance C and the capacitance 2C increasing in a binary manner, for example. To one input end of the comparator 14, one ends of the capacitors C110.sub.1 and C110.sub.2 are connected via the connection line 102. The capacitors C110.sub.1 and C110.sub.2 correspond to the conversion on the low order bit side in the AD conversion by the successive approximation type AD converter 10c.

(87) To the one input end of the comparator 14, one ends of the capacitors C110.sub.3 and C110.sub.4 are further connected via the connection line 102. The capacitors C110.sub.3 and C110.sub.4 have the capacitance C and the capacitance 2C, respectively, in the same manner as the capacitors C110.sub.1 and C110.sub.2. The capacitors C110.sub.3 and C110.sub.4 correspond to the conversion on the high order bit side in the AD conversion by the successive approximation type AD converter 10c.

(88) The low order bit side is a low order side (LSB side) of a certain bit position of the bit, for each bit after conversion by the AD conversion. The high order bit side is the bit at a certain bit position and a high order side (MSB side) of the bit, for each bit after conversion by the AD conversion.

(89) The other ends of the capacitors C110.sub.1, C110.sub.2, C110.sub.1, and C110.sub.2 are connected to the terminals x of the switches SW111.sub.1 to SW111.sub.4, respectively. The switches SW111.sub.1 to SW111.sub.4 are controlled by a control signal 103 output from the logic unit 15 such that one of the terminals a, b, and c is connected to the terminal x.

(90) To the terminals a, b, and c of each of the switches SW111.sub.1 and SW1112, the connection points 115.sub.3, 115.sub.2, and 115.sub.1 in the reference voltage generator 102b are connected, respectively. As a result, to the terminals a, b, and c of each of the switches SW111.sub.1 and SW111.sub.2, the upper limit voltage VRT-B, the intermediate voltage VRC-B, and the lower limit voltage VRB-B that are output from the reference voltage generator 102b are supplied, respectively.

(91) In the same manner as described above, to the terminals a, b, and c of each of the switches SW111.sub.3 and SW111.sub.4, the connection points 113.sub.3, 113.sub.2, and 113.sub.1 in the reference voltage generator 102a are connected, respectively. As a result, to the terminals a, b, and c of each of the switches SW111.sub.3 and SW111.sub.4, the upper limit voltage VRT-A, the intermediate voltage VRC-A, and the lower limit voltage VRB-A that are output from the reference voltage generator 102a are supplied, respectively.

(92) As described above, the successive approximation type AD converter 10c according to the first embodiment performs generation and supply of the upper limit voltage VRT, the intermediate voltage VRC, and the lower limit voltage VRB using the two systems, that is, the reference voltage generators 102a and 102b.

(93) FIG. 7 is a diagram illustrating a more concrete structural example of the successive approximation type AD converter according to the first embodiment. A successive approximation type AD converter 10d illustrated in FIG. 7 includes a capacitor C116 and a switch SW117 in addition to the structure of the successive approximation type AD converter 10c illustrated in FIG. 6. The capacitor C116 has a capacitance 4C, the capacitance being increased in a binary manner from that of the capacitor C110.sub.4 having a capacitance 2C and corresponding to the high order side bit. One end of the capacitor C116 is connected to the other input end of the comparator 14 via the connection line 102. The other end of the capacitor C116 is connected to the terminal x of the switch SW117.

(94) To the terminals a, b, and c of the switch SW117, the connection points 113.sub.3, 113.sub.2, and 113.sub.1 of the reference voltage generator 102a are connected, respectively. As a result, to the terminals a, b, and c of the switch SW117, the upper limit voltage VRT-A, the intermediate voltage VRC-A, and the lower limit voltage VRB-A that are output from the reference voltage generator 102a are supplied, respectively.

(95) From the outside of the successive approximation type AD converter 10d, voltage control signals Vctrl.sub.1 and Vctrl.sub.2 are supplied to terminals 104a and 104b, respectively. The voltage control signals Vctrl.sub.1 and Vctrl.sub.2 are supplied from the control unit 1002, for example.

(96) The voltage control signal Vctrl.sub.1 controls the voltage VREF-A generated by the reference voltage generator 102a. The voltage values of the upper limit voltage VRT-A, the intermediate voltage VRC-A, and the lower limit voltage VRB-A that are generated by the reference voltage generator 102a are, thus, controlled by the voltage control signal Vctrl.sub.1. In the same manner as described above, the voltage control signal Vctrl.sub.2 controls the voltage VREF-B generated in the reference voltage generator 102b, thereby controlling the voltage values of the upper limit voltage VRT-B, the intermediate voltage VRC-B, and the lower limit voltage VRB-B.

(97) As described above, the successive approximation type AD converter 10d according to the first embodiment has the two systems for generating the threshold voltage V.sub.th and can independently control the respective voltages output in the respective systems.

(98) FIG. 8 is a diagram for explaining the AD conversion range in the successive approximation type AD converter illustrated in FIG. 7 according to the first embodiment. The terms illustrated in FIG. 8 have the same meanings as those in FIG. 5. The descriptions thereof are omitted.

(99) At the high analog gain, a small voltage range of the pixel signal V.sub.SL is AD converted into a necessary gradation (e.g., 4 bits). The value of 1LSB is small. At the low analog gain, a large voltage range of the pixel signal V.sub.SL is converted while the gradation of the AD conversion is not changed. The value of 1LSB is large.

(100) With reference to FIG. 7, a potential difference between the upper limit voltage VRT-A and the lower limit voltage VRB-A is a voltage VREF (1) in the reference voltage generator 102a while a potential difference between the upper limit voltage VRT-B and the lower limit voltage VRB-B is a voltage VREF (2) in the reference voltage generator 102b. The voltage VREF is equal to the voltage VREF (1).

(101) At the high analog gain (18 dB) on the left side in FIG. 8, the voltages VREF-A and VREF-B are adjusted to satisfy that the voltage VREF (2)=¼×VREF. At the low analog gain, the voltages VREF-A and VREF-B are adjusted to satisfy that the voltage VREF (1)=4×VREF. As a result, the AD conversion range at the high analog gain and the AD conversion range at the low analog gain that are illustrated in FIG. 8 can be achieved.

(102) In the example illustrated in FIG. 8, for the redundant range serving as the common ineffective region at the low analog gain and the high analog gain, 1LSB is allocated at the low analog gain while 8LSB is allocated at the high analog gain. As a result, the necessary range of the AD converter at the high analog gain is 5 bits while the range of the AD converter at the low analog gain is 4.2 bits.

(103) In the example illustrated in FIG. 7, when the voltage value of the voltage VREF-A that is in the reference voltage generator 102a system and corresponds to the high order bit side is changed from four times to two times of the voltage value of the voltage VREF-B on the low order bit side, the amplitude of the final bit of the high order bit (the least significant bit on the high order bit side) becomes equal to the amplitude of the top bit of the low order bit (the most significant bit on the low order bit side). As a result, the final bit of the high order bit and the top bit of the low order bit overlap with each other. The top bit of the low order bit can be used as the redundant bit. In this case, a dynamic range (the AD conversion range) is half that before the change. In the structure illustrated in FIG. 7, a voltage value setting width of the voltage VREF-A output by the reference voltage generator 102a may be set to any voltage value equal to or smaller than four times of the voltage value of the voltage VREF-B output by the reference voltage generator 102b.

(104) In the structure illustrated in FIG. 7, when the top bit on the low order bit side is the redundant bit, the redundant bit becomes an effective bit by setting the voltage value of the voltage VREF-A, which is the output voltage of the reference voltage generator 102a system, to a voltage value four times of the voltage value of the voltage VREF-B, which is the output voltage of the reference voltage generator 102b system corresponding to the low order bit side. As a result, the dynamic range is doubled.

(105) The successive approximation type AD converter 10d according to the first embodiment has the two systems each of which independently generates and outputs the voltages used for setting the threshold voltage V.sub.th. This makes it possible to dynamically control the dynamic range of the AD conversion while 1LSB is maintained without change in the number of conversion bits determined by the circuit structure and change in the structure of the capacitive DA converter. As a result, the range of the necessary reference voltage is reduced, thereby making it possible to reduce the reference voltage.

(106) In the successive approximation type AD converter 10d according to the first embodiment, the reference voltage generator 102a generates the reference voltages on the high order bit side, and the reference voltage generator 102b generates the reference voltages on the low order bit side, resulting in charges being supplied to the capacitances for the respective bits in the DA converter 12d. This reduces loads of the reference voltage generators 102a and 102b as compared with a case where all capacitances are connected to a single system reference voltage generator. As a result, settling is improved.

(107) A case is examined where a current flowing in the resistors R112.sub.1 to R112.sub.4 that form the ladder resistance circuit in the reference voltage generator 102a on the high order bit side, and a current flowing in the resistors R114.sub.1 to R114.sub.4 that form the ladder resistance circuit in the reference voltage generator 102b on the low order bit side are equal. In this case, in the example illustrated in FIG. 7, the resistance value of the resistors R114.sub.1 to R114.sub.4 is one fourth of the resistance value of the resistors R112.sub.1 to R112.sub.4 because the voltage value of the voltage VREF-B generated by the reference voltage generator 102b is one fourth of the voltage value of the voltage VREF-A generated by the reference voltage generator 102a. The output impedance viewed from the respective connection points 115.sub.1 to 115.sub.3 can be reduced, thereby improving the settling at low order bit transition.

(108) When the successive approximation type AD converter 10d is applied to an imaging device, the low analog gain and the high analog gain can be set by the exposure control by the control unit 1002 in accordance with the value of the digital signal output of the successive approximation type AD converter 10d, for example. For example, when a subject is dark, the analog gain is set to be high to increase an exposure time while when a subject is bright, the analog gain is set to be low to reduce the exposure time. As a possible example of such a case, the low analog gain is set when an average of luminance values calculated on the basis of the values obtained by the AD conversion of the analog pixel signals of all pixels included in the pixel array unit 2 is equal to or larger than a predetermined value while the high analog gain is set when the average is smaller than the predetermined value.

(109) Determination Error Correction Using Redundant bit

(110) The following roughly describes determination error correction using the redundant bit, the determination error correction being applicable to the first embodiment. FIGS. 9A and 9B illustrate examples when the redundant bit is not used. FIG. 9C illustrates an example when the redundant bit is used.

(111) In FIGS. 9A to 9C, the lower limit voltage VRB=0, the upper limit voltage VRT=V, and an analog voltage value of the input signal is converted into a digital value represented by 3 bits, for the purpose of explanation. For each bit, the threshold voltage V.sub.th used for determination of the bit is indicated with the dotted line, and the solid line frame having the dotted line as its center indicates a determination range used for determination of the threshold voltage V.sub.th by the comparator 14, for example.

(112) The successive approximation type AD converter compares a comparison target with the threshold voltage V.sub.th. For example, when the comparison target>the threshold voltage V.sub.th, the bit value is set to be “1” while when the comparison target<the threshold voltage V.sub.th, the bit value is set to be “0”. When the bit value is “1”, the threshold voltage V.sub.th for the next bit (the bit lower by one bit with respect to the previous bit) is obtained as V.sub.pre+½×V.sub.pre where V.sub.pre is the previous threshold voltage V.sub.th. When the bit value is “0”, the threshold voltage V.sub.th for the next bit is obtained as V.sub.pre−½×V.sub.pre. In the successive approximation type AD converter, the threshold voltage V.sub.th is set in accordance with a conversion history of the bit having been converted before the bit serving as a conversion target.

(113) FIG. 9A illustrates an example of the AD conversion when no bit determination error exists. At bit (n+1), the comparison target and the threshold voltage V.sub.th=½V are compared. The value of bit (n+1) is set to be “0” because “the threshold voltage V.sub.th>the comparison target”. The threshold voltage V.sub.th for next bit n is obtained as V.sub.th=½V−½×(½V)=¼V. At bit n, the comparison target and the threshold voltage V.sub.th=¼V are compared. The value of the bit n is set to be “1” because “the threshold voltage V.sub.th<the comparison target”. The threshold voltage V.sub.th for next bit n is obtained as V.sub.th=¼V+½×(¼V)=⅜V. At bit (n−1), the comparison target and the threshold voltage V.sub.th=⅜V are compared. The value of bit (n−1) is set to be “0” because “the threshold voltage V.sub.th>the comparison target”. The AD conversion result of the comparison target is obtained as “010”, which is represented by 3 bits.

(114) In accordance with the determination result that “the threshold voltage V.sub.th>the comparison target” of bit (n−1), the threshold voltage V.sub.th for next bit (n−2) (not illustrated) is calculated as V.sub.th=⅜V+½×(⅜V)= 5/16V. A difference between the threshold voltage V.sub.th= 5/16V and the voltage value of the comparison target is a conversion error. In this case, the error factor of the conversion error is a quantization error.

(115) FIG. 9B illustrates an example when the determination error occurs at bit (n+1) in the determination in FIG. 9A and the bit value is set to be “1”. In this case, the threshold voltage V.sub.th for next bit n is obtained as V.sub.th=½V+½×(½V)=¾V. The value of bit n is set to be “0” because “the threshold voltage V.sub.th>the comparison target”. The threshold voltage V.sub.th for next bit (n−1) is obtained as V.sub.th=¾V+½×(¾V)=⅝V. The value of bit n is set to be “0” because “the threshold voltage V.sub.th>the comparison target”. In this case, the AD conversion result of the comparison target is “100”, which differs from the value of the example in FIG. 9A.

(116) In accordance with the determination result that “the threshold voltage V.sub.th>the comparison target” of bit (n−1), the threshold voltage V.sub.th for next bit (n−2) (not illustrated) is calculated as V.sub.th=⅝V+½×(⅝V)= 9/16V. A difference between the threshold voltage V.sub.th= 9/16V and the voltage value of the comparison target is the conversion error. From FIG. 9B, it is understood that the conversion error becomes larger than that of the example in FIG. 9A.

(117) FIG. 9C illustrates an example where a determination using the redundant bit n′ is applied to bit n in the example where the determination error occurs on bit (n+1) in FIG. 9B. In FIG. 9C, the redundant range of the redundant bit n′ is indicated with oblique lines. The redundant bit can reduce the determination error by 0.5×redundant bit weight. In the example illustrated in FIG. 9C, determination is performed by expanding the determination range with the redundant range by half the determination range of bit n, in relation to the determination error on bit (n+1) in FIG. 9B.

(118) In FIG. 9C, the threshold voltage V.sub.th for bit n′ (redundant bit) is changed to ½V from ¾V, which is the threshold voltage V.sub.th for bit n, which is the previous bit of bit n′. In this case, the value of bit n′ is set to be “0” because “the threshold voltage V.sub.th>the comparison target”. The threshold voltage V.sub.th for next bit (n−1) is obtained as V.sub.th=½V−½×½×(½V)=⅜V. The value of bit n is set to be “0” because “the threshold voltage V.sub.th>the comparison target”. In this case, the result of the AD conversion of the comparison target is “100” based on the employment of the determination result according to the redundant bit n′.

(119) In accordance with the determination result that “the threshold voltage V.sub.th>the comparison target” of bit (n−1), the threshold voltage V.sub.th for next bit (n−2) (not illustrated) is calculated as V.sub.th=⅜V+½×(⅜V)= 5/16V. A difference between the threshold voltage V.sub.th= 5/16V and the voltage value of the comparison target is the conversion error. As illustrated in FIG. 9C, the conversion error is smaller than that of the example illustrated in FIG. 9B and is equal to that of the case where no error occurs illustrated in FIG. 9A.

(120) More concrete example of AD conversion according to the first embodiment

(121) The following describes a more concrete example of the AD conversion according to the first embodiment with reference to FIGS. 10 and 11. In the successive approximation type AD converter 10d according to the first embodiment, when the reference voltage range is minimized as illustrated in FIG. 8, the number of bits of the successive approximation type AD converter 10d is an integer that can include necessary AD conversion range. At the low analog gain illustrated on the left side in FIG. 8, the necessary AD conversion range is 4.2 bits. The successive approximation type AD converter 10d has the AD conversion range of 5 bits. The difference of 0.8 bits can be allocated as the redundant bit. FIGS. 10 and 11 are examples that can achieve high resolution and redundant range expansion by switching of reference voltage ranges in the AD conversion according to the first embodiment. The terms illustrated in FIGS. 10 and 11 have the same meanings as those in FIGS. 9A to 9C. The descriptions thereof are omitted.

(122) FIG. 10 is a diagram illustrating an example of the AD conversion that can achieve high resolution and is applicable to the first embodiment. FIG. 10 illustrates an example of the AD conversion that achieves high resolution using all bits as the effective bits with a condition where the voltage VREF (1) serving as the reference voltage on the high order bit side is four times as large as VREF (2) serving as the reference voltage on the low order bit side. FIG. 10 illustrates an example of the AD conversion where no bit determination error occurs.

(123) At bit (n+1) in FIG. 10, the comparison target and the threshold voltage V.sub.th=½V are compared. The value of bit (n+1) is set to be “0” because “the threshold voltage V.sub.th>the comparison target”. The threshold voltage V.sub.th for next bit n is obtained as V.sub.th=½V−½×(½V)=¼V. At bit n, the comparison target and the threshold voltage V.sub.th=¼V are compared. The value of bit n is set to be “1” because “the threshold voltage V.sub.th<the comparison target”. The threshold voltage V.sub.th for next bit n′ is obtained as V.sub.th=¼V+½×(¼V)=⅜V. At bit n′, the comparison target and the threshold voltage V.sub.th=⅜V are compared. The value of bit n′ is set to be “0” because “the threshold voltage V.sub.th>the comparison target”. The threshold voltage V.sub.th for next bit (n−1) is obtained as V.sub.th=⅜V−½×(¾V)= 5/16V. At bit (n−1), the comparison target and the threshold voltage V.sub.th= 5/16V are compared. The value of bit (n−1) is set to be “0” because “the threshold voltage V.sub.th>the comparison target”. The AD conversion result of the comparison target is obtained as “0100”, which is represented by 4 bits.

(124) In accordance with the determination result that “the threshold voltage V.sub.th>the comparison target” of bit (n−1), the threshold voltage V.sub.th for next bit (n−2) (not illustrated) is calculated as V.sub.th= 5/16V+½×( 5/16V)= 9/32V. A difference between the threshold voltage V.sub.th= 9/32V and the voltage value of the comparison target is a conversion error.

(125) FIG. 11 is a diagram illustrating an example where the AD conversion is performed by expanding the redundant range, the AD conversion being applicable to the first embodiment. FIG. 11 illustrates an example of the AD conversion when the redundant range is expanded by widening the overlapping range of the reference voltages generated by the reference voltage generators 102a and 102b with a condition where the voltage VREF (1) serving as the reference voltage on the high order bit side is twice as large as the voltage VREF (2) serving as the reference voltage on the low order bit side. In this case, 1 bit out of 4 bits of the AD conversion range is allocated as the redundant bit. FIG. 11 illustrates an example of the AD conversion when a bit determination error exists and the determination error is corrected by the redundant bit.

(126) FIG. 11 illustrates an example where the determination using the redundant bit n′ is applied to bit n in the example where the determination error occurs on bit (n+1). In the example illustrated in FIG. 11, the determination is performed by expanding the determination range with the redundant range by half the determination range of bit n, in relation to the determination error on bit (n+1).

(127) In FIG. 11, the determination error occurs on bit (n+1), and the bit value, which is originally determined to be “0”, is determined to be “1”. In this case, the threshold voltage V.sub.th for next bit n is obtained as V.sub.th=½V+½×(½V)=¾V. The value of bit n is set to be “0” because “the threshold voltage V.sub.th>the comparison target”.

(128) The threshold voltage V.sub.th for next bit n′(the redundant bit n′) is obtained as V.sub.th=½V, and the value of bit n′ is set to be “0” because “the threshold voltage V.sub.th>the comparison target”. The threshold voltage V.sub.th for next bit (n−1) is obtained as V.sub.th=½V−½×½×(½V)=⅜V. The value of bit n bit is set to be “0” because “the threshold voltage V.sub.th>the comparison target”. In this case, the result of the AD conversion of the comparison target is “100” based on the employment of the determination result according to the redundant bit n′.

(129) In accordance with the determination result that “the threshold voltage V.sub.th>the comparison target” of bit (n−1), the threshold voltage V.sub.th for next bit (n−2) (not illustrated) is calculated as V.sub.th=⅜V+½×(⅜V)= 5/16V. A difference between the threshold voltage V.sub.th= 5/16V and the voltage value of the comparison target is a conversion error.

(130) As described above, the successive approximation type AD converter 10d according to the first embodiment generates the reference voltages of two systems by the reference voltage generators 102a and 102b each of which allows the voltages to be controlled, thereby making it possible to switch high resolution and expansion of the redundant range. The AD conversion can be performed adaptively in accordance with the use such as the use at the high analog gain or the use at the low analog gain.

(131) Reduction of Variance of Reference Voltage Among Multiple Systems

(132) When a plurality of systems that generate and supply reference voltages are included, it is necessary to reduce variance among the systems. FIGS. 12A and 12B are diagrams illustrating more specifically the structures of the reference voltage generators 102a and 102b, which are applicable to the first embodiment. In the example illustrated in FIG. 12A, the reference voltage generator 102a is structured using a feedback amplifier 120a, source follower transistors TR121a, TR130a.sub.1, TR130a.sub.2, TR130a.sub.3, TR130a.sub.4, . . . , and reference resistors ΔR_A having a resistance value of ΔR_A.

(133) A positive input end of the feedback amplifier 120a receives the voltage VREF-A and an output end of the feedback amplifier 120a is connected to a gate of the source follower transistor TR121a. A source of the transistor TR121a is connected to the ground potential (GND) via a connection point CP.sub.00A and the four reference resistors ΔR_A, and connected to a negative input terminal of the feedback amplifier 120a. A voltage Vgs-A is a gate-source voltage of the transistor TR121a. The upper limit voltage VRT-A, the intermediate voltage VRC-A, and the lower limit voltage VRB-A are taken out from connection points CP.sub.01A, CP.sub.02A, and CP.sub.03A, respectively, which connect the four reference resistors ΔR_A.

(134) Hereinafter, a structure composed of the feedback amplifier 120a, the transistor TR121a, and the four reference resistors ΔR_A connected to the source of the transistor TR121a via the connection point CP.sub.00A is called a voltage generation unit (A) as appropriate.

(135) The output end of the feedback amplifier 120a is connected to the gates of the source follower transistors TR130a.sub.1, TR130a.sub.2, . . . , corresponding to the respective AD converters (e.g., the successive approximation type AD converters 10d) in a column direction. The sources of the transistors TR130a.sub.1, TR130a.sub.2, . . . , are each connected to the ground potential (GND) via the four reference resistors ΔR_A.

(136) The structure illustrated in FIG. 12A allows the structure of the voltage generation unit (A) to be provided outside the successive approximation type AD converters 10d. In this case, the transistors TR130a.sub.1, TR130a.sub.2, . . . , and the four reference resistors ΔR_A connected to the respective transistors TR130a.sub.1, TR130a.sub.2, . . . , are each included in the reference voltage generator 102a included in the respective successive approximation type AD converters 10.sub.1, 10.sub.2, . . . , 10.sub.n-1, and 10.sub.n, illustrated in FIG. 2, each of which corresponds to the column, that is, the successive approximation type AD converter 10d.

(137) In each column, the upper limit voltage VRT-A is taken out from each of the connection points CP.sub.11A, CP.sub.21A, CP.sub.31A, and CP.sub.41A, the intermediate voltage VRC-A is taken out from each of the connection points CP.sub.12A, CP.sub.22A, CP.sub.32A, and CP.sub.42A, and the upper limit voltage VRT-A is taken out from each of the connection points CP.sub.13A, CP.sub.23A, CP.sub.33A, and CP.sub.43A.

(138) In this case, for reducing variance of the upper limit voltage VRT-A, the intermediate voltage VRC-A, and the lower limit voltage VRB-A among the columns, the connection points CP.sub.01A, CP.sub.02A, and CP.sub.03A are connected to the connection points having the same potential in each column, respectively, out of the connection points CP.sub.11A to CP.sub.43A. In the example illustrated in FIG. 12A, the connection points CP.sub.01A, CP.sub.11A, CP.sub.21A, CP.sub.31A, and CP.sub.41A are connected, the connection points CP.sub.02A, CP.sub.12A, CP.sub.22A, CP.sub.32A, and CP.sub.42A are connected, and the connection points CP.sub.03A, CP.sub.13A, CP.sub.23A, CP.sub.33A, and CP.sub.43A are connected. Furthermore, the connection point CP.sub.00A may be connected to the respective sources of the transistors TR130a.sub.1, TR130a.sub.2, . . . , in the respective columns.

(139) The connection points having the same potential are connected one another as described above, thereby reducing the variance of the gate-source voltage Vgs_A among the transistors TR121a, TR130a.sub.1, TR130a.sub.2, . . . , and the variance among the reference resistors ΔR_A.

(140) The reference voltage generator 102b has the same structure as described above. The reference voltage generator 102b includes a feedback amplifier 120b, source follower transistors TR121b, TR130b.sub.1, TR130b.sub.2, TR130b.sub.3, TR130b.sub.4, . . . , and a reference resistors ΔR_B having a resistance value of ΔR_B. The structure of the reference voltage generator 102b is the same as that of the reference voltage generator 102a described with reference to FIG. 12A. The detailed description thereof is omitted.

(141) Hereinafter, a structure composed of the feedback amplifier 120b, the transistor TR121b, and the four reference resistors ΔR_A connected to the source of the transistor TR121b via a connection point CP.sub.00B is called a voltage generation unit (B) as appropriate.

(142) In the reference voltage generator 102b, in the same manner as the reference voltage generator 102a, for reducing variance of the upper limit voltage VRT-B, the intermediate voltage VRC-B, and the lower limit voltage VRB-B among the columns, connection points CP.sub.01B, CP.sub.02B, and CP.sub.03B are connected to the connection points having the same potential out of the connection points CP.sub.11B to CP.sub.43B in the columns. In the example illustrated in FIG. 12A, the connection points CP.sub.01B, CP.sub.11B, CP.sub.21B, CP.sub.31B, and CP.sub.41B are connected, the connection points CP.sub.02B, CP.sub.12B, CP.sub.22B, CP.sub.32B, and CP.sub.42B are connected, and the connection points CP.sub.03B. CP.sub.13B, CP.sub.23B, CP.sub.33B, and CP.sub.43B are connected. Furthermore, the connection point CP.sub.00B may be connected to the sources of the transistors TR130b.sub.1, TR130b.sub.2, . . . , in the columns.

(143) The connection points having the same potential are connected one another as described above, thereby reducing the variance of the gate-source voltage Vgs_B among the transistors TR121b, TR130b.sub.1, TR130b.sub.2, . . . , and the variance among the reference resistors ΔR_A in the example illustrated in FIG. 12B.

(144) The variance between the respective systems, that is, the reference voltage generators 102a and 102b is not reduced. The two feedback amplifiers 120a and 120b are included. A difference between the offset voltages Vofst_A and Vofst_B, thus, becomes a problem.

(145) FIG. 13 is a diagram illustrating a first example of a structure that can reduce the variance among a plurality of systems and is applicable to the first embodiment. In FIG. 13, the voltage generation unit (A) is illustrated in the reference voltage generator 102a while a part of the voltage generation unit (B) is illustrated in the reference voltage generator 102b. The structures of the respective columns are the same as those in FIGS. 12A and 12B. The descriptions thereof are, thus, omitted to avoid complicated illustration. In FIG. 13, the structure from the connection point CP.sub.02B in the voltage generation unit (B) of the reference voltage generator 102b to the ground potential is omitted.

(146) In the structure illustrated in FIG. 13, the connection points having the same potential are connected one another in the voltage generation units (A) and (B). In the example illustrated in FIG. 13, the connection point CP.sub.03A of the voltage generation unit (A) and the connection point CP.sub.01B of the voltage generation unit (B) have the same potential and are connected each other via a resistor R.sub.short. This makes it possible to reduce a variance between the gate source voltage Vsg_A of the transistor TR121a and the gate source voltage Vsg_B of the transistor TR121b, a variance between the reference resistors ΔR_A and ΔR_B, and a variance between the offset voltage Vofst_A of the feedback amplifier 120a and the offset voltage Vofst_B of the feedback amplifier 120b, between the systems.

(147) In the first embodiment, the reference voltage generators 102a and 102b can independently change the reference voltages. With a change in reference voltage, the connection destinations are changed as illustrated with the dotted lines in FIG. 13. Such control can be performed by the control unit 1002, for example.

(148) FIG. 14 is a diagram illustrating a second example of the structure that can reduce the variance among a plurality of systems and is applicable to the first embodiment. In FIG. 14, the voltage generation unit (A) is illustrated in the reference voltage generator 102a while a part of the voltage generation unit (B) is illustrated in the reference voltage generator 102b. The structures of the respective columns are the same as those in FIGS. 12A and 12B. The descriptions thereof are, thus, omitted to avoid complicated illustration. In FIG. 13, the structure from the connection point CP.sub.02B in the voltage generation unit (B) of the reference voltage generator 102b to the ground potential is omitted.

(149) In the structure illustrated in FIG. 14, the reference voltage generator 102b does not include the feedback amplifier 120b, and a voltage generation unit (B)′, which corresponds to the voltage generation unit (B), is structured by a transistor TR122 and the multiple reference resistors ΔR_B connected to the source of the transistor TR122 via the connection point CP.sub.02B.

(150) When a source current iA of the transistor TR121a in the voltage generation unit (A) and a source current iB of the transistor TR122 in the voltage generation unit (B)′ are equal, the gate-source voltage Vgs_A of the transistor TR121a and the gate-source voltage Vgs_B of the transistor TR122 are equal.

(151) In the structure illustrated in FIG. 14, a sample hold circuit composed of switches SW1511 and SW1512, and a capacitor C150 is provided between the reference voltage generators 102a and 102b, for example. The sample hold circuit acquires the gate-source voltage Vgs_A of the transistor TR121a and supplies the acquired gate-source voltage Vgs_A to the gate and the source of the transistor TR122 in the voltage generation unit (B)′ of the reference voltage generator 102b. As a result, the gate-source voltage Vgs_B of the transistor TR122 is equal to the gate-source voltage Vgs_A of the transistor TR121a.

(152) This structure makes it possible to eliminate the feedback amplifier 120b of the reference voltage generator 102b. As a result, the variance between the offset voltage Vofst_A of the feedback amplifier 120a and the offset voltage Vofst_B of the feedback amplifier 120b, which is described with reference to FIGS. 12A and 12B, can be eliminated.

(153) The first example described with reference to FIG. 13 and the second example described with reference to FIG. 14 can be combined and the resulting combination can also be applied to the successive approximation type AD converter 10d according to the first embodiment.

Second Embodiment

(154) The following describes a second embodiment. In the first embodiment described above, the successive approximation type AD converter 10d according to the disclosure is applied to the solid state imaging element 1 that outputs image data according to irradiation light. The application is not limited to this example. The second embodiment is an example where the successive approximation type AD converter 10d according to the disclosure is applied to an indirect ToF method range image sensor that measures a distance by an indirect ToF method.

(155) The indirect ToF method is a technique in which light source light (e.g., laser light in an infrared region) modulated by pulse width modulation (PWM), for example, is emitted to a measurement target, reflected light from the measurement target is received by a light receiving element, and a distance to the measurement target is measured on the basis of a phase difference between the received reflected light and the light source light. In the indirect ToF method, a distance is measured on the basis of a ratio of a time in which reflected light of light source light is received in an off period in the PWM of light source light to a sum of a time in which reflected light of light source light is received in an on period in the PWM of light source light and the time in which the reflected light of the light source light is received in the off period just after the on period, for example.

(156) FIG. 15 is a diagram roughly illustrating an exemplary structure of an indirect ToF method range image sensor applicable to the second embodiment. In FIG. 15, an indirect ToF method range image sensor 10000 has a layered structure including a sensor chip 10001 and a circuit chip 10002 layered on the sensor chip 10001. In the layered structure, the sensor chip 10001 and the circuit chip 10002 are electrically connected via connection portions (not illustrated) such as via (VIA) connections and Cu-Cu connections. In the example illustrated in FIG. 15, a state is illustrated in which wiring lines of the sensor chip 10001 and the wiring lines of the circuit chip 10002 are connected by the connection portions.

(157) A pixel area 10020 includes a plurality of pixels 10230 arranged in an array shape on the sensor chip 10001 with a two-dimensional grid pattern. Each of the pixels 10230 arranged in the pixel area 10020 can receive infrared light, for example, and performs photoelectric conversion on the basis of the received infrared light to output an analog pixel signal. To each of the pixels 10230 included in the pixel area 10020, two vertical signal lines 10200 and 10300 are connected.

(158) In the indirect ToF method range image sensor 10000, a vertical drive circuit 10010, a column signal processing unit 10040, a timing control circuit 10050, and an output circuit 10060 are arranged in the circuit chip 10002.

(159) The timing control circuit 10050 controls the driving timing of the vertical drive circuit 10010 in accordance with an external control signal 10049. The timing control circuit 10050 generates a vertical synchronization signal on the basis of the control signal 10049. The column signal processing unit 10040 and the output circuit 10060 perform respective pieces of processing in synchronization with the vertical synchronization signal generated by the timing control circuit 10050.

(160) The vertical signal lines 10200 and 10300 are wired for each column of the pixels 10230 in the vertical direction in FIG. 15. When the total number of columns in the pixel area 10020 is M columns (M is an integer equal to or larger than one), 2×M number of vertical signal lines are wired in total in the pixel area 10020. Each pixel 10230 includes two taps TAP_A and TAP_B that store therein charges generated by photoelectric conversion, which are described later in detail. The vertical signal line 10200 is connected to the tap TAP_B of the pixel 10230 while the vertical signal line 10300 is connected to the tap TAP_A of the pixel 10230.

(161) To the vertical signal line 10200, a pixel signal AIN.sub.P1, which is an analog pixel signal based on the charges in the tap TAP_B of the pixel 10230 in the corresponding pixel column, is output. To the vertical signal line 10300, a pixel signal AIN.sub.P2, which is an analog pixel signal based on the charges in the tap TAP_A of the pixel 10230 in the corresponding pixel column, is output.

(162) The vertical drive circuit 10010 drives the pixels 10230 included in the pixel area 10020 on a pixel row basis in accordance with the timing control by the timing control circuit 10050 to cause each pixel 10230 to output the pixel signals AIN.sub.P1 and AIN.sub.P2. The pixel signals AIN.sub.P1 and AIN.sub.P2 output from each pixel 10230 are supplied to the column signal processing unit 10040 via the vertical signal line 10300 and 10200 in each column.

(163) The column signal processing unit 10040 includes a plurality of AD converters provided for each pixel column corresponding to the pixel column in the pixel area 10020, for example. Each AD converter included in the column signal processing unit 10040 performs AD conversion on the pixel signal AIN.sub.P1 and AIN.sub.P2 supplied via the vertical signal lines 10300 and 10200, and supplies the pixel signal AIN.sub.P1 and AIN.sub.P2 having been converted into digital signals to the output circuit 10060.

(164) The output circuit 10060 performs signal processing such as correlated double sampling (CDS) processing on the pixel signal AIN.sub.P1 and AIN.sub.P2 that have been output from the column signal processing unit 10040 and converted into the digital signals, and outputs the pixel signal AIN.sub.P1 and AIN.sub.P2 after the signal processing to a signal processing circuit on a rear stage via an output line 10120.

(165) FIG. 16 is a circuit diagram illustrating an exemplary structure of the pixel 10230 applicable to the second embodiment. The pixel 10230 includes a photo diode 10231, two transfer transistors 10232 and 10237, two reset transistors 10233 and 10238, two floating diffusion layers 10234 and 10239, two amplifier transistors 10235 and 10240, and two select transistors 10236 and 10241. The floating diffusion layers 10234 and 10239 correspond to the taps TAP_B and TAP_A, respectively.

(166) The photo diode 10231 is a light receiving element that performs photoelectric conversion on received light to generate charges. The photo diode 10231 is disposed on a rear surface opposite a surface that is a face on which circuits are arranged of a semiconductor substrate. Such a solid state imaging element is called a rear surface irradiation type solid state imaging element. Instead of the rear surface irradiation type, a surface irradiation type structure can be used in which the photo diode 10231 is disposed on the surface.

(167) An overflow transistor 10242, which is connected between a cathode of the photo diode 10231 and a power supply line VDD, has a function to reset the photo diode 10231. The overflow transistor 10242 turns on in response to an overflow gate signal OFG supplied from the vertical drive circuit 10010 to sequentially output charges in the photo diode 10231 to the power supply line VDD.

(168) The transfer transistor 10232 is connected between the cathode of the photo diode 10231 and the floating diffusion layer 10234. The transfer transistor 10237 is connected between the cathode of the photo diode 10231 and the floating diffusion layer 10239. The transfer transistors 10232 and 10237 sequentially transfer charges generated by the photo diode 10231 to the floating diffusion layers 10234 and 10239, respectively, in response to transfer signals TRG supplied from the vertical drive circuit 10010.

(169) The floating diffusion layers 10234 and 10239, which correspond to the tap TAP_B and TAP_A, respectively, store therein charges transferred from the photo diode 10231, covert the charges into the analog signals having voltage values according to the amount of the stored charges, and generate the pixel signals AIN.sub.P2 and AIN.sub.P1, respectively.

(170) The two reset transistors 10233 and 10238 are connected between the power supply line VDD and the floating diffusion layers 10234 and 10239, respectively. The reset transistors 10233 and 10238 turn on in response to reset signals RST and RST.sub.P that are supplied from the vertical drive circuit 10010 to pull out charges from the floating diffusion layers 10234 and 10239, respectively, thereby initializing the floating diffusion layers 10234 and 10239.

(171) The two amplifier transistors 10235 and 10240 are connected between the power supply line VDD and the select transistors 10236 and 10241, respectively. Each of the amplifier transistors 10235 and 10240 amplifies the voltage signal having a voltage converted from charges by the floating diffusion layers 10234 and 10239, respectively.

(172) The select transistor 10236 is connected between the amplifier transistor 10235 and the vertical signal line 10200 (VSL.sub.2). The select transistor 10241 is connected between the amplifier transistor 10240 and the vertical signal line 10300 (VSL.sub.1). The select transistors 10236 and 10241 turn on in response to selection signals SEL and SEL.sub.P that are supplied from the vertical drive circuit 10010 to output the pixel signals AIN.sub.P2 and AIN.sub.P1 that have been amplified by the amplifier transistors 10235 and 10240, respectively, to the vertical signal line 10200 (VSL.sub.2) and the vertical signal line 10300 (VSL.sub.1), respectively.

(173) The vertical signal line 10200 (VSL.sub.2) and the vertical signal line 10300 (VSL.sub.1) connected to the pixel 10230 are connected, for each pixel column, to the input end of a single AD converter included in the column signal processing unit 10030. The vertical signal line 10200 (VSL.sub.2) and the vertical signal line 10300 (VSL.sub.1) supply, for each pixel column, the pixel signals AIN.sub.P2 and AIN.sub.P1 that are output from the pixel 10230 to the AD converter included in the column signal processing unit 10040.

(174) The circuit structure of the pixel 10230 is not limited to that illustrated in FIG. 16. Any circuit structure is acceptable that can generate the pixel signals AIN.sub.P1 and AIN.sub.P2 by photoelectric conversion.

(175) As an example of application to the indirect ToF method, a period of the PWM signal driving a light source (not illustrated), and the overflow gate signal OFG, the transfer signal TRG, the reset signals RST and RST.sub.P, and the select signals SEL and SEL.sub.P are synchronized to switch output of the pixel signals AIN.sub.P1 and AIN.sub.P2 in the on period and the off period of the PWM signal. As a result, the structures illustrated in FIGS. 15 and 16 can achieve the operation of the indirect ToF method range image sensor.

(176) In the structure of the indirect ToF method range image sensor 10000 illustrated in FIGS. 15 and 16, the technique according to the disclosure is applicable to the respective AD converters included in the column signal processing unit 10040. The successive approximation type AD converter 10d described in the first embodiment can be applied to the respective AD converters included in the column signal processing unit 10040 illustrated in FIG. 15.

(177) The effects described in the specification are only represented by way of example, and are not limited to those. Other effects may be included.

(178) The technique can also include the following structures.

(179) Claims

(180) (1) A solid state imaging element, comprising:

(181) a converter that converts an analog pixel signal read out from a pixel into a bit value, successively for each of a plurality of bits, on the basis of a threshold voltage set according to a conversion history of the bit converted before a target bit; a plurality of voltage generation units that each generate a plurality of reference voltages; and a setting unit that sets the threshold voltage using the reference voltage selected from the reference voltages generated by each of the voltage generation units on the basis of the conversion history.
(2) The solid state imaging element according to the above (1), wherein the voltage generation units include: a first voltage generation unit that generates the reference voltages for conversion by the converter from the analog pixel signal into the bit value of the bit on a high order side; and a second voltage generation unit that generates the reference voltages for conversion by the converter from the analog pixel signal into the bit value of the bit on a low order side.
(3) The solid state imaging element according to the above (2), wherein the second voltage generation unit generates a plurality of reference voltages having a voltage range overlapping with the reference voltages generated by the first voltage generation unit, and the setting unit sets the threshold voltage by changing the reference voltage selected on the basis of the conversion history on the basis of the reference voltage included in the voltage range.
(4) The solid state imaging element according to the above (3), wherein the second voltage generation unit generates the reference voltages such that two or more reference voltages are included in the voltage range when a gain with respect to the analog pixel signal is equal to or larger than a certain value.
(5) The solid state imaging element according to the above (3), wherein the second voltage generation unit generates the reference voltages such that a single reference voltage is included in the voltage range when a gain with respect to the analog pixel signal is smaller than a certain value.
(6) The solid state imaging element according to any one of the above (1) to (5), wherein, out of connection points from which the reference voltages generated by each of the voltage generation units are taken out, respectively, the connection points having identical potential are connected one another.
(7) The solid state imaging element according to any one of the above (1) to (6), further comprising a sample hold unit that samples the voltage generated by one of the voltage generation units and supplies the sampled voltage to another of the voltage generation units.
(8) An electronic apparatus, comprising: a solid state imaging element that includes a converter that converts an analog pixel signal read out from a pixel into a bit value, successively for each of a plurality of bits, on the basis of a threshold voltage set according to a conversion history of the bit converted before a target bit, a plurality of voltage generation units that each generates a plurality of reference voltages, and a setting unit that sets the threshold voltage using the reference voltage selected from the reference voltages generated by each of the respective voltage generation units on the basis of the conversion history; and an image processing unit that performs image processing on a digital pixel signal converted by the converter from the analog pixel signal into a bit value for each bit.
(9) The electronic apparatus according to the above (8), wherein the voltage conversion units include: a first voltage generation unit that generates the reference voltages for conversion by the converter from the analog pixel signal into the bit value of the bit on a high order side; and a second voltage generation unit that generates the reference voltages for conversion by the converter from the analog pixel signal into the bit value of the bit on a low order side.
(10) The electronic apparatus according to the above (9), wherein the second voltage generation unit generates a plurality of reference voltages having a voltage range overlapping with the reference voltages generated by the first voltage generation unit, and the setting unit sets the threshold voltage by changing the reference voltage selected on the basis of the conversion history on the basis of the reference voltage included in the voltage range.
(11) The electronic apparatus according to the above (10), wherein the second voltage generation unit generates the reference voltages such that two or more reference voltages are included in the voltage range when a gain with respect to the analog pixel signal is equal to or larger than a certain value.
(12) The electronic apparatus according to the above (10), wherein the second voltage generation unit generates the reference voltages such that a single reference voltage is included in the voltage range when a gain with respect to the analog pixel signal is smaller than a certain value.
(13) The electronic apparatus according to any one of the above (8) to (12), wherein, in the solid state imaging element, out of connection points from which the reference voltages generated by each of the voltage generation units are taken out, respectively, the connection points having identical potential are connected one another.
(14) The electronic apparatus according to any one of the above (8) to (13), wherein the solid state imaging element further includes a sample hold unit that samples the voltage generated by one of the voltage generation units and supplies the sampled voltage to another of the voltage generation units.
(15) The electronic apparatus according to any one of the above (8) to (14), wherein the electronic apparatus is an indirect ToF method range image sensor.

REFERENCE SIGNS LIST

(182) 1 solid state imaging element 2 pixel array unit 5 AD conversion unit 10.sub.1, 10.sub.2, 10.sub.n, 10a, 10b, 10c, 10d successive approximation type AD converter 12, 12a, 12b, 12c, 12d DA converter 14, 200 comparator 15 logic unit 102a, 102b reference voltage generator C110.sub.1, C110.sub.2, C110.sub.3, C110.sub.4, C116, C150, C213.sub.1, C213.sub.2, C214.sub.1, C214.sub.2 capacitor SW111.sub.1, SW111.sub.2, SW111.sub.3, SW111.sub.4, SW117, SW151.sub.1, SW151.sub.2, SW211.sub.1, SW211.sub.2, SW211.sub.3, SW211.sub.4, SW216.sub.1, SW216.sub.2, SW216.sub.3, SW216.sub.4, SW216.sub.5 switch