Method to improve profile control during selective etching of silicon nitride spacers

Abstract

Cyclic etch methods comprise the steps of: i) exposing a SiN layer covering a structure on a substrate in a reaction chamber to a plasma of hydrofluorocarbon (HFC) to form a polymer layer deposited on the SiN layer that modifies the surface of the SiN layer, the HFC having a formula C.sub.xH.sub.yF.sub.z where x=2-5, y>z, the HFC being a saturated or unsaturated, linear or cyclic HFC; ii) exposing the polymer layer deposited on the SiN layer to a plasma of an inert gas, the plasma of the inert gas removing the polymer layer deposited on the SiN layer and the modified surface of the SiN layer on an etch front; and iii) repeating the steps of i) and ii) until the SiN layer on the etch front is selectively removed, thereby forming a substantially vertically straight SiN spacer comprising the SiN layer on the sidewall of the structure.

Claims

1. A cyclic etch method, the method comprising the steps of: i) exposing a SiN layer covering structures on a substrate in a reaction chamber to a plasma of hydrofluorocarbon (HFC) to form a polymer layer deposited on the SiN layer that modifies the surface of the SiN layer, the HFC having a formula C.sub.xH.sub.yF.sub.z where x=2-5, y>z, the HFC being a saturated or unsaturated, linear or cyclic HFC; ii) exposing the polymer layer deposited on the SiN layer to a plasma of an inert gas, the plasma of the inert gas removing the polymer layer deposited on the SiN layer and the modified surface of the SiN layer on etch front; and iii) repeating the steps of i) and ii) until the SiN layer covered on the etch front is removed thereby forming vertical straight SiN spacers with the SiN layer covered on the sidewalls of the structures, wherein a pressure in the reaction chamber ranges from approximately 1 mTorr to approximately 1 Torr.

2. The cyclic etch method of claim 1, further comprising the steps of, after the step of i), pumping the reaction chamber to a vacuum; purging the reaction chamber with Ar; pumping the reaction chamber to the vacuum; and introducing the inert gas into the reaction chamber to generate the plasma of the inert gas.

3. The cyclic etch method of claim 2, further comprising the steps of, after the step of ii), pumping the reaction chamber to a vacuum; purging the reaction chamber with Ar; pumping the reaction chamber to the vacuum; and introducing the HFC into the reaction chamber to generate the plasma of the HFC.

4. The cyclic etch method of claim 1, wherein a single or multiple RF sources are applied to generate the plasma of the HFC in the step of i) and to generate the plasma of the inert gas in the step of ii), respectively.

5. The cyclic etch method of claim 1, wherein a single RF source is applied to generate the plasma of the HFC in the step of i) and multiple RF sources are applied to generate the plasma of the inert gas in the step of ii), and vice versa.

6. The cyclic ALE method of claim 1, wherein the inert gas is Ar.

7. The cyclic etch method of claim 1, wherein the HFC is C.sub.2H.sub.5F or C.sub.3H.sub.7F.

8. The cyclic etch method of claim 1, wherein the HFC selectively etches the SiN layer over the structures.

9. The cyclic etch method of claim 1, wherein less to no footings are formed at each corner between the vertical straight SiN spacer and the substrate.

10. The cyclic etch method of claim 1, wherein no fluoride residuals are left on the vertical straight SiN spacers and the etch front.

11. A cyclic etch method for forming vertical straight SiN spacers, the method comprising the steps of: i) exposing a SiN layer covering structures on a substrate in a reaction chamber to a plasma of hydrofluorocarbon (HFC) to form a polymer layer deposited on the SiN layer that modifies the surface of the SiN layer, the HFC having a formula C.sub.xH.sub.yF.sub.z where x=2-5, y>z, the HFC being a saturated or unsaturated, linear or cyclic HFC; ii) exposing the polymer layer deposited on the SiN layer to a plasma of an inert gas, the plasma of the inert gas removing the polymer layer deposited on the SiN layer and the modified surface of the SiN layer on the etch front; and iii) repeating the steps of i) and ii) until the SiN layer covered on the etch front is removed thereby forming the vertical straight SiN spacers with the SiN layer covered on the sidewalls of the structures, wherein a pressure in the reaction chamber ranges from approximately 1 mTorr to approximately 1 Torr.

12. The cyclic etch method of claim 11, wherein a single or multiple RF sources are applied to generate the plasma of the HFC in the step of i) and to generate the plasma of the inert gas in the step of ii), respectively.

13. The cyclic etch method of claim 11, wherein a single RF source is applied to generate the plasma of the HFC in the step of i) and multiple RF sources are applied to generate the plasma of the inert gas in the step of ii), and vice versa.

14. The cyclic etch method of claim 11, wherein the HFC is C.sub.2H.sub.5F or C.sub.3H.sub.7F.

15. The cyclic etch method of claim 11, wherein the HFC selectively etches the SiN layer over the structures.

16. The cyclic etch method of claim 11, wherein less to no footings are formed at each corner between the vertical straight SiN spacer and the substrate.

17. A cyclic etch method for forming vertical straight SiN gate spacers, the method comprising the steps of: i) exposing a SiN layer covering gate stacks on a substrate in a reaction chamber to a plasma of hydrofluorocarbon (HFC) selected from the group consisting of C.sub.2H.sub.5F and C.sub.3H.sub.7F to form a polymer layer deposited on the SiN layer that modifies the surface of the SiN layer; ii) exposing the polymer layer deposited on the SiN layer to Ar plasma, the Ar plasma removing the polymer layer deposited on the SiN layer and the modified surface of the SiN layer on etch front; and iii) repeating the steps of i) and ii) until the SiN layer covered on the etch front is removed thereby forming the vertical straight SiN gate spacers with the SiN layer covered on the sidewalls of the gate stacks, wherein a pressure in the reaction chamber ranges from approximately 1 mTorr to approximately 1 Torr.

18. The cyclic etch method of claim 17, wherein a single or multiple RF sources are applied to generate the plasma of the HFC in the step of i) and to generate the Ar plasma in the step of ii), respectively.

19. The cyclic etch method of claim 18, wherein a single RF source is applied to generate the plasma of the HFC in the step of i) and multiple RF sources are applied to generate the Ar plasma in the step of ii), and vice versa.

20. The cyclic etch method of claim 18, wherein less to no footings are formed at each corner between the SiN gate spacer and the substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) For a further understanding of the nature and objects of the present invention, reference should be made to the following detailed description, taken in conjunction with the accompanying drawings, in which like elements are given the same or analogous reference numbers and wherein:

(2) FIG. 1a is a cross-sectional side view of an exemplary pattern formed for producing SiN spacers on an underlying substrate in the art;

(3) FIG. 1b is a cross-sectional side view of exemplary SiN spacers on an underlying substrate with an ideal etch result of SiN spacers in the art;

(4) FIG. 1c is a cross-sectional side view of exemplary SiN spacers on an underlying substrate with actual spacer etching processes that produce footing at the bottom of the spacers in the art;

(5) FIG. 2 is a process flow per cycle of the disclosed cyclic ALE process;

(6) FIG. 3 is a graph of etched thickness versus ALE cycles using CH.sub.3F;

(7) FIG. 4 is a graph of etched thickness versus ALE cycles using C.sub.2H.sub.5F;

(8) FIG. 5 is a graph of etched thickness versus ALE cycles using C.sub.3H.sub.7F;

(9) FIG. 6a is EDS mapping of SiN spacers after ALE with 100% etch sidewall and 100% over etch sidewall using C.sub.2H.sub.5F, respectively,—horizontal scan of the sidewall;

(10) FIG. 6b shows EDS line scan using atomic of SiN spacers after ALE with 100% etch sidewall and 100% over etch sidewall using C.sub.2H.sub.5F, respectively,—vertical scan of the bottom of the spacer; and

(11) FIG. 7 is continuous etch of SiN Spacers using C.sub.2H.sub.5F: EDS mapping (left figure) and EDS line scan (right figure).

DESCRIPTION OF PREFERRED EMBODIMENTS

(12) Disclosed are methods to improve profile control for forming silicon nitrile (SiN) spacers on Si-containing substrates with high selectivity in semiconductor applications. The disclosed methods apply a cyclic atomic layer etching (ALE) process using a plasma of a HFC and a plasma of a noble gas to selectively etch a SiN layer over structures covered by the SiN layer and/or a underlying Si-containing layer (e.g., a substrate). Here, the structures may be a gate or a gate stack.

(13) The disclosed methods have significant improved profile controls for forming the SiN spacers. Critical characteristics of the formed SiN spacers include high selectivity of SiN to the underlying Si-containing layer, such as, poly-Si (or Si), and SiO.sub.2. The critical characteristics of the formed SiN spacers also include no chemical damage to the underlying Si-containing layer even when using an over-etch recipe, less to no excess material proximate the SiN layer and the substrate, less to no footing at the bottom edge of the spacers, no F residuals left on the sidewall of the spacers, etc.

(14) In semiconductor applications, a spacer is a layer of a material deposited on a structure, such as a gate or a gate stack, by CVD or ALD to isolate gate contact and source and drain contacts in metal-oxide-semiconductor field-effect transistors (MOSFETs). The material may be SiN or the like. The spacer passivates sidewalls of the gate stack. The disclosed methods may apply to any types of spacers in semiconductor applications, including gate spacers, patterning spacers having self-aligned double patterning (SADP) spacers, self-aligned quadruple patterning (SAQP) spacers, etc. Here the gate stack may be a digital switch, random-access memory (RAM), amplifier, field-effect transistor-based biosensor (BioFET), DNA field-effect transistor (DNAFET), ferroelectric, magnetic, electrolytic, etc. More specifically, the gate stack may be high-k gate stacks including flash memory, such as 3D NAND and NOR, silicon-oxide-nitride-oxide-silicon (SONOS), strained interfaces including global strain and local strain, ferroelectric gate stacks, electrolytic interfaces, etc.

(15) FIG. 1a to FIG. 1c demonstrate exemplary cross-sectional side views of exemplary SiN spacers formation on an underlying substrate. FIG. 1a shows a trench pattern, but is not limited to, formed for producing SiN spacers. SiN covered structures 10 and 12 were formed on the top of a substrate 102. A plurality of SiN covered structures may be formed on the top of the substrate 102, but only two structures 10 and 20 are shown. The substrate 102 may be a FinFET (Fin Field-effect transistor) substrate composed of Si-containing material, such as Si, poly-Si, SiO.sub.2, etc. Numeral 104 represents a layer of SiN layer that covers structures 106 on the substrate 102. The structure 106, also called a pillar in the art, may be a gate stack covered by the SiN layer 104. In an ideal situation, the SiN layer that horizontally covers etch front, the top of structures 106 or the top of the pillar and the top of substrate 102 or the bottom of the trench, should be removed and a vertically straight and uniform SiN sidewall on the structures 106 with less to no footing at the bottom corner should be obtained. Here, “a.sub.1” and “a.sub.2” represent the thickness of SiN layer on sidewalls 104 at different heights of the structure or gate stack. The height of “a.sub.1” may be close to the top of the pillar, for example, at the height about ⅓ of the total height of the structure 106 below the top of the pillar; “a.sub.2” may be at the height close to the substrate 102 at the height about ⅓ of total height of the structure 106 above the substrate 102. Since the structure 106 under the SiN layer 104 may be curved at the bottom adjacent to the substrate 102 (not shown), the value of “a.sub.2” may be less than the value of “a.sub.1” with a vertically straight SiN spacer. “b” and “c” represent the thickness of SiN layer on top of the structures 106 and on top of the substrate 102, respectively. Here “b” and “c” are the thicknesses of etch front. Furthermore, “c” may also represent the thickness of the removal of substrate 102 after removing the SiN layer. In this case, “c” may be a negative value. As shown in FIG. 1b, an ideal SiN spacer etch result is presented, in which a vertically straight and uniform SiN sidewall 204 coverage on the structures 206 is formed and the SiN layer on the etch front that horizontally covers the top of structures 206 and the top of substrate 202 are removed. However, actual spacer etching processes often have excess material left proximate the SiN layer and the substrate, producing footing 308 at the bottom of the spacers, as shown in FIG. 1c. Here the horizontal length of the footing 308 adjacent to the substrate 302, “d”, is defined to represent the size of the footing.

(16) The disclosed cyclic ALE processes for controlling etch profile of SiN spacers formed on Si-containing substrates overcome the shortages of footing when manufacturing the SiN spacers. The disclosed cyclic ALE processes for controlling etch profile of SiN spacers formed on Si-containing substrates also produce vertically straight spacers without tapering when manufacturing the SiN spacers. The disclosed cyclic ALE processes comprises a surface modification step or a deposition step and a surface removal step or an etching step in one ALE cycle. During the surface modification step, a thin layer of polymer is deposited on the surface of the SiN layer that modifies the surface of the SiN layer (see FIG. 1a, SiN layer 104) in a reaction chamber. The thin layer of polymer is formed by a plasma of a HFC gas or a plasma of a gas mixture of a HFC gas and an inert gas, such as N.sub.2, Ar, Kr, Xe, preferably Ar. The HFC gas reacts with the material SiN on the surface of the SiN layer, forming the thin layer of polymer which is a C rich polymer (C:F>1) and also called a modified surface layer on the surface of the SiN layer where chemical bonds are formed at an interlayer between the thin layer of polymer and the surface of the SiN layer. At the surface removal step, the modified surface layer is etched or removed by a pure inert gas (e.g., Ar) plasma through energetic ion bombardment to sputter the modified surface layer, which are highly volatile and may be pumped out from the chamber. After the surface removal step, the surface modification step is repeated, forming a cyclic ALE process. With the cyclic ALE, an ALE over etch recipe may be applied to further remove the SiN layer on the etch front with an infinite selectivity of SiN versus the structures or the gate stacks. The ALE over etch recipe may range from approximately 10% ALE over etch to approximately 200% ALE over etch, preferably, from approximately 50% ALE over etch to approximately 200% ALE over etch. These processes may be cyclized and enable step-by-step removal of materials, which increases pattern fidelity and minimizes a footing of SiN spacer. Between the surface modification step and the surface removal step or after the deposition step and the etching step, a N.sub.2 purge step is applied. The N.sub.2 purge step includes a vacuum pump step to pump the HFC gas out of the reaction chamber before the N.sub.2 purge step and a vacuum pump step to pump N.sub.2 out of the reaction chamber after N.sub.2 purge step.

(17) An ideal cyclic ALE process is based on self-limiting reactions, which means the reactants only react with the available surface sites on the substrate while keep the bottom layer intact. ALE process conditions may be optimized by tracking the self-limiting nature regarding the reactant flow rates and exposure time. A constant purge of N.sub.2 was used at the end of each step to eliminate the excessive etchant from the system to avoid any synergistic reactions.

(18) Referring to FIG. 2, in one cycle of the disclosed ALE process, a plasma etching gas formed from a gas mixture of a HFC gas and Ar deposits a thin layer of polymer on the surface of the SiN layer in a reaction chamber in Step 1. The thin layer of polymer is then etched or removed by a pure inert gas (e.g., Ar) plasma in Step 2. After each Step, the reaction chamber experiences a pump/N.sub.2 purge/pump process, which includes pumping the reaction chamber to a vacuum, filling N.sub.2 into the reaction chamber for purging and pumping the reaction chamber to a vacuum again before proceeding the next Step.

(19) The disclosed cyclic ALE methods may include using the HFC gases, having a formula C.sub.xH.sub.yF.sub.z where x=2-5, y>z, being saturated or unsaturated, linear or cyclic, to selectively plasma etch SiN. The HFC plasma interacts with SiN forming C rich polymer (C:F>1) which deposits on top of the SiN layer forming a polymer layer. The disclosed HFC gases may be used to mix with an inert gas in a plasma chamber to selectively etch the polymer layer and a single atomic layer of the SiN layer as well. Thus, the SiN spacers are formed with improved profile control, such as high selectivity, minimized footing, limited fluorine formation and smooth surface of the SiN spacers. The inert gas may be Ar, Kr and Xe. Preferably, Ar.

(20) The disclosed HFC gases for forming the polymer layer on the SiN layer may include the following HFC gases, i.e., fluoroethane C.sub.2H.sub.5F (CAS #353-36-6) and 1-fluoropropane C.sub.3H.sub.7F (CAS #460-13-9). These HFC gases are used to mix with an inert in a plasma chamber to deposit a polymer layer on the SiN layer. An interlayer between the polymer layer and the SiN layer is formed to modify the surface of the SiN layer. A plasma of an inert gas, such as, Ar, is then selectively removes the polymer layer and the interlayer as well. This is equivalent to remove a single atomic layer of the SiN layer. In this way, the SiN spacers are formed with improved profile control, such as high selectivity, minimized footing, limited fluorine formation and smooth surface of the SiN spacers. The inert gas may be Ar, Kr and Xe, preferably, Ar.

(21) The disclosed HFC gases are provided at greater than 99% v/v purity, preferably at greater than 99.9% v/v purity, by removing key impurities N.sub.2, CO.sub.x, SO.sub.x, H.sub.2O, etc.

(22) The disclosed HFC gases contain less than 1% by volume trace gas impurities, with less than 150 ppm by volume of impurity gases, such as N.sub.2 and/or H.sub.2O and/or CO.sub.2, contained in said trace gaseous impurities. Preferably, the water content in the plasma etching gas is less than 20 ppmw by weight. The purified product may be produced by distillation and/or passing the gas or liquid through a suitable adsorbent, such as a 4 Å molecular sieve.

(23) The disclosed cyclic ALE methods includes providing a plasma processing chamber having a substrate disposed therein. The plasma processing chamber may be any enclosure or chamber within a device in which etching methods take place such as, and without limitation, any chambers or enclosures used for plasma etching, such as, reactive ion etching (RIE), capacitively coupled plasma (CCP) with single or multiple frequency RF sources, inductively coupled plasma (ICP), electron cyclotron resonance (ECR), microwave plasma reactors, remote plasma reactors, pulsed plasma reactors, or other types of etching systems capable of selectively removing a portion of the silicon-containing film or generating active species. Preferred chamber is a CCP chamber.

(24) One of ordinary skill in the art will recognize that the different plasma reaction chamber designs provide different electron temperature control. Suitable commercially available plasma reaction chambers include but are not limited to the Applied Materials magnetically enhanced reactive ion etcher sold under the trademark eMAX™ or the Lam Research Dual CCP reactive ion etcher dielectric etch product family sold under the trademark 2300® Flex™. The RF power in such may be pulsed to control plasma properties and thereby improving the etch performance (selectivity and damage) further.

(25) An oxygen-containing gas may be introduced into the reaction chamber in order to eliminate high polymer deposition or reduce the thickness of the high polymer deposition. The oxygen-containing gas include, without limitation, oxidizers such as, O.sub.2, O.sub.3, CO, CO.sub.2, NO, NO.sub.2, N.sub.2O, SO.sub.2, COS, H.sub.2O and combinations thereof. It is known that addition of oxygen or oxygen containing gases to the plasma chemistry increases F/C ratio of plasma species and reduces polymer formation (See, e.g., U.S. Pat. No. 6,387,287 to Hung et al.). The disclosed HFC gas and the oxygen containing gas may be mixed together prior to introducing into the reaction chamber.

(26) Alternatively, the oxygen-containing gas is introduced continuously into the chamber and the disclosed HFC gas introduced into the chamber in pulses. The oxygen-containing gas comprise between approximately 0.01% by volume to approximately 99.99% by volume of the mixture introduced into the chamber.

(27) In the disclosed cyclic ALE methods, the plasma process time may vary from 0.01 s to 10000 s. Preferably from 1 s to 30 s. N.sub.2 purge time may vary from 1 s to 10000 s. Preferably 10 s to 60 s.

(28) The temperature and the pressure within the reaction chamber are held at conditions suitable for the silicon-containing film to react with the activated etching gas. For instance, the pressure in the chamber may be held between approximately 1 mTorr and approximately 50 Torr, preferably between approximately 1 mTorr and approximately 10 Torr, more preferably between approximately 300 mTorr and approximately 1 Torr, as required by the etching parameters. Likewise, the substrate temperature in the chamber may range between approximately −110° C. to approximately 2000° C., preferably between approximately −70° C. to approximately 1500° C., more preferably between approximately −20° C. to approximately 1000° C., even more preferably between approximately 25° C. to approximately 700° C., even more preferably between approximately 25° C. to approximately 500° C., and even more preferably between approximately 25° C. to approximately 50° C. Chamber wall temperatures may range from approximately 25° C. to approximately 100° C. depending on the process requirements.

(29) In one embodiment, the disclosed HFC gas is introduced into the reaction chamber containing the substrate having structures, such as gate stacks, formed thereon with a covered SiN layer. The gas may be introduced to the chamber at a flow rate ranging from approximately 1 sccm to approximately 10 slm. Preferably 1 sccm to 100 sccm. The inert gas may be introduced to the chamber at a flow rate ranging from approximately 1 sccm to approximately 10 slm. Preferably 10 sccm to 200 sccm. One of ordinary skill in the art will recognize that the flow rate may vary from tool to tool.

(30) The disclosed cyclic etch methods further comprise the steps of i) positioning a patterned substrate on a substrate holder in a plasma processing chamber or a reaction chamber, the patterned substrate having a SiN layer covering at least one structure on a substrate, here the structure may be a gate stack; the substrate may contain Si-containing layer(s), ii) introducing a HFC gas or a mixture of a HFC gas and an inert gas into the reaction chamber to generate a plasma therein, once the plasma is generated, the plasma depositing a polymer layer on the SiN layer that modifies the surface of the SiN layer, the HFC gas having a formula C.sub.xH.sub.yF.sub.z where x=2-5, y>z, being a saturated or unsaturated, linear or cyclic HFC, the inert gas being N.sub.2, Ar, Kr, Xe, preferably Ar; iii) pumping the HFC gas or the mixture of the HFC gas and the inert gas out of the reaction chamber until the reaction chamber reaches to a high vacuum; iv) purging the reaction chamber with N.sub.2; v) pumping the reaction chamber to the high vacuum again; that is, pumping N.sub.2 out of the reaction chamber until the reaction chamber reaches to the high vacuum; vi) introducing the inert gas into the reaction chamber to generate a plasma of an inert gas; vii) exposing the polymer layer deposited on the SiN layer to the plasma of the inert gas, the plasma of the inert gas removing the polymer layer deposited on the SiN layer on an etch front and the modified surface of the SiN layer on the etch front through ion bombardment; vii) pumping the reaction chamber to the high vacuum; that is, pumping the inert gas out of the reaction chamber until the reaction chamber reaches to the high vacuum; viii) purging the reaction chamber with N.sub.2; ix) pumping the reaction chamber to the high vacuum; and x) repeating the steps of ii) to ix) until the SiN layer on the etch front is selectively removed, thereby forming a substantially vertically straight SiN spacer comprising the SiN layer on the sidewall of the gate stack. Here an over etch recipe may be applied, for example, from 50% over etch to 200% over etch may be applied.

(31) In an ideal case, the ion bombardment process only removes the polymer layer and the modified surface of the SiN layer on the etch front, that is, the SiN layer and the modified surface of the SiN layer on the top of the pillar and the bottom of the trench, and remains the SiN layer on the sidewall not changed. In reality, the thickness of the SiN layer on the sidewall might slightly change, due to small deviations and/or a structure having a curved bottom. The disclosed cyclic etch methods provide that at least a majority of the SiN layer on the sidewall of the gate stack is not removed. Preferably, less than 10% of a thickness of the SiN layer on the sidewall of the gate stack is removed, especially the SiN layer close to the bottom of the structure. More preferably, less than 5% of the thickness of the SiN layer on the sidewall of the gate stack is removed. Even more probably, less than 1% of the thickness of the SiN layer on the sidewall of the gate stack is removed. Even more preferably, no measurable reduction in the thickness of the SiN layer on the sidewall of the gate stack is produced.

(32) Compared with conventional SiN spacer etch processes, the disclosed cyclic ALE process using the disclosed HFC gases herein may reduce the SiN footing at the bottom edge of the spacers by more than 70%, from the examples that follow, while maintaining chemical integrity, without causing significant surface roughness or chemical contamination (e.g., F residue) on underlying materials. More specifically, with a cyclic ALE process using C.sub.2H.sub.5F, no fluoride residuals produced on the bottom of the trench and sidewall. Here, no fluoride residuals mean less than approximately 0.05% fluoride residuals left on the bottom of the trench and the sidewall, preferably, less than 0.03%. The disclosed cyclic ALE process using the disclosed HFC gases also produces a smooth surface of SiN spacers.

EXAMPLES

(33) The following non-limiting examples are provided to further illustrate embodiments of the invention. However, the examples are not intended to be all inclusive and are not intended to limit the scope of the inventions described herein.

(34) The following examples were conducted with a CCP plasma chamber with variable conditions for each step. Plasma power, pressure, gas flow rate, reaction time and so on were very well controlled. The pressure range was from 300 mtorr to 1 Torr. The temperature range was from 25° C. to 50° C. The gas flow rates for CH.sub.3F or C.sub.2H.sub.5F or C.sub.3H.sub.7F varied from 1 sccm to 10 sccm. The flow rates for noble gas varied from 10 sccm to 200 sccm. The noble gas used was Ar. The RF plasma power ranged from 50 W to 100 W. Plasma process time or reaction time varied from 1 s to 30 s. N.sub.2 purge time varied from 10 s to 60 s. Desired purity of CH.sub.3F or C.sub.2H.sub.5F or C.sub.3H.sub.7F was >99.9% by removing key impurities such as N.sub.2, CON, C.sub.xH.sub.yF.sub.z, SO.sub.x, H.sub.2O etc.

(35) The samples used in the following examples were patterned spacer wafers as shown in FIG. 1a, in which the substrate was a Si substrate.

(36) Ellisometer was J.A. Woollam Co. M-2000. SEM (scanning electron microscope) to image the patterned structure was JOEL JSM-7500 SEM. XPS to characterize the surface was Kratos XPS—Supra Model. AFM (atomic force microscope) to examine the surface was Park NX10 AFM. TEM (transmission electron microscope) to image the patterned structure was done with a FEI Tecnai Osiris FEG/TEM operated at 200 kV in bright-field (BF) TEM mode and high-resolution (HR) TEM mode. EDS (electronic diffusion spectra) were acquired on Bruker Quantax EDS system.

Example 1

CH.SUB.3.F Cyclic ALE Process

(37) The CH.sub.3F cyclic ALE process was conducted under optimized ALE conditions. Referring to FIG. 2, the etching gas was CH.sub.3F. The deposition step (Step 1) with CH.sub.3F was performed with RF power 75 W, pressure 300 mTorr, Ar gas flow rate 100 sccm, CH.sub.3F flow rate 5 sccm and reaction time for the deposition step was 4 seconds. The removal step (Step 2) was performed with RF power 50 W, pressure 500 mTorr, Ar gas flow rate 100 sccm, no CH.sub.3F and reaction time 30 seconds. The time for the pump/N.sub.2 purge/pump process between Step 1 and Step 2 and vice versa, was 90 seconds, FIG. 3 shows etched thickness versus ALE cycles for CH.sub.3F. With the increase of the ALE cycles, SiN etched thickness is getting deeper, the selectivity of SiN to p-Si, SiO and SiON is getting higher, and the selectivity of SiN to SiCN may remain not change. The etched thickness of SiN per cycle using CH.sub.3F with various ALE cycles is listed in Table 1.

(38) TABLE-US-00001 TABLE 1 Etched thickness of SiN per cycle with various ALE cycles ALE cycles 15 30 45 60 Etched thickness per cycle (nm) CH.sub.3F 4.9 4.5 4.2 4.7 C.sub.2H.sub.5F 1.49 1.47 1.36 1.37 C.sub.3H.sub.7F 2.0 2.1 2.3 2.4

Example 2

C.SUB.2.H.SUB.5.F Cyclic ALE Process

(39) The C.sub.2H.sub.5F cyclic ALE process was conducted under optimized ALE conditions. Referring to FIG. 2, the etching gas was C.sub.2H.sub.5F. The deposition step (Step 1) with C.sub.2H.sub.5F was performed with RF power 75 W, pressure 300 mTorr, Ar gas flow rate 100 sccm, C.sub.2H.sub.5F flow rate 5 sccm and reaction time for the deposition step was 4 seconds. The removal step (Step 2) was performed with RF power 50 W, pressure 500 mTorr, Ar gas flow rate 100 sccm, no C.sub.2H.sub.5F and reaction time 35 seconds. The time for the pump/N.sub.2 purge/pump process between Step 1 and Step 2 and vice versa, was 90 seconds. FIG. 4 shows etched thickness versus ALE cycles for C.sub.2H.sub.5F. With the increase of the ALE cycles, SiN etched thickness increases linearly and no etching to p-Si, SiO, SiON and SiCN occurs. The results of the C.sub.2H.sub.5F cyclic ALE process shows a very high selectivity of SiN to p-Si, SiO, SiON and SiCN, almost an infinite selectivity.

(40) Comparing to the cyclic ALE process using CH.sub.3F, C.sub.2H.sub.5F gas shows higher etch selectivity of SiN to p-Si, SiO, SiON and SiCN and lower etch rate, such that less etched amount per cycle was obtained. The etched thickness of SiN per cycle using C.sub.2H.sub.5F with various ALE cycles is listed in Table 1.

Example 3

C.SUB.3.H.SUB.7.F Cyclic ALE Process

(41) The C.sub.3H.sub.7F cyclic ALE process was conducted under optimized ALE conditions. Referring to FIG. 2, the etching gas was C.sub.3H.sub.7F. The deposition step (Step 1) with C.sub.3H.sub.7F was performed with RF power 75 W, pressure 300 mTorr, Ar gas flow rate 100 sccm, C.sub.3H.sub.7F flow rate 5 sccm and reaction time for the deposition step was 4 seconds. The removal step (Step 2) was performed with RF power 50 W, pressure 500 mTorr, Ar gas flow rate 100 sccm, no C.sub.3H.sub.7F and reaction time 40 seconds. The time for the pump/N.sub.2 purge/pump process between Step 1 and Step 2 and vice versa, was 150 seconds. FIG. 5 shows etched thickness versus ALE cycles for C.sub.3H.sub.7F. Etched thickness amount was increased linearly with number of ALE cycles, with an etch rate of 2.0-2.4 nm/cycle. An infinite etch selectivity of SiN over other material may also be obtained under optimized conditions. The etched thickness of SiN per cycle using C.sub.3H.sub.7F with various ALE cycles is listed in Table 1.

Example 4

SEM of SiN Spacer Patterned Wafer Cyclic ALE Using CH.SUB.3.F and C.SUB.2.H.SUB.5.F

(42) Referring to FIG. 1a, the dimensions of the SiN spacer patterned wafer before etch are as follows: “a” is 34 nm; “b” is 34 nm; and “c” is 34 nm. The substrate 102 is a Si substrate. Key factors concerned after etching are damage to the Si substrate, sidewall deposition, footing at the corner between the spacer and the substrate, fluoride residues on the SiN layer and the substrate or etch front, surface roughness of the SiN layer and the substrate or etch front, etc. Table 2 lists the thicknesses of the etch front after the cyclic ALE of the SiN spacer with CH.sub.3F and C.sub.2H.sub.5F with various cyclic ALE modes, such as 50% etch, 100% etch, 100% over etch and 200% over etch. It is noticed that ALE 100% etch and ALE 100% over etch with C.sub.2H.sub.5F provided optimized results, which demonstrate less to no footing formed at the bottom of the spacers.

(43) TABLE-US-00002 TABLE 2 SEM results with CH.sub.3F and C.sub.2H.sub.5F with various cyclic ALE modes. Cyclic ALE mode b (nm) c (nm) CH.sub.3F 50% etch 20  13.1 100% etch 0 to 5 0 100% over etch 0 −14.1 200% over etch 0 −26.7 to −27.7 C.sub.2H.sub.5F 50% etch 17.8 to 18.3 16.4 100% etch 0-5 0 100% over etch 0 −3.75 to −4.22 200% over etch 0 −14.1

Example 5

TEM of SiN Spacer Patterned Wafer Cyclic ALE Using C.SUB.2.H.SUB.5.F

(44) ALE 100% etch and 100% over etch with C.sub.2H.sub.5F shown in Example 4 were further tested with TEM.

(45) Referring to FIG. 1a, the dimensions of the SiN spacer patterned wafer before etch are as follows: “a” is 34 nm; “b” is 34 nm; and “c” is 34 nm. The substrate 102 is a Si substrate. TEM-ready samples were prepared using the in situ focused ion beam (FIB) lift out technique on an FEI Strata 400 Dual Beam FIB/SEM. The samples were capped with protective carbon and e-Pt/I-Pt prior to milling. The TEM lamella thickness was ˜100 nm. The samples were imaged with a FEI Tecnai Osiris FEG/TEM operated at 200 kV in bright-field (BF) TEM mode and high-resolution (HR) TEM mode. The TEM results of cyclic ALE using C.sub.2H.sub.5F are listed in Table 3.

(46) With ALE-100% etch, no over etch occurred, SiN on the top of the pillar was not completely etched, the left (L) and right (R) thicknesses (“a.sub.2”, about ⅓ of the total height of the gate stack close to the substrate) of the SiN layer on the sidewall are 32.6 and 32.3 nm, respectively, and the left and right footings (“d”) were 6.6 nm and 8.2 nm. The thicknesses (“a.sub.2”) of the SiN layer on the sidewall reduced about 5%. In contrast, with ALE-100% over etch, SiN on the top of the pillar was completely etched, the left and right thicknesses (“a.sub.2”) of the SiN layer on the sidewall are 30.4 and 31.1 nm, respectively, and the left and right footings were 6.0 nm and 3.9 nm. The thicknesses (“a.sub.2”) of the SiN layer on the sidewall reduced about 9.5%. Thus, less than 10% of a thickness of the SiN layer on the sidewall of the gate stack is removed. The reduction of the thickness (a.sub.2) of the SiN layer on the sidewall may be due to the curvature of the structure or the gate stack adjacent to the substrate that makes the inner side of the SiN layer adjacent to the structure or gate stack curved. The reduction of the thickness (a.sub.2) of the SiN layer on the sidewall may also be due to small deviations.

(47) Si recess refers to the amount of thickness of the Si substrate was etched. The Si recess was measured 10 nm away from the bottom edge of SiN sidewall toward left and right directions. With ALE-100% etch, no over etch occurred, and the left and right Si recesses were 1.446 nm and 1.285 nm, respectively. In contrast, with ALE-100% over etch, the left and right Si recesses were 4.096 nm and 4.194 nm, respectively.

(48) Surface roughness of SiN spacer after ALE with 100% etch and 100% over etch using C.sub.2H.sub.5F includes the surface roughness of the top of the pillar (T) and the surface roughness of the bottom of the trench (B). Table 3 also includes the surface roughness results. With ALE 100% etch, a 2-3 atomic layer level (a.l.) of SiN layer was still left on the top of the pillar (positive value), meaning the SiN layer on the top of the pillar was not completely removed. In this case, the interface between SiN layer and the top of the pillar was smooth and flat, which equivalents to the surface roughness without etching. The bottom of the trench etched with ALE-100% etch also shows 2-3 atomic layer level of SiN layer left on the bottom of the trench. With ALE-100% over etch, the top of the pillar and the bottom of the trench were all etched a 2-3 atomic layer level (negative value).

(49) TABLE-US-00003 TABLE 3 TEM results with C.sub.2H.sub.5F with different cyclic ALE modes “a.sub.2” (nm) “d” (nm) Si recess (nm) surface roughness (a.i.) ALE mode L R L R L R T B 100% etch 32.6 32.3 6.6 8.2 1.446 1.285 2 to 3 2 to 3 100% over etch 30.4 31.1 6 3.9 4.096 4.194 −2 to −3 −2 to −3

Example 6

EDS of SiN Spacer Patterned Wafer Cyclic ALE Using C.SUB.2.H.SUB.5.F

(50) FIG. 6a shows EDS mapping of SiN spacer after ALE with 100% etch sidewall and 100% over etch sidewall using C.sub.2H.sub.5F, respectively,—horizontal scan of the sidewall. With 100% etch, no over etch occurred and no F residual on the sidewall. With 100% over etch, no F residual on the sidewall either.

(51) FIG. 6b shows EDS line scan using atomic of SiN spacer after the cyclic ALE with 100% etch sidewall and 100% over etch sidewall using C.sub.2H.sub.5F, respectively,—vertical scan of the bottom of the spacer. With 100% etch, no F residual on the sidewall. With 100% over etch, no F residual on the sidewall either.

Example 7

Cyclic ALE vs Continuous Etch Using C.SUB.2.H.SUB.5.F

(52) Table 4 is a comparison of continuous etch and cyclic ALE. The results show with continuous etch process, Si recess was 2.9 nm; polymer layer was formed on the sidewall; and the footing was 16.2 nm at the left corner and 15.3 at the right corner. Whereas, with the cyclic ALE process, the results show that Si recess was 4.1 to 4.2 nm; the minimized polymer layer was formed on the sidewall; and the footing was 6.0 nm at left and 3.9 nm was formed at right. Comparing to the continuous etch, the cyclic ALE process reduces the footing approximately 75%. Thus, with the cyclic ALE process, the Si recess and surface roughness are all getting improved and less to no footings are formed comparing to those with continuous etch process using C.sub.2H.sub.5F to etch SiN Spacer. Here, less to no footing may be defined by “d” approximately 6 nm.

(53) TABLE-US-00004 TABLE 4 Comparison of continuous etch and cyclic ALE Si Etch Left “d” Right “d” recess Polymer layer mode (nm) (nm) (nm) on sidewall Continuous 16.2 15.3 2.9 yes etch ALE 100% 6 3.9 4.1 to 4.2 minimized over etch

(54) FIG. 7 shows continuous etch of SiN Spacer using C.sub.2H.sub.5F: EDS mapping (left figure) and EDS line scan (right figure). Clearly, with continuous etch, F residues existed on the sidewall (around 22 to 36 nm) and the bottom of the trench (around 36 to 58 nm). Whereas, F residues were not shown in FIG. 6a and FIG. 6b.

(55) Table 5. lists the measured percentage of fluoride residues remained on the bottom of the trench and the sidewall after cyclic ALE and continuous etch, respectively. The cyclic ALE process modes have almost no fluoride left on the bottom of the trench and sidewall, whereas, the continuous etch method produced the fluoride residues on the bottom of the trench and sidewall.

(56) Thus, the cyclic ALE process modes with C.sub.2H.sub.5F produce no fluoride residues and reduced etchant residuals on the surface of etch front and sidewall. The cyclic ALE process modes with C.sub.2H.sub.5F produce minimized SiN footings and less to no damage to the top of SiN spacer.

(57) TABLE-US-00005 TABLE 5 Fluoride Residues ALE 100% ALE 100% Continuous etch over etch etch Bottom 0.03% 0.018% 3.35% of trench Sidewall 0.021% 0.014% 7.26%

Example 8

Surface Roughness Using C.SUB.2.H.SUB.5.F to Cyclic ALE SiN Planar Wafer

(58) Surface roughness—RMS of a thin film of SiN on a planar wafer was measured by AFM before and after cyclic ALE with C.sub.2H.sub.5F. Before the cyclic ALE with C.sub.2H.sub.5F, RMS (Root Mean Square)=2.9 nm. After the cyclic ALE with C.sub.2H.sub.5F, RMS=1.1 nm. Thus, a smaller RMS was achieved after the cyclic ALE with C.sub.2H.sub.5F, which shows an improved surface smoothing effect of the ALE with C.sub.2H.sub.5F.

(59) In summary, the disclosed cyclic ALE of SiN spacer using the disclosed HFCs, such as, C.sub.2H.sub.5F, C.sub.3H.sub.7F, may minimize SiN footings (e.g., reducing the footing approximately 75% comparing to the continuous etch), produce no F residues on the top of the pillar, the bottom of the trench and the sidewall, no chemical contamination and no degradation of surface roughness after cyclic ALE processes. The disclosed cyclic ALE of SiN spacer using the disclosed HFCs, such as, C.sub.2H.sub.5F, C.sub.3H.sub.7F, improves etching profile control for etching SiN spacers formed on Si-containing substrates in semiconductor applications with high selectivity.

(60) It will be understood that many additional changes in the details, materials, steps, and arrangement of parts, which have been herein described and illustrated in order to explain the nature of the invention, may be made by those skilled in the art within the principle and scope of the invention as expressed in the appended claims. Thus, the present invention is not intended to be limited to the specific embodiments in the examples given above and/or the attached drawings.

(61) While embodiments of this invention have been shown and described, modifications thereof may be made by one skilled in the art without departing from the spirit or teaching of this invention. The embodiments described herein are exemplary only and not limiting. Many variations and modifications of the composition and method are possible and within the scope of the invention. Accordingly, the scope of protection is not limited to the embodiments described herein, but is only limited by the claims which follow, the scope of which shall include all equivalents of the subject matter of the claims.