METHOD FOR PRODUCING A PLANAR LIGHT CIRCUIT AND PLANAR LIGHT CIRCUIT

Abstract

A method for producing a planar light circuit is specified. The method comprises: providing a substrate free of light producing regions, depositing a waveguide layer, applying a photostructurable mask on the waveguide layer, photostructuring of the photostructurable mask such that the photostructurable mask is removed in regions, etching of the waveguide layer in the regions such that channels are produced in the waveguide layer, wherein the channels confine waveguides, removal of the photostructurable mask layer, and singulating into a planar light circuit. Furthermore, a planar light circuit is specified.

Claims

1. A method for producing a planar light circuit comprising: providing a substrate free of light producing regions, depositing a waveguide layer, applying a photostructurable mask on the waveguide layer, photostructuring of the photostructurable mask such that the photostructurable mask is removed in regions, etching of the waveguide layer in the regions such that channels are produced in the waveguide layer, wherein the channels confine waveguides and wherein a majority of the waveguide layer remains on the substrate, removal of the photostructurable mask, and singulating into a planar light circuit.

2. The method for producing a planar light circuit according to claim 1, wherein the waveguide layer comprises a material selected from the following group: SiN.sub.x, SiO.sub.xN.sub.y, GaN, HfO.sub.2, LiNbO.sub.3, Ta.sub.2O.sub.5, Nb.sub.2O.sub.5, HfO.sub.2, TiO.sub.2, Si and mixtures thereof.

3. The method for producing a planar light circuit according to claim 1, wherein an adhesion layer is deposited on the waveguide layer before applying the photostructurable mask.

4. The method for producing a planar light circuit according to claim 1, wherein an adhesion promoter is applied on the waveguide layer before applying the photostructurable mask.

5. The method for producing a planar light circuit according to claim 1, wherein the waveguide layer is deposited by plasma-enhanced chemical vapor deposition.

6. The method for producing a planar light circuit according to claim 5, wherein a low frequency plasma source is used in the plasma-enhanced chemical vapor deposition.

7. The method for producing a planar light circuit according to claim 1, wherein the waveguide layer is etched by inductively coupled plasma etching.

8. The method for producing a planar light circuit according to claim 7, wherein a reaction chamber for the inductively coupled plasma etching is cleaned before etching the waveguide layer.

9. The method for producing a planar light circuit according to claim 1, wherein a cladding is applied on the waveguide layer after removal of the photostructurable mask.

10. A planar light circuit comprising: a substrate free of light producing regions, and a waveguide layer on the substrate, wherein the waveguide layer comprises channels confining a waveguide and the waveguide layer covers a majority of the substrate.

11. The planar light circuit according to claim 10, wherein the waveguide is a multi-mode waveguide.

12. The planar light circuit according to claim 10, wherein the substrate comprises or consists of a transparent or opaque inorganic material selected from the group consisting of: fused silica, sapphire, YAG, MgF.sub.2, AlN, various glasses, single crystal semiconductor based materials.

13. The planar light circuit according to claim 10, wherein the substrate is opaque, the substrate comprises an interlayer, and the interlayer is transparent.

14. The planar light circuit according to claim 10, wherein an adhesion layer is arranged on the waveguide layer.

15. The planar light circuit according to claim 10, wherein a cladding is arranged on the waveguide layer and a material of the cladding has a lower refractive index than a material of the waveguide layer.

16. The planar light circuit according to claim 15, wherein the cladding comprises a material selected from the following group: SiO.sub.2, Al.sub.2O.sub.3, HfO.sub.2, oxide glass.

17. The planar light circuit according to claim 10, wherein the waveguide layer has a thickness of at least 500 nanometers.

18. The planar light circuit according to claim 10, wherein the waveguide comprises, seen in top view, at least two branches merging together into a single branch in at least one combining region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

In the figures:

[0071] FIGS. 1A to 1H show schematic sectional view of stages of a method for producing a planar light circuit according to an exemplary embodiment.

[0072] FIG. 2 shows a schematic top view of a stage of a method for producing a planar light circuit according to an exemplary embodiment.

[0073] FIGS. 3A and 3B show results of ellipsometry measurements of waveguide layers.

[0074] FIG. 4 shows a plot of a N/Si ratio versus a refractive index of a waveguide layer comprising SiN.sub.x.

[0075] FIG. 5 shows a scanning electron microscopy (SEM) image of a cross-section of a stage of a method for producing a planar light circuit.

[0076] FIG. 6 shows a SEM image of a top view of a stage of a method for producing a planar light circuit.

[0077] FIG. 7 shows a SEM image of a top view of a planar light circuit according to an exemplary embodiment.

[0078] FIGS. 8, 9, and 10A to 10C each show a SEM image of cross-sections of a planar light circuit according to exemplary embodiments.

[0079] FIG. 11 shows an image of a top view of a planar light circuit according to an exemplary embodiment.

[0080] FIG. 12 shows a schematic top view of a radiation emitting device according to an exemplary embodiment.

DETAILED DESCRIPTION

[0081] In the exemplary embodiments and figures, similar or similarly acting constituent parts are provided with the same reference symbols. The elements illustrated in the figures and their size relationships among one another should not be regarded as true to scale. Rather, individual elements may be represented with an exaggerated size for the sake of better representability and/or for the sake of better understanding.

[0082] As shown in FIG. 1A, during a method for producing a planar light circuit according to an exemplary embodiment a substrate 1 is provided. The substrate 1 is free of light producing regions. Presently the substrate 1 comprises a substrate layer 2 and an interlayer 3. The substrate layer 2 comprises or consists of silicon, whereas the interlayer 3 comprises or consists of wet thermal SiO.sub.2. The interlayer 3 has a thickness of about 2 micrometer. Alternatively, a substrate 1 comprising or consisting of fused silica is provided. The substrate 1 is provided in the form of a wafer.

[0083] A waveguide layer 4 is deposited on the substrate 1 as shown in FIG. 1B. Before the deposition of the waveguide layer 4, a surface of the substrate 1, in particular a surface of the interlayer 3 is cleaned using a plasma clean with N.sub.2O at 200 Watts for about 5 min. The waveguide layer 4 presently comprises or consists of Si-poor SiN.sub.x. The waveguide layer 4 is directly applied on the substrate 1, in particular directly on the interlayer 3 of the substrate 1. The waveguide layer 4 is deposited by PECVD using the parameters described in table 1.

TABLE-US-00001 TABLE 1 Parameters for PECVD deposition of Si-poor SiN.sub.x. Parameter Value Table Temperature 300 C. Chamber Pressure 650 mTorr N.sub.2 490 sccm NH.sub.3 40 sccm 5% SiH.sub.4 in Ar 160 sccm Low frequency electrode impedance 882 Ohms Low frequency power 20 W Low frequency period 7 s Low frequency pulsed? yes High frequency power 20 W High frequency period 13 s High frequency pulsed? No Estimated deposition rate 13.703 nm/min

[0084] The waveguide layer 4 presently has a thickness of about 3 micrometer. Table 2 shows extinction coefficients for the waveguide layer 4 depending on the wavelength. The extinction coefficient here and in the following is to be understood as the parameter b in the equation I(x)=I.sub.0*exp(b*x) where I is the intensity depending on a distance x along a waveguide.

TABLE-US-00002 TABLE 2 Extinction coefficients of a waveguide layer 4 with Si-poor SiN.sub.x and a thickness of about 3 micrometer. Wavelength (nm) Extinction coefficient (1/mm) 405 (purple) 0.521 450 (blue) 0.105 532 (green) 0.119 650 (red) 0.030

[0085] After the deposition of the waveguide layer 4, an adhesion layer 5 is deposited on the waveguide layer 4, as shown in FIG. 1C. The adhesion layer 5 presently comprises or consists of SiO.sub.2. A thickness of the adhesion layer 5 is about 10 nanometer. The adhesion layer 5 is deposited by PECVD using the parameters listed in table 3.

TABLE-US-00003 TABLE 3 Parameters for PECVD deposition of an adhesion layer 4 comprising SiO.sub.2. Parameter Value Table Temperature 300 C. Chamber Pressure 1000 mTorr N.sub.2O 710 sccm 5% SiH.sub.4 in Ar 150 sccm High frequency power 20 W Approximate deposition rate 60 nm/min

[0086] In a further step, as shown in FIG. 1D, an adhesion promoter 6 is applied on the waveguide layer 4. The adhesion promoter 6 is directly applied on the adhesion layer 5. Presently, the adhesion promoter 6 is hexamethyldisilazane (HMDS). The HMDS is applied on the waveguide layer 4 using spin coating. As absorption of moisture may affect an adhesion of the HMDS, an oxygen plasma clean may be used if the waveguide layer 4 was sitting for a significant amount of time. The parameters shown in table 4 were used during spin coating of the HMDS.

TABLE-US-00004 TABLE 4 HMDS spin coating parameters. Velocity Ramp Time Step (rpm) (rpm/s) (s) 1 500 200 5 2 5000 750 30 3 0 500 0

[0087] After applying the adhesion promoter 6, the waveguide layer 4 is heated for 3 min to 110 C. Then, a photostructurable mask 7 is applied on the adhesion promoter 6 by spin coating using the parameters shown in table 5.

TABLE-US-00005 TABLE 5 Photostructurable mask 7 spin coating parameters. Step Velocity (rpm) Ramp (rpm/s) Time (s) 1 500 200 5 2 6000 750 60 3 0 500 0

[0088] The photostructurable mask 7 is heated for 3 min to 110 C. Presently, the photostructurable mask 7 has a thickness of about 5 micrometer.

[0089] Before photostructuring, the photostructurable mask 7 is allowed to rehydrate. For this the photostructurable mask 7 was left in air for about 30 min.

[0090] As shown in FIG. 1E, the photostructurable mask 7 is photostructured such that the photostructurable mask 7 is removed in regions. For photostructuring, the photostructurable mask 7 is exposed to electromagnetic radiation in the regions. Presently, UV radiation is used. Detailed parameters for the exposure to electromagnetic radiation are described in table 6.

TABLE-US-00006 TABLE 6 Parameters for exposure to electromagnetic radiation. Parameter Value Exposure dose 6.1 s @ 24.9 mW/cm.sup.2 Wavelength 365 nm Alignment Gap 6 m Expose Type Hard Hard contact wait time 10 s WEC Type Contact WEC Offset Off

[0091] WEC is the abbreviation for wedge error compensation. The WEC type contact means that a structuring mask is in direct contact with the photostructurable mask 7 during exposure to electromagnetic radiation. The exposure type hard brings a structuring mask in direct contact with the photostructurable mask 7. The hard contact wait time represents a delay during which the structuring mask will be in contact with the photostructurable mask 7 before exposure to the electromagnetic radiation.

[0092] After exposure to electromagnetic radiation, the photostructurable mask 7 is developed using a developer. In this way, the photostructurable mask 7 is removed in the regions. Presently, a potassium-based buffered developer mixed with water is used as developer. The ratio of water to developer is 1:4. A development time was about 90 s.

[0093] In a next step of the method for producing a planar light circuit, the waveguide layer 4 is etched in the regions which are free of the photostructurable mask 7 (FIG. 1F). In this way, channels 8 are produced in the waveguide layer 4. The channels 8 confine waveguides 9. A channel 8 is directly adjacent to at least one waveguide 9. The channels 8 reach through the waveguide layer 4. That is the waveguide layer 4 is completely removed in the regions which are free of the photostructurable mask 7 after photostructuring. A bottom face of the channels 8 is formed by the substrate 1, in particular the interlayer 3 of the substrate 1. The waveguide layer 4 is etched by inductively coupled plasma (ICP) etching using various fluorine and carbon based gasses.

[0094] Before the etching of the waveguide layer 4, a reaction chamber for the inductively coupled plasma etching is cleaned. To clean the reaction chamber the parameters described in table 7 are set. A clean time is for example about 10 min.

TABLE-US-00007 TABLE 7 Parameters for reaction chamber cleaning. Parameter Value ICP Power 1500 W Electrode 150 W Chuck Temperature Setpoint 15 C. Backing helium pressure 0 Torr Chamber Pressure 20 mTorr O.sub.2 40 sccm SF.sub.6 10 sccm

[0095] After cleaning of the reaction chamber, the waveguide layer 4 is etched using the parameters listed in table 8. An etching time is about 12.5 minutes.

TABLE-US-00008 TABLE 8 Parameters for etching the waveguide layer 4. Parameter Value ICP Power 1250 W Electrode 15 W Chuck Temperature Setpoint 15 C. Backing helium pressure 5 Torr Chamber Pressure 6 mTorr SF.sub.6 6 sccm CHF.sub.3 26 sccm

[0096] During etching of the waveguide layer 4, the adhesive layer 4 is also removed in the regions free of the photostructurable mask 7.

[0097] As shown in FIG. 1G, the photostructurable mask 7 is removed after the waveguide layer 4 is etched such that channels 8 are produced in the waveguide layer 4. The photostructurable mask 7 is presently removed using a mixture of H.sub.2SO.sub.4 and H.sub.2O.sub.2 prepared from four parts 70% H.sub.2SO.sub.4 and one part 30% aqueous H.sub.2O.sub.2. This mixture is also called piranha solution. The photostructurable mask 7 is removed by soaking in the mixture for less than 10 min. Afterwards, the waveguide layer 4 is rinsed with deionized water.

[0098] As shown in FIG. 1H, a cladding 11 is applied on the waveguide layer 4 using PECVD. The cladding 11 reduces scattering loss and insertion loss. The cladding 11 has a thickness of about 2 micrometer. The parameters described in table 9 are used during PECVD.

TABLE-US-00009 TABLE 9 Parameters for applying the cladding 11 by PECVD. Parameter Value Table Temperature 400 C. Chamber Pressure 1500 mTorr N.sub.2O 480 sccm CF.sub.4 800 sccm 5% SiH.sub.4 in Ar 160 sccm High frequency power 20 W High frequency pulsed No Deposition time 20 min

[0099] The cladding 11 covers the waveguide layer 4. In particular, the cladding 11 is in direct physical contact with the adhesion layer 5. The channels 8 are partially filled with the cladding 8. Side faces 21 of the channels 8 and a bottom face 20 of the channels 8 formed by the substrate 1 are covered with the cladding 11.

[0100] To produce a planar light circuit 10, the wafer is singulated. For singulation, cleaving locations 12 are scored into the wafer. The planar light circuit 10 is obtained by cleaving at the cleaving locations 12, 13, 14 using pliers. An order of cleaving is shown in FIG. 2. The order is cleaving at the first cleaving locations 12 (hashed lines), then at the second cleaving locations 13 (dotted lines), and then at the third cleaving locations 14 (solid lines).

[0101] Additionally, the wafer is in particular diced, lapped, and polished. However, care must be taken to minimize chipping of facets of the waveguide.

[0102] The planar light circuits 10 shown in FIG. 2 each comprise a waveguide 9 comprising three branches 15, 16. Presently, the three branches 15, 16 merge together into a single branch 18 in a combining region 17. The waveguide 9 comprises a symmetry axis running parallel to the middle branch 16, seen in the top view of FIG. 2. The branches 15 comprise a curved shape.

[0103] FIGS. 3A and 3B each show results of ellipsometry measurements of waveguide layers 4. The waveguide layer 4 comprising compressively stressed Si-poor SiN.sub.x showing the measurements of FIG. 3B was produced using the parameters shown in table 1. The waveguide layer 4 comprising close to stoichiometric SiN.sub.x showing the measurements of FIG. 3A was produced using different parameters.

[0104] FIGS. 3A and 3B each show the refractive index n and the extinction coefficient k depending from the wavelength . The waveguide layer 4 comprising compressively stress Si-poor SiN.sub.x comprises a refractive index curve N2 and an extinction coefficient curve K2. The waveguide layer 4 comprising close to stoichiometric SiN.sub.x comprises a refractive index curve N1 and an extinction coefficient curve K1. The curves N2 and K2 both show a steeper slope than the curves N1 and K1. Furthermore, the refractive index of the waveguide layer 4 comprising compressively stress Si-poor SiN.sub.x is lower than that of the waveguide layer 4 comprising close to stoichiometric SiN.sub.x. The extinction coefficient of the waveguide layer 4 comprising compressively stress Si-poor SiN.sub.x is nearly unresolvable compared to the extinction coefficient of the waveguide layer 4 comprising close to stoichiometric SiN.sub.x.

[0105] FIG. 4 shows a plot of an estimated N/Si ratio versus a measured refractive index of a waveguide layer 4 comprising SiN, at a wavelength of 900 nanometer. The N/Si ratio may be estimated from the following equation:

[00003]$R{\left(\frac{N}{\mathrm{Si}}\right)}_{\mathrm{ratio}}=\frac{4}{3}\left(\frac{n_{\mathrm{Si}}-n_{\mathrm{waveguide}\mathrm{layer}}}{n_{\mathrm{waveguide}\mathrm{layer}}+n_{\mathrm{Si}}-2n_{\mathrm{Si}3N4}}\right).$

[0106] Here, n.sub.Si is the refractive index of a waveguide layer 4 consisting of Si, n.sub.Si3N4 is the refractive index of a waveguide layer 4 consisting of stoichiometric SiN.sub.x, that is Si.sub.3N.sub.4, and n.sub.waveguide layer is the refractive index of waveguide layer 4 consisting of non-stoichiometric SiN.sub.x. Presently, n.sub.Si=3.610 and n.sub.Si3N3=2.018.

[0107] Using the plot shown in FIG. 4, the N/Si ratio of the waveguide layer 4 leading to the graphs of FIG. 3A is determined to be about 0.94. That is this waveguide layer 4 comprises a SiN.sub.x with a close to stoichiometric composition. The waveguide layer 4 leading to the graphs of FIG. 3B comprises a N/Si of about 1.29. That is the waveguide layer 4 of FIG. 3B is Si-poor.

[0108] The SEM image shown in FIG. 5 is an intermediate stage during etching of a waveguide layer 4. The waveguide layer 4 is deposited on a substrate 1 comprising a substrate layer 2 with silicon and an interlayer 3 with SiO.sub.2. The waveguide layer 4 comprises Si-poor SiN.sub.x. A photostructurable layer 7 is arranged on the waveguide layer 4. Channels 8 reach into the waveguide layer 4. That is, a bottom face of the channels 8 is formed in the waveguide layer 4. In other words, the waveguide layer 4 shown in FIG. 4 is not completely etched through. Two channels 8 confine a waveguide 9.

[0109] FIG. 6 shows a SEM image of a top view of a stage of a method for producing a planar light circuit 10. Presently, the photostructurable mask 7 has not been removed yet. Due to the etching of the waveguide layer 4, the photostructurable mask 7 is polymerized on its surface. This polymerized residue 19 of the photostructurable mask 7 is hard to remove by solvents such as acetone.

[0110] FIG. 7 shows a SEM image of a top view of a planar light circuit 10 according to an exemplary embodiment. The planar light circuit 10 comprises a waveguide layer 4 with channels 8. The channels 8 reach through the waveguide layer 4 and confine a waveguide 9. The waveguide 9 presently comprises three branches 15, 16 which merge together into a single branch 18 in a combining region 17. Each branch 15, 16 is confined by channels 8.

[0111] In FIG. 8, a SEM image of a cross section of a planar light circuit 10 according to an exemplary embodiment is shown. The planar light circuit 10 comprises a substrate 1 having a substrate layer 2 and an interlayer 3. The substrate layer 2 comprises or consists of silicon, whereas the interlayer 3 comprises or consists of SiO.sub.2. A waveguide layer 4 is arranged in direct contact physical contact with the interlayer 3. Presently, the waveguide layer 4 comprises Si-poor SiN.sub.x. Channels 8 confine a waveguide 9 in the waveguide layer 4. The waveguide 9 is formed from the same material as the surrounding waveguide layer 4. In the cross-section, the waveguide 9 comprises a rectangular shape. Two faces of the waveguide 9 are directly adjacent to the channels 8. Another face of the waveguide 9 is directly adjacent to the interlayer 3.

[0112] The structure of the planar light circuit 10 shown in FIG. 9 is similar to the one shown in FIG. 8. However, the channels 8 and thus the waveguide 9 comprise a different shape, especially seen in cross-section. Presently, the side faces 21 of the channels 8 are not perpendicular to a main extension plane of the planar light circuit 10. Here, the side face 21 are slightly inclined. Thus, the channels 8 approximately comprise, seen in cross-section, the shape of a trapezoid.

[0113] The planar light circuit 10 shown as cross-section in FIG. 10A comprises a cladding 11 on the waveguide layer 4. Seen in top view, the cladding 11 preferably completely covers the waveguide layer 4. The channels 8 are partially filled by the cladding 11. In particular, the planar light circuit 10 shown in FIG. 10A has been produced by the method described in combination with FIGS. 1A to 1H.

[0114] The planar light circuit 10 shown in FIG. 10B is, in particular, the same as the one shown in FIG. 10A. The waveguide layer 4 is arranged on a substrate 1 comprising a substrate layer 2 and an interlayer 3. The waveguide layer 4 is in direct physical contact with the interlayer 3. The substrate 1 comprises presently a silicon substrate layer 2 and a SiO.sub.2 interlayer 3. The waveguide layer 4 comprises or consists of Si-poor SiN.sub.x.

[0115] Channels 8 run through the waveguide layer 4 such that a waveguide 9 is formed in the waveguide layer 4. Two channels 8 confine the waveguide 9. Thus, seen in cross-section, the channels 8 in the waveguide layer 4 and the waveguide 9 comprise a rectangular shape.

[0116] A cladding 11 is arranged on the waveguide layer 4. The cladding 11 partially fills the channels 8 in the waveguide layer 4. Presently, the cladding 11 comprises or consists of fluorine doped SiO.sub.2. Seen in the cross-section, the waveguide 9 surrounded by the cladding 11 has approximately the shape of a trapezoid with two rounded corners. This shape may be compared to the shape of a toast.

[0117] A bottom face and side faces of the channels 8 are covered by the cladding 11. A thickness of the cladding 11 is smaller at the bottom face 20 of the channels 8 than a top face 22 of the waveguide 9 facing away from the substrate 1. The thickness of the cladding 11 on the side faces 21 of the channels 8 decreases in a direction towards the bottom face 20 of the channels 8. In other words, the cladding 11 comprises an undercut in the region of the channels 8. A distance of the cladding 11 outside of the channels 8 in the waveguide layer 4 is smaller than inside the channels 8.

[0118] FIG. 10C shows the planar light circuit 10 of FIG. 10B enlarged. Furthermore, thicknesses of the cladding 11 and the waveguide 9 are shown. Seen in the cross-section of FIG. 10C, the waveguide 9 comprises a greater height than width. The height of the waveguide 9 is in particular perpendicular to a main extension plane of the planar light circuit 10, whereas the width is parallel to the main extension plane of the planar light circuit 10. Presently, the waveguide 9 comprises a height of about 3.37 micrometers and a width of about 2.76 micrometer.

[0119] At the bottom face 20 of the channels 8 the cladding 11 comprises a lower thickness than on the top face 22 of the waveguide 9. Presently, the thickness of the cladding 11 at the bottom face 20 is about 1.08 micrometers and the top face 22 of the waveguide 9 about 2.45 micrometers. The thickness of the cladding 11 on the side face 21 is about 844 nanometers in the region of the bottom face 20 of the channels 8. The thickness on the side face 21 increases to reach about 1.09 micrometers in the region of the top face 22 of the waveguide 9. The cladding 11 surrounding the waveguide 9 has a maximum width of about 5.48 micrometers in a region above the top face 22 of the waveguide 9. A distance between the cladding 11 on the waveguide 9 and the cladding 11 on the surrounding waveguide layer 4 is about 550 nanometers at the narrowest point.

[0120] FIG. 11 shows an image of a top view of a planar light circuit 10 according to an exemplary embodiment. The planar light circuit 10 comprises a waveguide 9 having three branches 15, 16. The three branches 15, 16 merge together into a single branch 18 in a combining region 17. The waveguide 9 comprises a symmetry axis which is parallel to the middle branch 16. Presently, the symmetry axis is an axis of reflection. The middle branch 16 changes into the single branch 18 without a bend. That is, the middle branch 16 and the single branch 18 are arranged on the same imaginary line. In other words, a starting point of the middle branch 16 and an end point and/or a starting point of the single branch 18 are on the same line.

[0121] The branches 15 comprise a curved shape in top view. For example, the branches 15 comprise a Bezir, a sigmoidal shape or the shape of a tangent function. A course of the branches 15, seen in top view, comprises at least one inflection point. A starting point of the two branches 15 is equally distanced to a starting point of the middle branch 16.

[0122] An efficiency of the planar light circuit 10 described herein was measured using both lens coupled laser diodes and butt-coupled laser diodes. The results are shown in table 10. During measurements a high NA microscope objective (NA=0.85) was used.

TABLE-US-00010 TABLE 10 Efficiencies of a planar light circuit 10. efficiency Wavelength Fast left middle right (nm) axis Polarization branch branch branch 450 Horizontal Vertical 0.347 0.371 0.341 450 Vertical Horizontal 0.489 0.485 0.493 532 Round Vertical 0.424 0.460 0.368 532 Round Horizontal 0.350 0.377 0.344 650 Horizontal Vertical 0.342 0.414 0.384 650 Vertical Horizontal 0.455 0.483 0.558 450 Vertical Horizontal 0.302 0.424 0.517 450 Vertical Horizontal 0.499 0.485 0.444 450 Vertical Horizontal 0.483 0.424 0.405

[0123] For 450 nanometer and 650 nanometer laser diodes, the fast axis is perpendicular to the polarization. In case of the 532 nanometer laser diode which is believed to be second harmonic converted, the beam is round, so there is no distinction of beam asymmetry with respect to polarization. The waveguides 9 in particular are taller than wide and have more cladding 11 in the vertical direction. The vertical direction is perpendicular to a main extension plane of the planar light circuit. This suggests that aligning the fast axis with the vertical direction should yield higher efficiency due to greater availability of modes and better confinement. This agrees with the experimental results for the 450 nanometer and 650 nanometer laser diodes. The 532 nanometer laser diode does not have this spatial asymmetry. In this case, the vertical polarized light seems to have increased efficiency.

[0124] Using a green edge emitting laser diode, light was coupled into the middle branch 16 of a planar light circuit 10 and an efficiency of 0.45 was achieved.

[0125] FIG. 12 shows a radiation emitting device 23 according to an exemplary embodiment. Presently, the radiation emitting device 23 comprises N laser diodes 24. The laser diodes 24 emit electromagnetic radiation of different wavelengths. The laser diodes 24 may be run continuous wave (CW), modulated, or pulsed (including alternating pulse patterns). The radiation emitting device 23 further comprises a planar light circuit 10 which is used as a beam combiner. The planar light circuit 10 comprises a waveguide 9 having N branches 15, 16. The branches 15, 16 merge together into a single branch 18 in combining regions 17. N1 branches 15 comprise a curved shape, whereas one branch 16 is linear. The radiation emitting device 23 is for example used in spectroscopy applications.

[0126] In the case of in-line or imaging spectroscopy using the radiation emitting device 23, the laser diodes 24 are sequentially (not in any particular order) switch on such that the desired wavelength appears at a source port of the spectroscopy system and the detector detecting the currently applied excitation wavelength. Furthermore, more sophisticated schemes can be employed whereby all laser diodes 24 can be pulsed or modulated at the same time. For example, an orthogonal pulse sequences such as a Hadamard orthogonal set is used for modulation. Alternatively, each laser diode 24 is modulated at a different frequency which can be independently detected via lock-in or down-conversion schemes.

[0127] The features and exemplary embodiments described in connection with the figures can be combined with each other according to further exemplary embodiments, even if not all combinations are explicitly described. Furthermore, the exemplary embodiments described in connection with the figures may have alternative or additional features as described in the general part.

[0128] The invention is not restricted to the exemplary embodiments by the description on the basis of said exemplary embodiments. Rather, the invention encompasses any new feature and also any combination of features, which in particular comprises any combination of features in the patent claims and any combination of features in the exemplary embodiments, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments.