Stacked buck converters and associated method of operation

Abstract

A converter includes two switching stages coupled in series between positive and negative input terminals. A control circuit is configured for driving the switching stages based on an output voltage of the converter. A first switching stage includes two switches coupled in series between a positive input terminal and a first node. A capacitor and an inductor are coupled in series between the two switches and a positive output terminal. A third switch is coupled between a node between the capacitor and the inductor and the negative input terminal. A second capacitor is coupled between the first node and the negative input terminal. A second switching stage includes a second node coupled to the first node. Two additional electronic switches are coupled in series between the second node and the negative input terminal. A second inductor is coupled between the two additional switches and the positive output terminal.

Claims

1. An electronic converter comprising: an input terminal configured to receive an input voltage; an output terminal configured to supply an output voltage; an output capacitor coupled to the output terminal; a first electronic switch coupled between the input terminal and the output terminal; a second electronic switch coupled between the first electronic switch and a first node; a first capacitor coupled between the first electronic switch and the output terminal; a first inductor coupled between the first capacitor and the output terminal; a third electronic switch coupled to a second node that is coupled between the first capacitor and the first inductor; a second capacitor coupled to the first node; a fourth electronic switch coupled between the first node and the output terminal; a second inductor coupled between the fourth electronic switch and the output terminal; a fifth electronic switch coupled to a third node that is coupled between the fourth electronic switch and the second inductor; and a control circuit configured to, during a switching cycle, close the first and fourth electronic switches and open the second, third, and fifth electronic switches to simultaneously cause a first current to flow from the input terminal to the output terminal via the first inductor, and a second current to flow from the first node to the output terminal via the second inductor, wherein the control circuit is configured to drive the first electronic switch with a first pulse width modulation (PWM) driving signal, and wherein the first PWM driving signal has a working cycle higher than 50%.

2. The electronic converter of claim 1, wherein the control circuit is configured to periodically close the first electronic switch with a predetermined fixed switching period.

3. The electronic converter of claim 1, wherein the control circuit is configured to: drive the second electronic switch with a second PWM driving signal, the second PWM driving signal being an inverted version of the first PWM driving signal; drive the third electronic switch with the second PWM driving signal; drive the fourth electronic switch with a third PWM driving signal; and drive the fifth electronic switch with a fourth PWM driving signal the fourth PWM driving signal being an inverted version of the third PWM driving signal.

4. The electronic converter of claim 1, wherein the control circuit is configured to periodically close the first electronic switch with a switching period, and to vary the switching period as a function of the output voltage.

5. The electronic converter of claim 1, wherein each of the first, second, third, fourth, and fifth electronic switches comprises respective metal-oxide semiconductor field-effect transistors (MOSFETs).

6. The electronic converter of claim 1, wherein each of the first, second, third, fourth, and fifth electronic switches comprises respective n-type transistors.

7. The electronic converter of claim 1, wherein the electronic converter is a step-down converter.

8. An electronic circuit comprising: a first terminal configured to receive an input voltage; a second terminal configured to be coupled to an output node via a first inductor; a third terminal configured to be coupled to the output node via a second inductor; a fourth terminal configured to be coupled to a first capacitor; a fifth terminal configured to be coupled to the second terminal via a second capacitor; a first electronic switch coupled between the first terminal and the fifth terminal; a second electronic switch coupled between the fifth terminal and the fourth terminal; a third electronic switch coupled to the second terminal; a fourth electronic switch coupled between the fourth terminal and the third terminal; a fifth electronic switch coupled to the third terminal; and a control circuit configured to generate an output voltage at the output node by controlling the first, second, third, fourth, and fifth electronic switches, wherein the control circuit is configured to, during a switching cycle, close the first and fourth electronic switches and open the second, third, and fifth electronic switches to simultaneously cause a first current to flow from the first terminal to the output node via the first inductor, and a second current to flow from the fourth terminal to the output node via the second inductor, wherein the control circuit is configured to drive the first electronic switch with a first pulse width modulation (PWM) having a working cycle higher than 50%.

9. The electronic circuit of claim 8, wherein the control circuit is configured to periodically close the first electronic switch with a predetermined fixed switching period.

10. The electronic circuit of claim 8, wherein the control circuit is configured to periodically close the first electronic switch with a switching period, and to vary the switching period as a function of the output voltage.

11. The electronic circuit of claim 8, wherein each of the first, second, third, fourth, and fifth electronic switches comprises respective metal-oxide semiconductor field-effect transistors (MOSFETs).

12. The electronic circuit of claim 8, wherein each of the first, second, third, fourth, and fifth electronic switches is an NMOS transistor.

13. An electronic converter comprising: an input terminal configured to receive an input voltage; an output terminal configured to supply an output voltage; an output capacitor coupled to the output terminal; a first electronic switch coupled between the input terminal and the output terminal; a second electronic switch coupled between the first electronic switch and a first node; a first capacitor coupled between the first electronic switch and the output terminal; a first inductor coupled between the first capacitor and the output terminal; a third electronic switch coupled to a second node that is coupled between the first capacitor and the first inductor; a second capacitor coupled to the first node; a fourth electronic switch coupled between the first node and the output terminal; a second inductor coupled between the fourth electronic switch and the output terminal; a fifth electronic switch coupled to a third node that is coupled between the fourth electronic switch and the second inductor; and a control circuit configured to control the first and fourth electronic switches so that, in a switching cycle, the first electronic switch is closed and the fourth electronic switch is open during a first period of time of the switching cycle, and the first electronic switch and the fourth electronic switch are both closed for a second period of time of the switching cycle.

14. The electronic converter of claim 13, wherein the control circuit is configured to periodically close the first electronic switch with a predetermined fixed switching period.

15. The electronic converter of claim 13, wherein the control circuit is configured to: drive the first electronic switch with a first pulse width modulation (PWM) driving signal; drive the second electronic switch with a second PWM driving signal, the second PWM driving signal being an inverted version of the first PWM driving signal; drive the third electronic switch with the second PWM driving signal; drive the fourth electronic switch with a third PWM driving signal; and drive the fifth electronic switch with a fourth PWM driving signal the fourth PWM driving signal being an inverted version of the third PWM driving signal.

16. The electronic converter of claim 15, wherein the first PWM driving signal has a working cycle higher than 50%.

17. The electronic converter of claim 13, wherein the control circuit is configured to periodically close the first electronic switch with a switching period, and to vary the switching period as a function of the output voltage.

18. The electronic converter of claim 13, wherein each of the first, second, third, fourth, and fifth electronic switches comprises respective transistors of the same type.

19. The electronic converter of claim 13, wherein each of the first, second, third, fourth, and fifth electronic switches comprises respective metal-oxide semiconductor field-effect transistors (MOSFETs).

20. The electronic converter of claim 13, wherein each of the first, second, third, fourth, and fifth electronic switches comprises an NMOS transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The embodiments of the present disclosure will now be described with reference to the annexed drawings, which are provided purely to way of non-limiting example, and in which:

(2) FIG. 1 shows a buck converter;

(3) FIG. 2 shows waveforms of the buck converter of FIG. 1;

(4) FIG. 3 shows an electronic converter according to the present description;

(5) FIG. 4 shows driving signals for a first operation of the converter of FIG. 3;

(6) FIGS. 5A to 5D show the operating steps for the driving illustrated in FIG. 4;

(7) FIG. 6 shows driving signals for a second operation of the converter of FIG. 3;

(8) FIGS. 7A to 7D show the operating steps for the driving illustrated in FIG. 6;

(9) FIGS. 8 and 9 show the embodiment of two modules that can be used for implementing the converter of FIG. 3; and

(10) FIGS. 10A, 10B, 11A, 11B, and 12-15 show various embodiments of electronic converters that use the modules of FIGS. 8 and 9.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(11) In the ensuing description, various specific details are illustrated aimed at providing an in-depth understanding of the embodiments. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that various aspects of the embodiments will not be obscured.

(12) Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in various points of this description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

(13) The references used herein are merely provided for convenience and hence do not define the sphere of protection or the scope of the embodiments.

(14) In the ensuing FIGS. 3 to 15, parts, elements, or components that have already been described with reference to FIGS. 1 to 2 are designated by the same references as the ones used previously in these figures; the description of these elements presented previously will not be repeated in what follows in order not to burden the present detailed description.

(15) FIG. 3 shows a first embodiment of an electronic converter 1a according to the present description. Also in this case, the electronic converter 1a comprises: two input terminals 10a and 10b configured for receiving a D.C. input voltage V.sub.in; and two output terminals 12a and 12b configured for supplying a D.C. output voltage V.sub.OUT.

(16) In the embodiment considered, the negative output terminal 12b is connected (for example, directly) to the negative input terminal 10b, which represents a ground GND. In the embodiment considered, a capacitor C.sub.OUT is connected (for example, directly) between the output terminals 12a and 12b.

(17) In the embodiment considered, four electronic switches HS1, RST, HS2, and LS2 are connected (for example, directly) in series between the input terminals 10a and 10b. For instance, in the embodiment considered, the switches HS1, RST, HS2, and LS2 are FETs, preferably an n-channel FETs, for example MOSFETs.

(18) In particular, in the embodiment considered, the intermediate point between the switches HS1 and RST, for example the source terminal of the transistor HS1/drain terminal of the transistor RST, is connected (for example, directly) via a capacitor C.sub.S and an inductor L1 to the output terminal 12a. In particular, a first terminal of the capacitor C.sub.S is connected to the intermediate point between the switches HS1 and RST, and the second terminal of the capacitor C.sub.S is connected through the inductor L1 to the terminal 12a. Moreover, a further electronic switch LS1, such as a FET, preferably an n-channel FET, for example a MOSFET, is connected (for example, directly) between the second terminal of the capacitor C.sub.S (i.e., the intermediate point between the capacitor C.sub.S and the inductor L1) and the negative input terminal 10b/ground GND.

(19) In the embodiment considered, the intermediate point between the switches HS2 and LS2, for example the source terminal of the transistor HS2/drain terminal of the transistor LS2, is connected (for example, directly) via an inductor L2 to the output terminal 12a.

(20) Finally, in the embodiment considered, the intermediate point between the switches RST and HS2, for example the source terminal of the transistor RST/drain terminal of the transistor HS2, is connected (for example, directly) via a capacitor C.sub.M to the negative input terminal 10b/ground GND.

(21) Hence, the electronic converter 1a illustrated in FIG. 3, comprises two buck stages/phases: the first phase is represented by the switches LS2, HS2 and the inductor L2; and the second phase is represented by the switches HS1, LS1, and RST, the capacitor C.sub.S, and the inductor L1.

(22) In particular, as compared to a conventional buck converter with capacitor in series (represented by the capacitor C.sub.S), the electronic converter 1a illustrated in FIG. 3 hence comprises the electronic switch, for example MOSFET, RST and the capacitor/capacitance C.sub.M. As will be explained hereinafter, thanks to the presence of these two components, the two buck phases may be completely independent, also with duty cycles greater than 50%. Moreover, the inventor has noted that the response of the system is substantially the equivalent response of a multiphase buck with two phases, it being able, in the event of load transient, to increase the duty cycle to values higher than 50% by superposing the ON periods of the switches HS1 and HS2, which is not possible with a traditional buck converter with series capacitor.

(23) In the embodiment considered, the electronic switches HS1, LS1, RST, HS2, and LS2 are hence driven via a control circuit 14.a that generates respective driving signals D.sub.HS1, D.sub.LS1, D.sub.RST, D.sub.HS2, and D.sub.LS2.

(24) In particular, in various embodiments, the driving signal D.sub.RST for the switch RST is in phase with the driving signals D.sub.HS1, D.sub.LS1 for the switches HS1 and LS1. Specifically, in various embodiments, the driving signal D.sub.LS1 for the switch LS1 corresponds to the inverted version of the driving signal HLS1 for the switch HS1, and the driving signal D.sub.RST for the switch RST corresponds to the driving signal D.sub.LS1 for the switch LS1; i.e., the control circuit 14a is configured for periodically repeating the following intervals: during a first interval T.sub.ON1, closing the switch HS1 and opening the switches LS1 and RST; and during a second interval T.sub.OFF1, opening the switch HS1 and closing the switches LS1 and RST.

(25) Consequently, in various embodiments, the switching period T.sub.SW1 for the switches HS1, LS1, and RST is T.sub.SW1=T.sub.ON1+T.sub.OFF1; i.e., driving of the switch HS1 corresponds to a pulse width modulation in which the working cycle is T.sub.ON1/T.sub.SW1.

(26) Likewise, the driving signals D.sub.HS2, D.sub.LS2 for the switches HS2 and LS2 are synchronised, and the driving signal D.sub.LS2 for the switch LS2 corresponds to the inverted version of the driving signal H.sub.LS2 for the switch HS2; i.e., the control circuit 14a is configured for repeating the following intervals periodically: during a first interval T.sub.ON2, closing the switch HS2 and opening the switch LS2; and during a second interval T.sub.OFF2, opening the switch HS2 and closing the switch LS2.

(27) Consequently, in various embodiments, the switching period T.sub.SW2 for the switches HS2 and LS2 is T.sub.SW2=T.sub.ON1+T.sub.OFF2; i.e., driving of the switch HS2 corresponds to a pulse width modulation in which the working cycle is T.sub.ON2/T.sub.SW2.

(28) In general, it is not required for the driving signals D.sub.HS2, D.sub.LS2 to be synchronised with the driving signals D.sub.HS1, D.sub.LS1, and D.sub.RST. However, for reasons of regulation it may be preferable for the driving signal D.sub.HS2 to have a constant phase P with respect to the driving signal D.sub.HS1. Consequently, in this case, the switching period T.sub.SW1 corresponds to the switching period T.sub.SW2, i.e., T.sub.SW1=T.sub.SW2.

(29) Moreover, in some embodiments, to minimise the ripple on the voltage V.sub.M across the capacitor C.sub.M, an interleaving of 50% between the two phases is preferable; i.e., the control circuit 14a is configured for closing the switch HS2 substantially at a time T.sub.SW1/2 from start of a switching cycle T.sub.SW1, i.e., from closing of the switch HS1. As mentioned previously, this is not necessary from the standpoint of operation of the topology in so far as it also enables superposition of ON periods of the two switches HS1 and HS2, unlike the prior art referred to.

(30) As will be explained in greater detail hereinafter, by adopting an appropriate driving of the switches HS1, LS1, RST, HS2, and LS2, these switches work at a maximum operating voltage across them of V.sub.in/2. For this reason, a class of FETs/MOSFETs with higher figures of merit can be used for improving the efficiency or else for doubling the switching frequency, and the output inductances L1 and L2 may be smaller, thus increasing the power density of the cell.

(31) Hence, assuming a phase shift P of 50% between the driving signals D.sub.HS1 and D.sub.HS2, there exist two driving scenarios: in the first case, with a duty cycle T.sub.ON1/T.sub.SW1 of less than 50%, the switch HS2 is set into the closed condition when the switch HS1 is open; and in the second case, with a duty cycle T.sub.ON1/T.sub.SW1 of more than 50%, the switch HS2 is set into the closed condition when the switch HS2 is open.

(32) The first case is schematically illustrated in FIG. 4, which shows an embodiment of the driving signals D.sub.HS1, D.sub.LS1, D.sub.RST, D.sub.HS2, and D.sub.LS2 for the switches HS1, LS1, RST, HS2, and LS2.

(33) In particular, in the embodiment considered, the control circuit 14a is configured for: at an instant t.sub.1, closing the switch HS1 and opening the switches LS1 and RST; at an instant t.sub.2, opening the switch HS1 and closing the switches LS1 and RST; at an instant t.sub.3, closing the switch HS2 and opening the switch LS2; and at an instant t.sub.4, opening the switch HS1 and closing the switch LS2.

(34) Consequently, during a first interval Δt1 (between the instants t.sub.1 and t.sub.2), the switches HS1 and LS2 are closed, and the switches LS1, RST, and HS2 are open. During a second interval Δt2 (between the instants t.sub.2 and t.sub.3), the switches LS1, RST, and LS2 are closed, and the switches HS1 and HS2 are open. During a third interval Δt3 (between the instants t.sub.3 and t.sub.4), the switches LS1, RST, and HS2 are closed, and the switches HS1 and LS2 are open. Finally, during a fourth interval Δt4 (between the instants t.sub.4 and the next instant t.sub.1′), the switches LS1, RST, and LS2 are closed, and the switches HS1 and HS2 are open.

(35) Hence, in the embodiment considered, the time T.sub.SW1 of a switching cycle corresponds to the sum of the duration of the four intervals, namely:
T.sub.SW1=T.sub.SW2=Δt1+Δt2+Δt3+Δt4.

(36) Moreover, the closing time T.sub.ON1 of the switch HS1 corresponds to the time Δt1, i.e., T.sub.ON1=Δt1, the closing time T.sub.ON2 of the switch HS2 corresponds to the time Δt3, i.e., T.sub.ON2=Δt3, and the phase shift P between the switches HS1 and HS2 is P=(Δt1+Δt2)/T.sub.SW1.

(37) FIG. 5A shows in this context operation during the first interval Δt1.

(38) This step substantially corresponds to an energising step. In particular, if the voltage across the capacitor C.sub.S is denoted by V.sub.S, the voltage on the first terminal of the inductor L1 (terminal connected to the capacitor C.sub.S) is equal to V.sub.in−V.sub.S (switch HS1 closed and switch LS1 open). Instead, the voltage on the second terminal of the inductor L1 corresponds to the voltage V.sub.OUT. In the embodiment considered, a voltage V.sub.in−V.sub.S−V.sub.OUT is hence applied to the inductor L1. Consequently, since the voltage on the inductor L1 should be positive during this operating step, the current I1 through the inductor L1 increases, as occurs in a traditional buck converter.

(39) Therefore, when the switch HS1 is set into the open condition and the switch LS1 is set into the closed condition, the first terminal of the inductor L1 (terminal connected to the capacitor C.sub.S) is now connected to the terminal 10b/ground GND. This is illustrated also in FIG. 5B. Consequently, during this operating step, the voltage on the inductor L1 is negative and the current I1 through the inductor L1 decreases, as occurs in a traditional buck converter.

(40) However, as also illustrated in FIG. 5B, during the second operating interval Δt2 also the switch RST is closed. Consequently, the capacitor C.sub.S is connected in parallel with the capacitor C.sub.M; i.e., the capacitor transfers a part of its charge onto the capacitor C.sub.S, and the voltage V.sub.M rises by an amount ΔV.sub.M1 given by the following formula:
ΔV.sub.M1=T.sub.ON1.Math.I1/(C.sub.S+C.sub.M)
where T.sub.ON1 corresponds to the duration Δt1, i.e., the ON time of the switch HS1.

(41) The charge accumulated during energising of the first phase (HS1, LS1, L1) of the converter is hence stored by using the switch RST in the capacitor C.sub.M. The charge stored in the capacitor C.sub.M can hence be used in turn for supplying the energy for the second phase of the converter (HS2, LS2, L2).

(42) Hence, as illustrated in FIG. 5C, during the interval Δt3, the switch HS2 is closed and the switch LS1 is open. In this case, the first terminal of the inductor L2 (terminal connected to the switch HS2) is thus connected to the capacitors C.sub.M and C.sub.S (the switches HS2 and RST are closed), i.e., to the voltage V.sub.M. Instead, the voltage on the second terminal of the inductor L2 corresponds to the voltage V.sub.OUT. In the embodiment considered, a voltage V.sub.M−V.sub.OUT is thus applied to the inductor L2. Consequently, since the voltage on the inductor L2 should be positive during this operating step, the current I2 through the inductor L2 increases, as occurs in a traditional buck converter.

(43) Consequently, when the switch HS2 is set into the open condition and the switch LS3 is set into the closed condition, the first terminal of the inductor L2 (terminal connected to the switch HS2) is now connected to the terminal 10b/ground GND. This is also illustrated in FIG. 5D. Hence, during this operating step, the voltage on the inductor L2 is negative, and the current I2 through the inductor L2 decreases, as occurs in a traditional buck converter.

(44) In particular, the charge subtracted by the second phase of the converter (HS2, LS2, L2) from the capacitor C.sub.M will produce a variation of voltage ΔV.sub.M2, given by the following formula:
ΔV.sub.M2=T.sub.ON2.Math.I2/(C.sub.S+C.sub.M)

(45) Instead, when the working cycle is longer than the phase shift P (e.g., higher than 50%), superposition of energisation of the first phase (HS1, LS1, and L1) with switching of the second phase (HS2, LS2, and L2) produces a slightly different sequence.

(46) In particular, as illustrated in FIG. 6, in various embodiments, the control circuit 14a is configured for: at an instant t.sub.5, closing the switch HS1 and opening the switches LS2 and RST; at an instant t.sub.6, opening the switch HS2 and closing the switch LS2; at an instant t.sub.7, closing the switch HS2 and opening the switch LS2; and at an instant t.sub.8, opening the switch HS1 and closing the switches LS1 and RST.

(47) Consequently, during a first interval Δt5 (between the instants t.sub.5 and t.sub.6), the switches HS1 and HS2 are closed, and the switches LS1, RST, and LS2 are open. During a second interval Δt6 (between the instants t.sub.6 and t.sub.7), the switches HS1 and LS2 are closed, and the switches LS1, RST, and HS2 are open. During a third interval Δt7 (between the instants t.sub.7 and t.sub.8), the switches HS1 and HS2 are closed, and the switches LS1, RST, and LS2 are open. Finally, during a fourth interval Δt8 (between the instant t.sub.8 and the next instant t.sub.5′), the switches LS1, RST, and HS2 are closed, and the switches HS1 and LS2 are open.

(48) Hence, in the embodiment considered, the time of a switching cycle corresponds to the sum of the duration of the four intervals, i.e.,
T.sub.SW1=T.sub.SW2=Δt5+Δt6+Δt7Δt8

(49) Moreover, the closing time T.sub.ON1 of the switch HS1 corresponds to the sums of the times Δt5, Δt6, and Δt7, i.e., T.sub.ON1=Δt5+Δt6+Δt7, the closing time T.sub.ON2 of the switch HS2 corresponds to the sums of the times Δt7, Δt8 and Δt5, i.e., T.sub.ON2=Δt7+Δt8+Δt5, and the phase shift P between the switches HS1 and HS2 is P=(Δt5+Δt6)/T.sub.SW1.

(50) FIG. 7A shows, in this context, operation during the first interval Δt5.

(51) In particular, as explained previously, during this operating step, the switches HS1 and HS2 are closed, whereas the switches LS1, RST and LS2 are open. This operating step is hence peculiar in so far as it is not possible with the solution according to the prior art.

(52) In particular, the voltage on the first terminal of the inductor L1 (terminal connected to the capacitor C.sub.S) is again equal to V.sub.in−V.sub.S (switch HS1 closed and switch LS1 open). Instead, the voltage on the first terminal of the inductor L2 (terminal connected to the switch HS2) is equal to V.sub.M (switch HS2 closed and switch RST open). The voltage on the second terminal of the inductor L1 and the voltage on the second terminal of the inductor L2 in any case correspond to the voltage V.sub.OUT. Consequently, since the voltages V.sub.in−V.sub.S and V.sub.M should be higher than the voltage V.sub.OUT, the currents I1 and I2 increase.

(53) Next, as illustrated in FIG. 7B, the switch HS2 is set into the open condition and the switch LS2 is set into the closed condition. Consequently, from the instant t.sub.6 the voltage on the first terminal of the inductor L2 (terminal connected to the switch HS2) is equal to zero and the current I2 decreases, whereas the current I1 of the first phase of the converter (HS1, LS1, and L1) continues to increase.

(54) The above operating step Δt6 hence finishes at the instant t.sub.7, when the control circuit 14a opens the switch LS2 and closes the switch HS2. Consequently, this situation basically corresponds to the one described with reference to FIG. 7A; i.e., the current I2 in the capacitor L2 starts to increase, and the current I1 of the first phase of the converter (HS1, LS1, and L1) continues to increase.

(55) Finally, as also illustrated in FIG. 7D, at the instant t.sub.8 the control circuit 14a opens the switch HS1 and closes the switch LS1. Consequently, from the instant t.sub.8 the voltage on the first terminal of the inductor L1 (terminal connected to the capacitor C.sub.S) is equal to zero, and the current I1 decreases, whereas the current I1 of the second phase of the converter (HS2, LS2, and L2) continues to increase.

(56) However, during this step also the switch RST is set into the closed condition; i.e., the charge accumulated by the capacitor C.sub.S during the other steps is transferred in part onto the capacitor C.sub.M (see also the description of FIG. 5C).

(57) Consequently, also in this case, the charge stored in the capacitor C.sub.S during energization of the first phase of the converter (HS1, LS1, and L1) is transferred onto the capacitor C.sub.M and is used by the second phase of the converter (HS2, LS2, and L2). Hence, by equating the ON times T.sub.ON1 and T.sub.ON2 of the switches HS1 and HS2, automatically the balance of the currents in the inductors L1 and L2 is obtained in so far as:
T.sub.ON1.Math.I1=T.sub.ON2.Math.I2

(58) In fact, in the case where T.sub.ON1=T.sub.ON2, also the currents are equal, i.e., I1=I2.

(59) Consequently, in various embodiments, the control circuit 14a is configured for driving the switches HS1 and HS2 with the same ON time T.sub.ON1=T.sub.ON2 and with the same OFF time T.sub.OFF1=T.sub.OFF2. Moreover, in some embodiments, the control circuit 14a is configured for regulating the duration T.sub.ON1 and/or T.sub.OFF1 as a function of the output voltage V.sub.OUT in such a way as to regulate the output voltage V.sub.OUT on a required value. In this way, a current-sharing correction by the controller 14a is not required.

(60) For instance, in various embodiments, the controller 14a is configured for using a constant time T.sub.SW1 for the switching cycle and for regulating the duration T.sub.ON1 in such a way that the output voltage V.sub.OUT corresponds to a required value; i.e., the controller 14a can implement a PWM regulation.

(61) For instance, for this purpose, the control circuit 14a can implement a regulator that comprises at least one I (Integral) component, such as a PI (Proportional-Integral) regulator or a PID (Proportional-Integral-Derivative) regulator.

(62) In general, a similar PWM regulation could also be obtained with one or more comparators, which are configured for: increasing the time T.sub.ON1 when the voltage V.sub.OUT is below a lower threshold; and reducing the time T.sub.ON1 when the voltage V.sub.OUT is above an upper threshold.

(63) However, a regulation system in which the time T.sub.ON1 is variable and the time T.sub.SW1 is constant may present problems of instability, in particular during load transients, i.e., when the load changes. In this case, also problems of current sharing between the phases of the converter may emerge.

(64) Consequently, in various embodiments, the control circuit 14a is configured for using a constant ON time T.sub.ON1=T.sub.ON2, whereas the OFF time T.sub.OFF1=T.sub.OFF2 is variable; i.e., the control circuit 14a varies the time of the switching cycle T.sub.SW1=T.sub.SW2. For instance, for this purpose reference may be made to the document U.S. Pat. No. 8,963,519 B2, which describes a control circuit configured for varying the frequency of the switching cycle (1/T.sub.SW1) as a function of the output voltage V.sub.OUT. Consequently, also in this case, the switch HS1 (and likewise the switch HS2) is driven by using a PWM driving signal, where the ON time T.sub.ON is constant and the duration of the switching cycle T.sub.SW is variable. For instance, also for this purpose, a regulator with I component, for example a PI or PID regulator, may be used.

(65) In the solution described previously, the converter 1a hence comprises two buck stages, which are connected in series between the input terminals 10a and 10b. The inventor has noted that this configuration is useful for output voltages V.sub.OUT close to 0.5V.sub.in. In order to regulate lower output voltages V.sub.OUT, it is possible to set a number of buck stages in series in order to work with input voltages of the individual buck stages equal to V.sub.in/N, where N is the number of buck stages connected in series.

(66) In particular, by grouping the components together, it is possible to define two types of buck stages. The first type of buck stage, referred to hereinafter as “SPH” (Stacked PHase), comprises the switches HS1, LS1, and RST, as well as the capacitor C.sub.S and the inductor L1. Instead, the second type of buck stage, referred to hereinafter as “BPH” (Buck Phase), comprises the switches HS2 and LS2, and the inductor L2.

(67) In particular, FIG. 8 shows an embodiment of the stage SPH, which enables a modular converter to be obtained.

(68) In particular, in the embodiment considered, the module SPH comprises four terminals 100, 102, 104, and 120. In particular, two electronic switches HS1 and RST are connected (for example, directly) in series between the terminals 100 and 102. For instance, in the embodiment considered, two n-channel FETs (e.g., MOSFETs) are used, where the drain terminal of the transistor HS1 is connected (for example, directly) to the terminal 100, the source terminal of the transistor HS1 is connected (for example, directly) to the drain terminal of the transistor RST, and the source terminal of the transistor RST is connected (for example, directly) to the terminal 102. A capacitor C.sub.S and an inductor L1 are connected (for example, directly) in series between the intermediate point between the switches HS1 and RST (e.g., the source terminal of the switch HS1) and the terminal 120. In particular, a first terminal of the capacitor C.sub.S is connected (for example, directly) to the switches HS1 and RST, and the second terminal of the capacitor C.sub.S is connected (for example, directly) by via the inductor L1 to the terminal 120. Finally, an electronic switch LS1 is connected between the intermediate point between the capacitor C.sub.S and the inductor L1 and the terminal 104. For instance, in the embodiment considered an n-channel FET (e.g., a MOSFET) is used, where the drain terminal of the transistor LS1 is connected (for example, directly) to the capacitor C.sub.S and the source terminal of the transistor LS1 is connected (for example, directly) to the terminal 104.

(69) Consequently, with reference to FIG. 3, the module illustrated in FIG. 8 can be used for the first phase of the electronic converter 1a when: the terminal 100 is connected to the terminal 10a, the terminal 102 is connected to the capacitor C.sub.M, the terminal 104 is connected to the terminal 10b, i.e., ground GND, and the terminal 120 is connected to the terminal 12a.

(70) In the embodiment considered, the module SPH further comprises an optional control circuit 140. For instance, in various embodiments, this control circuit 140 is configured for driving the switches HS1, RST, and LS1 as a function of a PWM driving signal received on a further terminal PWM1. For instance, the driving signal applied to the terminal PWM1 may correspond to the driving signal D.sub.HS1 for the switch HS1, and the control circuit 140 may generate the driving signals D.sub.RST and D.sub.LS1 for the switches RST and LS1 by inverting the aforesaid driving signal.

(71) In general, as for the capacitor C.sub.S, the module SPH may also comprise the capacitor C.sub.M. For instance, this capacitor C.sub.M may be connected (for example, directly) between the terminals 102 and 104.

(72) Instead, FIG. 9 shows an embodiment of the stage BPH that enables a modular converter to be obtained.

(73) In particular, in the embodiment considered, the module BPH comprises three terminals 106, 108, and 122. In particular, two electronic switches HS2 and LS2 are connected (for example, directly) in series between the terminals 106 and 108. For instance, in the embodiment considered, two n-channel FETs (e.g., MOSFETs) are used, where the drain terminal of the transistor HS2 is connected (for example, directly) to the terminal 106, the source terminal of the transistor HS2 is connected (for example, directly) to the drain terminal of the transistor LS2, and the source terminal of the transistor LS2 is connected (for example, directly) to the terminal 108. An inductor L2 is connected (for example, directly) between the intermediate point between the switches HS2 and LS2 (e.g., the source terminal of the switch HS1) and the terminal 122.

(74) Consequently, with reference to FIG. 3, the module illustrated in FIG. 9 may be used for the second phase of the electronic converter 1a when: the terminal 106 is connected to the capacitor C.sub.M, the terminal 108 is connected to the terminal 10b, i.e., ground GND, and the terminal 122 is connected to the terminal 12a.

(75) In the embodiment considered, the module BPH further comprises an optional control circuit 142. For instance, in various embodiments, this control circuit 142 is configured for driving the switches HS2 and LS2 as a function of a PWM driving signal received on a further terminal PWM2. For instance, the driving signal applied to the terminal PWM2 may correspond to the driving signal D.sub.HS2 for the switch HS2, and the control circuit may generate the driving signal D.sub.LS2 for the switch LS2 by inverting the aforesaid driving signal.

(76) Consequently, to implement a multiphase converter, all the buck stages except one (the one connected to ground GND) will comprise the module SPH so as to scale the voltage at input to each buck. Only the last buck stage connected to ground GND does not need to scale the voltage, and it is hence possible to implement the aforesaid buck stage with a simplified stage BPH.

(77) For instance, FIG. 10A shows an embodiment of an electronic converter, which comprises three buck stages connected in series. Consequently, the converter comprises two stages SPH.sub.1 and SPH.sub.2 and one stage BPH.

(78) In particular, the terminal 100 of the stage SPH.sub.1 is connected to the terminal 10a, the terminal 102 of the stage SPH.sub.1 is connected to the terminal 100 of the stage SPH.sub.2, the terminal 102 of the stage SPH.sub.2 is connected to the terminal 106 of the stage BPH, and the terminal 108 of the stage BPH is connected to the terminal 10b. Moreover, the terminals 120 and 122 of the stages SPH.sub.1, SPH.sub.2 and BPH are connected to the terminal 12a, where a capacitor C.sub.OUT is connected between the output terminals 12a and 12b.

(79) Also illustrated in the embodiment considered are two capacitors C.sub.M1 and C.sub.M2, where the first capacitor C.sub.M1 is connected between the terminal 102 of the stage SPH.sub.1 and ground GND, and the second capacitor C.sub.M2 is connected between the terminal 102 of the stage SPH.sub.2 and ground GND.

(80) In the embodiment considered, moreover illustrated is a control circuit 144 configured for generating the driving signals that are applied to the terminals PWM1 and PWM2 of the stages SPH.sub.1, SPH.sub.2, and BPH. Consequently, in the embodiment considered, the control circuits 140, 142, and 142 implement the control circuit 14a.

(81) For instance, in the embodiment considered, the control circuit 144 generates three PWM signals: APWM0 for the module SPH.sub.1, APWM120 for the module SPH.sub.2, and APWM240 for the module BPH.

(82) For instance, FIG. 10B shows an embodiment of the signals APWM0, APWM120, and APWM240. In particular, in the embodiment considered the three signals APWM0, APWM120, and APWM240 correspond to three PWM signals that have the same switching period T.sub.SW and the same ON time T.sub.ON, i.e., the same working cycle. However, the signals APWM0, APWM120, and APWM240 are phase-shifted with respect to one another. For instance, in the embodiment considered, the phase shift between the various signals is 120°.

(83) Instead, FIG. 11A shows an embodiment of an electronic converter that comprises four buck stages connected in series. Consequently, the converter comprises three stages SPH.sub.1, SPH.sub.2, and SPH.sub.3, and one stage BPH.

(84) In particular, the terminal 100 of the stage SPH.sub.1 is connected to the terminal 10a, the terminal 102 of the stage SPH.sub.1 is connected to the terminal 100 of the stage SPH.sub.2, the terminal 102 of the stage SPH.sub.2 is connected to the terminal 100 of the stage SPH.sub.3, the terminal 102 of the stage SPH.sub.3 is connected to the terminal 106 of the stage BPH, and the terminal 108 of the stage BPH is connected to the terminal 10b. Moreover, the terminals 120 and 122 of the stages SPH.sub.1, SPH.sub.2, SPH.sub.3, and BPH are connected to the terminal 12a, where a capacitor C.sub.OUT is connected between the output terminals 12a and 12b.

(85) Also illustrated in the embodiment considered are three capacitors C.sub.M1, C.sub.M2, and C.sub.M3, where the first capacitor C.sub.M1 is connected between the terminal 102 of the stage SPH.sub.1 and ground GND, the second capacitor C.sub.M2 is connected between the terminal 102 of the stage SPH.sub.2 and ground GND, and the third capacitor C.sub.M3 is connected between the terminal 102 of the stage SPH.sub.3 and ground GND.

(86) Again illustrated in the embodiment considered is a control circuit 144 configured for generating the driving signals that are applied to the terminals PWM1 and PWM2 of the stages SPH.sub.1, SPH.sub.2, SPH.sub.3, and BPH. In particular, in the embodiment considered, the control circuit 144 generates four PWM signals: APWM0 for the module SPH.sub.1; APWM180 for the module SPH.sub.2; APWM90 for the module SPH.sub.3; and APWM270 for the module BPH.

(87) For instance, FIG. 11B shows an embodiment of the signals APWM0, APWM90, APWM180, and APWM270. In particular, in the embodiment considered, the four signals APWM0, APWM90, APWM180, and APWM270 correspond to PWM signals that have the same switching period T.sub.SW and the same ON time T.sub.ON, i.e., the same working cycle. However, the signals APWM0, APWM90, APWM180, and APWM270 are phase-shifted with respect to one another. For instance, in the embodiment considered, the phase shift between the various signals is 90 °.

(88) As shown in FIG. 12, the electronic converter 1a may hence comprise N stages connected in series, where the first N-1 stages are of the type SPH illustrated in FIG. 8, where each stage SPH has associated a respective capacitor C.sub.M1, . . . , C.sub.MN-1, and the last stage is of the type BPH illustrated in FIG. 9.

(89) In this context, the control circuit 14a, for example implemented with the circuits 140, 142, and 144, can drive the various stages with any phase shift.

(90) For this purpose, the control circuit 14a can drive the electronic switch HS1 of each stage/module SPH with a respective PWM driving signal D.sub.HS1 having a given period T.sub.SW and a given ON time T.sub.ON. For instance, in the embodiment considered, the driving circuit 144 generates for this purpose respective driving signals APWM.sub.1, . . . , APWM.sub.N-3 for the stages SPNH.sub.1, . . . , SPH.sub.N-1. Moreover, the control circuit 14a can open the electronic switches RST and LS1 when the electronic switch HS1 is closed, and close the electronic switches RST and LS1 when the electronic switch HS1 is open. For instance, using n-channel FETs for all the switches, the control circuit 14a can generate driving signals D.sub.RST and D.sub.LS1 that correspond to the signal D.sub.HS1 inverted.

(91) In addition, the control circuit 14a can drive the electronic switch HS2 of a stage/module BPH with a PWM driving signal D.sub.HS2 having the period T.sub.SW and the ON time T.sub.ON. For instance, in the embodiment considered, the driving circuit 144 for this purpose generates, for the stage BPH, a respective driving signal APWM.sub.N. Moreover, the control circuit 14a can open the electronic switch LS2 when the electronic switch HS2 is closed, and close the electronic switch LS2 when the electronic switch HS2 is open. For instance, using n-channel FETs for all the switches, the control circuit 14a can generate a driving signal D.sub.LS2 that corresponds to the signal D.sub.HS2 inverted.

(92) Finally, in various embodiments, the control circuit 14a varies the ON time T.sub.ON or preferably the period T.sub.SW as a function of the output voltage V.sub.OUT, in particular for regulating the output voltage V.sub.OUT on a required value.

(93) As explained previously, the control circuit 14a can use any phase shift for the various stages. For instance, the phase shift between the sequences of PWM driving signals (for example, the signals APWM.sub.1, . . . , APWM.sub.N) can be chosen by the user as a function of the board, the coupling between the output coils, or other factors. In fact, as explained previously, the PWM driving signal of one stage may have any phase shift with respect to that of the next or previous stage comprised between 0° and 360°.

(94) In various embodiments, to increase the current-carrying capacity of the system, it is possible to set a number of structures in parallel, thus creating a matrix structure.

(95) For instance, FIG. 13 shows a 2×2 configuration. In particular, in this case, a first stage ASPH of the type SPH (see FIG. 8) and a first stage ABPH of the type BPH (see FIG. 9) are connected in series between the input terminals 10a and 10b, where the terminals 120 and 122 of the stages ASPH and ABPH are connected to the positive output terminal 12a and a capacitor AC.sub.M is associated to the stage ASPH, for example connected to the terminal 102 of the stage ASPH, which is in turn connected to the terminal 106 of the stage ABPH. Moreover, a second stage BSPH of the type SPH and a second stage BBPH of the type BPH are connected in series between the input terminals 10a and 10b, where also the terminals 120 and 122 of the stages BSPH and BBPH are connected to the positive output terminal 12a and a capacitor BC.sub.M is associated to the stage BSPH, for example connected to the terminal 102 of the stage BSPH, which is in turn connected to the terminal 106 of the stage BBPH.

(96) In the embodiment considered, the control circuit 14a hence generates the driving signals for the switches of the various stages. For instance, in the embodiment considered, the control circuit 144 generates driving signals APWM.sub.1, and APWM.sub.2 for the stages ASPH and ABPH, respectively, and driving signals BPWM1 and BPWM2 for the stages BSPH and BBPH, respectively.

(97) In various embodiments, the aforesaid driving signals are PWM signals that have the same period T.sub.SW. Moreover, the driving signals of the stages of one and the same chain/column, for example the stages ASPH and ABPH, have the same ON time T.sub.ON.

(98) In various embodiments, the phase shift between the driving signals APWM1, APWM2, BPWM1, and BPWM2 may be chosen, for example so as to minimise the capacitances AC.sub.M and BC.sub.M. For instance, in various embodiments, the driving signal APWM.sub.1 is in phase with the driving signal BPWM.sub.2; and the driving signal APWM.sub.2 is in phase with the driving signal BPWM.sub.1, where the driving signal APWM.sub.2 is preferably phase-shifted by 180° with respect the driving signal APWM.sub.1.

(99) The inventor has noted that in this way it is also possible to carry out an operation of current sharing in order to equalise the supplied currents of the two columns.

(100) In particular, for this purpose, the control circuit 144 can vary the time T.sub.ON of each column. For instance, in the case where the first column (ASPH and ABPH) were to carry more current, the control circuit 144 can decrease the time T.sub.ON of this column and/or increase that of the second column (BSPH and BBPH).

(101) As illustrated in FIG. 14, the topology may hence be generalised to a structure of N×M stages.

(102) In particular each of the M columns comprises N stages connected in series, where: the first stage is a stage SPH, with the terminal 100 connected to the positive input terminal 10a; the last stage is a stage BPH, where the terminal 106 is connected to the terminal 102 of the previous stage SPH and the terminal 108 is connected to the negative input terminal 10a; and the intermediate stages are all stages SPH, with the terminal boo connected to the terminal 102 of the previous stage SPH.

(103) All the columns are then connected in parallel between the terminals 10a and 10b, and the terminals 120 of all stages SPH and the terminals 122 of all staged BPH are connected to the positive output terminal 12a, which is in turn connected by means of one or more capacitors C.sub.OUT to the negative output terminal 12b.

(104) In the embodiment considered, the control circuit 14a can hence again generate the driving signals for the switches. For instance, in the embodiment considered, the control circuit 144 generates N×M PWM driving signals.sub.1,1 . . . PWM.sub.N,M, which all have the same period T.sub.SW.

(105) However, the control circuit can vary the ON time T.sub.ON of each column in order to implement a current-sharing correction. In particular, as explained previously, the possibility of driving each stage of one and the same column with the same ON time T.sub.ON leads to having an automatic balancing of the current within the cells of one and the same column. However, it may be advantageous to correct the unbalancing of the currents between different columns to prevent problems of reliability, for example due to the greater heating of the stages that carry more current, and moreover to prevent, in the worst cases, saturation of the cores of the output inductors. To do this, it is possible to use any multiphase control, with fixed frequency or variable frequency. In fact, in general it is sufficient for all the stages SPH and BPH of one column to use PWM driving signals with one and the same period T.sub.SW and one and the same ON time T.sub.ON.

(106) In particular, in various embodiments, the control circuit 14a (for example, by using an appropriate configuration of the circuit 144) is configured for regulating first the period T.sub.SW to obtain the required output voltage V.sub.OUT. Next, the control circuit 14a detects whether the load remains stable, for example because the control circuit 14a no longer varies the period T.sub.SW. Then, when the load is stable, i.e., in the absence of transients, the control circuit 14a varies the ON time T.sub.ON of each column in such a way as to implement a current-sharing correction.

(107) For instance, FIG. 15 shows a possible embodiment of the control circuit 144 configured for generating P driving signals PWM.sub.1, . . . , PWM.sub.P for P stages SPH and BPH. In various embodiments, the parameter P may be programmable. For instance, with reference to FIG. 14, the parameter P corresponds to N×M.

(108) In the embodiment considered, the control circuit 144 comprises a finite-state machine 1440. In particular, the finite-state machine 1440, implemented for example by using a digital circuit, is configured for generating, in response to a clock signal CLK P clock signals CK.sub.1, . . . , CK.sub.P at a lower frequency. In particular, the circuit 1440 generate P clock signals CK.sub.1, . . . , CK.sub.P that have the same period, which hence identifies the period T.sub.SW. In various embodiments, each signal CK produced has a phase shift with respect to the previous and next signal CK of +/−360°/P. Hence, by varying the frequency of the clock signal CLK, the period T.sub.SW can be varied for all the driving signals.

(109) In the embodiment, the signals CK.sub.1, . . . , CK.sub.P are then supplied to a selection circuit 1442 that associates one of the clock signals CK.sub.1, . . . , CK.sub.P to each driving signal PWM.sub.1, . . . , PWM.sub.P. For instance, for this purpose the circuit 1442 can receive, for each signal PWM.sub.1, . . . , PWM.sub.P, a respective selection signal PH_SEL.sub.1, . . . , PH_SEL.sub.P. In general, the circuit 1442 is purely optional, since the assignment of the signals CK.sub.1, . . . , CK.sub.P to the signals PWM.sub.1, . . . , PWM.sub.P could also be fixed at a hardware level.

(110) Finally, the circuit 144 comprises a circuit 1444 configured for varying the ON time T.sub.ON1, . . . , T.sub.ONP of each signal PWM.sub.1, . . . , PWM.sub.P.

(111) For this purpose, the circuit 1444 can receive data CS_SEL.sub.1, . . . , CS_SEL.sub.P, which associate each signal PWM.sub.1, . . . , PWM.sub.P to a respective column 1, . . . , M of the matrix of stages N×M (see also FIG. 14). In general, this function of the circuit 1444 is purely optional, since the assignment of the PWM.sub.1, . . . , PWM.sub.P to the columns 1, . . . , M could also be fixed at a hardware level.

(112) Moreover, the circuit 1444 receives data that identify the phase shift of the current CS_COL.sub.1, . . . , CS_COL.sub.M of each column 1, . . . , M. Hence, the circuit 1444 can vary the ON time T.sub.ON1, . . . , T.sub.ONP of the signals PWM.sub.1, . . . , PWM.sub.P in such a way that all the signals PWM.sub.1, . . . , PWM.sub.P that belong to one and the same column (as identified, for example, by the signals CS_SEL.sub.1, . . . , CS_SEL.sub.P) have the same ON time T.sub.ON, and the circuit varies this duration as a function of the data CS_COL.sub.1, . . . , CS_COL.sub.M.

(113) Of course, without prejudice to the principle of the invention, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated purely by way of example herein, without thereby departing from the scope of the present invention, as defined by the ensuing claims.