ESD-protection device and MOS-transistor having at least one integrated ESD-protection device

Abstract

Protection against electrostatic discharges is to be improved for electronic devices, or is to be provided in the first place. The device for protection against electrostatic discharges having an integrated semiconductor protection device comprises an inner region (1) configured at least as a thyristor (SCR) and at least one outer region (2a, 2b) configured as a corner region, which is formed and configured at least as a PNP transistor. The inner region (1) and the at least one outer region (2a, 2b) are arranged adjacent to one another.

Claims

1. A device for protection against electrostatic discharges with an at least one integrated semiconductor protection device, comprising: an inner region configured as a thyristor (SCR); and at least one outer region as a corner region configured as at least one PNP transistor and adapted to protect against electrostatic discharges, the inner region and the at least one outer region being arranged adjacent to one another, the at least one outer region comprising: at least one first outer region p-doped region (A-P+) that is connected to at least one anode terminal (A); at least one first N-well (HV-NWELL) having arranged therein at least one first outer reaion n-doped region (D-N+) and the at least one first outer reaion p-doped region (A P+); at least one second outer region p-doped region (B-P+) having connected thereto a bulk terminal (B); at least one P-well (PWELL) having arranged therein the at least one second outer reaion p-doped region (B-P+); and at least one outer region isolation region (I) arranged between the at least one first outer reaion n-doped region (D-N+) and the at least one first outer reaion p-doped region (A-P+) on one side, and the at least one second outer reaion p-doped region (B-P+) on an opposite side thereof, wherein a gate terminal (G) is arranged above the at least one outer region isolation region (I); wherein the at least one PNP transistor in the at least one outer region is configured by the at least one first outer reaion p-doped region (A-P+), the at least one first N-well (HV-NWELL) and the at least one P-well (PWELL).

2. The device according to claim 1, wherein sections of the inner region and sections of the at least one outer region, each comprising semiconductor materials, are oriented parallel to one another substantially in a direction of their longer main axis.

3. The device according to claim 2, wherein at least one outer reaion p-doped region (P-resurf) arranged between the at least one first outer reaion n-doped region (D-N+) and the at least one P-well (PWELL) is provided.

4. The device according to claim 2, wherein at least one highly doped outer reaion p-type region (H-P+) arranged in the at least one P-well (PWELL) is arranged below the at least one second outer reaion p-doped region (B-P+).

5. The device according to claim 2, wherein the at least one first outer reaion n-doped region (D-N+) and/or the at least one first outer reaion p-doped region (A-P+) is/are arranged in a second N-well (NWELL) that is arranged in a first N-well (HV-NWELL).

6. The device according to claim 2, wherein the inner region is arranged between two outer regions.

7. The device according to claim 1, wherein the inner region comprises: at least one first inner region n-doped region (D-N+) having connected thereto at least one inner reaion drain terminal (D); at least one first inner reaion p-doped region (A-P+) arranged next to the at least one first inner region n-doped region (D-N+) and having connected thereto the at least one anode terminal (terminal A); at least one first N-well (HV-NWELL) having arranged therein the at least one first inner region n-doped region (D-N+) and the at least one first inner region p-doped region (A-P+); at least one second inner reaion n-doped region (S-N+) arranged in spaced relationship with the at least one first inner reaion n-doped region (D-N+) and the at least one first inner region p-doped region (A-P+), the at least one second inner region n-doped region (S-N+) having connected thereto a source (S); at least one second inner reaion p-doped region (B-P+) arranged next to the at least one second inner reaion n-doped region (S-N+) and having connected thereto a bulk terminal (B); at least one P-well (PWELL) having arranged therein the at least one second inner reaion n-doped region (S-N+) and the at least one second inner reaion p-doped region (B-P+); and at least one inner region isolation region (I) arranged between the at least one first inner reaion n-doped region (D-N+) and the at least one first inner reaion p-doped region (A-P+) on one side and the at least one second inner reaion n-doped region (S-N+) on an opposite side, an inner region gate terminal (G) is arranged above the at least one inner region isolation region (I); wherein the thyristor in the inner region (1) is configured by the at least one first inner region p-doped region, the at least one first N-well (HV-NWELL), the at least one P-well (PWELL) and the at least one second inner region n-doped region (S-N+).

8. The device according to claim 7, comprising an MOS transistor and an integrated semiconductor protection device, a resistor being connected between a gate and a source of the MOS transistor.

9. The device according to claim 1, wherein the at least one outer region further comprises: a second outer region n-doped region (S-N+) arranged in spaced relationship with the at least one first outer reaion n-doped region (D-N+) and/or the at least one first outer reaion p-doped region (A-P+) and adapted to have connected thereto a source (S); at least one first outer region n-doped region (D-N+) adapted to have connected thereto a drain (D), and/or at least one outer region isolation region (I) arranged between the at least one first outer reaion n-doped region (D-N+) and/or the at least one first outer reaion p-doped region (A-P+) and the at least one second outer reaion n-doped region (S-N+) and used for receiving thereon a gate (G); wherein the at least one first outer region p-doped region (A-P+) is arranged next to the at least one first outer reaion n-doped region (D-N+).

10. The device according to claim 1, wherein at least one section of the at least one outer region is configured as a common section with a corresponding section of the inner region.

11. The device according to claim 1, wherein the device comprises two respective source regions (S) and two respective second n-doped regions (S-N+).

12. The device according to claim 1, wherein the at least one first outer reaion n-doped region (D-N+) is configured as a region with a floating potential.

13. The device according to claim 1, wherein a width (W2a, W2b) of the at least one outer region is greater than a width (W1) of the at least one inner region.

14. The device according to claim 1, comprising an MOS transistor and an integrated semiconductor protection device.

15. The device according to claim 14, wherein the MOS transistor is configured as a depletion field effect transistor.

16. The device according to claim 14, wherein the MOS transistor has a gate connection, a source connection, a drain connection, and a bulk connection, and the drain connection is short-circuited with the at least one anode terminal.

17. The device according to claim 1, wherein the at least one PNP transistor triggers in the corner regions prior to the thyristor in the inner region (1) when an ESD pulse occurs, and acts as a first ESD protection stage having a high holding voltage, the high holding voltage being higher than half of a trigger voltage.

18. The device according to claim 1, wherein ignition of the thyristor in the inner region, and thus a thyristor-typical low holding voltage, will only take place at higher currents, these higher currents being currents of at least 200 mA.

Description

(1) The embodiments of the present invention are described on the basis of examples and they are not described in a way allowing limitations to be transferred from the figures into the claims or to be read into the claims. Like reference numerals in the figures stand for like elements.

(2) FIG. 1 is an integrated HV-NLDMOS transistor according to the prior art;

(3) FIG. 2 shows an integrated HV-NMOS transistor according to the prior art;

(4) FIG. 3 is an equivalent circuit diagram of the HV-NLDMOS transistor of FIG. 1;

(5) FIG. 4 is an integrated HV-ESD protection device configured as a silicon controlled rectifier or thyristor (aka SCR) for integrated high-voltage MOS transistors in CMOS circuits according to the prior art;

(6) FIG. 5 is an equivalent circuit diagram of the protection device of FIG. 4.

(7) FIG. 6 is an LDMOS transistor with integrated thyristor according to the prior art;

(8) FIG. 7 is an equivalent circuit diagram of the device of FIG. 6.

(9) FIG. 8 is a device according to a first embodiment of the present invention;

(10) FIG. 9 is a section through an outer region of the device of the first embodiment according to FIG. 8;

(11) FIG. 10 is an equivalent circuit diagram of a device according to FIG. 8;

(12) FIG. 11 is a schematic representation of the quasi-static high current characteristic curves of the device of the first embodiment of the present invention according to FIG. 8 in comparison with the device according to FIG. 6;

(13) FIG. 12 is an equivalent circuit diagram of the device of the first embodiment according to FIG. 8 with an external resistor R for dynamic triggering;

(14) FIG. 13 is a section through an inner region of the device of a second embodiment of the present invention with an additional P-resurf region;

(15) FIG. 14 is a section through an outer region of the device of the second embodiment of the present invention with an additional P-resurf region;

(16) FIG. 15 shows a section through an inner region of the device of a third embodiment of the present invention with an additional doping of a P-well in the bulk region;

(17) FIG. 16 shows a section through an outer region of the device of the third embodiment of the present invention with an additional doping of a P-well in the bulk area;

(18) FIG. 17 shows a section through the inner region of the device of a fourth embodiment of the present invention, with a P-well of the bulk region being located in the p-type substrate;

(19) FIG. 18 shows a section through the outer region of the device of the fourth embodiment of the present invention, with a P-well of the bulk region being located in the p-type substrate.

(20) FIG. 19 shows a section through the inner region of the device of a fifth embodiment of the present invention, which is particularly suitable for use as an ESD protection device;

(21) FIG. 20 shows a section through the outer region of the device of the fifth embodiment of the present invention;

(22) FIG. 21 is an equivalent circuit diagram of the device of the fifth embodiment of the present invention according to FIG. 19 and FIG. 20;

(23) FIG. 22 is an equivalent circuit diagram of the device of the fifth embodiment of the present invention according to FIG. 19 and FIG. 20 with an external resistor;

(24) FIG. 23 shows a section through the inner region of the device of a sixth embodiment of the present invention with an additional doping of a P-well in the bulk region;

(25) FIG. 24 shows a section through the outer region of the device of the sixth embodiment of the present invention with an additional doping of a P-well in the bulk region;

(26) FIG. 25 shows a section through the inner region of the device of a seventh embodiment of the present invention with a second N-well in the drain extension region;

(27) FIG. 26 shows a section through the outer region of the device of the seventh embodiment of the present invention.

(28) A first embodiment of the device according to the present invention, which can be used both as a transistor with an integrated ESD protection device and as an ESD protection device alone, will be explained in more detail with reference to FIG. 8 and FIG. 9.

(29) In the case of this embodiment, the device consists of an inner region 1 and two outer regions 2a, 2b, which are realized by corner regions. The drain region D-N+ of the transistor is preferably arranged inside, when seen in the radial direction of the device, while the source region S-N+ is preferably arranged further out. The layout of the outer regions 2a, 2b is shown in FIG. 8 in simplified form. In the real MOS device, either 45° corners or round corner terminations (a so-called racetrack layout) are preferably used for reasons of dielectric strength.

(30) For the same reasons, the outer radius of the drain region D-N+ preferably has a certain minimum size in the corner regions 2a, 2b. Even larger drain radii occur preferably in cases where the drain region D-N+ has a bond pad integrated therein—a variant which is commonly used in UHV devices and which preferably dispenses with the use of a metal and via plane for the ultra-high voltage, in order to prevent, on the one hand, a possible reduction of the breakdown voltage due to the field plate effect of this UHV metal plane and save, on the other hand, the two mask planes required for this.

(31) The structural design in the inner region 1 (cross-section along plane A′-A′ in FIG. 8) corresponds in principle to the SCR-LDMOS in FIG. 6, i.e. it preferably comprises an Ndiff drain connection region D-N+, also referred to as first n-doped region, and a Pdiff region A-P+, also referred to as first p-doped region, which acts as anode A of a thyristor, a drain extension region HV-NWELL, also referred to as first N well, a bulk region PWELL, also referred to as P well and, within the drain extension region HV-NWELL, an Ndiff source region S-N+, also referred to as second n-doped region, and a Pdiff bulk junction region B-P+, also referred to as second p-doped region, within the bulk region PWELL. The source S and the bulk B are preferably short-circuited with each other and will therefore be referred to in the following as source S for short. The drain extension region HV-NWELL is preferably located within a P substrate.

(32) The structural design in the outer region, in particular the corner regions 2a, 2b of the device, which are corner regions in the present embodiment (cross sections along the plane B′-B′ and C′-C′ of FIG. 8), cf. cross-section of FIG. 9, is preferably modified in comparison with the structural design in the inner region 1 insofar as the Ndiff source region S-N+ is missing there or is replaced by a Pdiff bulk connection region B-P+. Thus, a thyristor (SCR) is preferably only formed in the inner region 1 of the device of FIG. 8, while a PNP transistor is formed in the corner regions 2a, 2b, cf. FIG. 9, the PNP transistor comprising the Pdiff anode region A-P+ in the drain extension area HV-NWELL as an emitter, the drain extension region HV-NWELL as a base and the bulk region B-P+ as a collector.

(33) Accordingly, the ESB of FIG. 10 of the device of FIG. 8 shows, in comparison with the ESB (equivalent circuit diagram) of FIG. 7, an additional PNP transistor integrated in the device. On the one hand, this modification prevents the formation of a parasitic NPN transistor or a thyristor (SCR) in the corner regions 2a, 2b, which, due to premature triggering in this area, could otherwise lead to a high current density and the resultant thermal damage. On the other hand, the PNP transistor triggers in the corner regions 2a, 2b prior to the thyristor (SCR) in the inner region 1 and thus acts as a first ESD protection stage having a high holding voltage V.sub.H.sup.(1) due to the low snapback typical of PNP transistors. Numerical values of the holding voltage level are higher than half the trigger voltage, in particular the (first) snapback voltage of a PNP transistor.

(34) This high holding voltage V.sub.H.sup.(1) is shown as a quasi-static high current characteristic curve of the device in FIG. 11.

(35) If the gate G of the device is short-circuited (V.sub.GS=0) with the source S and the bulk B, the protective effect or protection of the device in the case of an ESD pulse functions (or works) as follows: When a pn breakdown voltage between the drain extension region HV-NWELL and the bulk region PWELL has been exceeded (a breakdown typically occurs in the corner regions), this will preferably lead to an electron current being excited at the drain D in the drain extension region HV-NWELL, which electron current further preferably causes a voltage drop below the Pdiff anode region A-P+, shown as R.sub.HVNW in FIG. 10. This preferably causes a voltage difference between the PNP emitter and the PNP base, which switches on the PNP transistor. The collector current of the PNP transistor in the outer regions 2a, 2b preferably does not contribute to triggering of the NPN transistor in the inner region 1. Even after the NPN transistor in the inner region 1 has been switched on, with a large PNP collector current component in the corner regions 2a, 2b the charge carrier concentration required for conductivity modulation in the inner region 1 and thus the ignition of the thyristor (SCR) in the inner region 1 and the thyristor-typical low holding voltage V.sub.H.sup.(2) will preferably only be reached at higher currents, shown as I.sub.T.sup.(2) in FIG. 11. These high currents are currents of at least 200 mA, preferably 300 mA or more than 400 mA. This will preferably reduce the risk that the thyristor may be triggered by interference pulses and that a latch-up may result from this, because much higher currents are necessary to reach the critical state with a low holding voltage. However, such high currents will normally not be reached by interference pulses.

(36) Since the thyristor is not triggered if interference pulses occur, dynamic triggering can be used (as triggering by capacitive gate coupling at gate G of the SCR-LDMOS and/or by the dV/dt displacement current generated by the steep rising edge of the ESD pulse). Under ESD conditions, i.e. when an interference pulse occurs, a preferably transient trigger voltage of the PNP transistor in the outer regions 2a, 2b can thus be accomplished, this trigger voltage being below the static breakdown voltage of the thyristor in the inner region 1. In addition to the PNP transistor especially in the corner regions, the PNP transistor is also active in the inner region (emitter, base and collector in the inner region and in the corner regions are not separated from one another). Instead of an ESD pulse, also an interference pulse (which occurs in the same time range) will be processed in this way.

(37) This will be advantageous especially in cases where an ESD design window is small. The device can therefore preferably be used both as an HV-MOS transistor with an integrated ESD protection device and as a mere ESD protection device.

(38) An ESB of the ESD protection device is shown in FIG. 12. For dynamic triggering, capacitive gate coupling by means of a resistor R (preferably in the 10 kΩ range) is here used in cooperation with the (parasitically acting) gate-drain capacitance C.sub.GD already comprised in the MOS transistor. Through an ESD interference pulse at the drain D, which generally has a steep edge, the voltage at the gate G is raised via the gate-drain capacitance C.sub.GD and the MOS transistor switches on. The current resulting therefrom at drain D causes, in turn, a voltage drop in the drain extension region HV-NWELL below the Pdiff anode region A-P+ and creates a potential difference between the emitter and the base of the PNP transistor. This potential difference causes the PNP transistor to be switched on. The trigger voltage can here preferably be set (be variable) through the magnitude of the resistance R between drain D and source S, but it also depends on the steepness of the edge of the ESD interference pulse.

(39) A second version of the device is configured as a double resurf device according to FIGS. 13 and 14 (double resurf is a known principle for accomplishing a high breakdown voltage in combination with the lowest possible switch-on resistance for LDMOS and HVMOS transistors). The P-resurf region in the corner regions 2a, 2b is connected to the bulk region PWELL over a large area (in particular over the entire width), as can be seen in FIG. 14. The P-resurf region thus acts as the collector of the PNP transistor in the corner regions 2a, 2b. This is advantageous for the intended mode of operation of the device.

(40) All the embodiments of the device described hereinafter apply analogously also to the double-resurf device of the second embodiment according to the present invention, which is shown in FIGS. 13 and 14.

(41) In a third embodiment of the device according to the present invention, shown in FIGS. 15 and 16, the doping of the bulk region PWELL preferably below the Ndiff source connection region S-N+and Pdiff bulk connection region B-P+is increased by an additional boron implantation (in the range of 10.sup.13/cm.sup.2 to 10.sup.14/cm.sup.2). This embodiment will be advantageous in cases where the doping of the PWELL bulk region is so low that, due to the hole current generated by impact ionization at the blocked pn junction between the drain extension region HV-NWELL and the bulk region PWELL in the bulk region, the voltage drop across the PWELL resistor R.sub.pw, which is shown in FIG. 10, to bulk B will become so large that the parasitic NPN transistor in the inner region 1 will switch on prior to the PNP transistor in the corner regions 2a, 2b.

(42) As a result, on the one hand, there is a risk that damage may be caused to the device before the PNP transistor switches on at least in the corner regions 2a, 2b or the thyristor (SCR) switches on in the inner region, and, on the other hand, the intended mode of operation, viz. that at first only the PNP transistor switches on, in particular in the corner regions, will be prevented. The high p-type doping below the connection regions of the source S and the bulk B is preferably produced in the entire P-well PWELL by generating a suitable retrograde well profile, which may drop in particular towards the surface. Further preferably, the high p-type doping is produced via an additional mask level only in the connection regions of the source S and the bulk B and at a distance from the channel region of the MOS transistor in order to prevent an influence on the MOS transistor characteristics, in particular the threshold voltage. With a suitably high p-type doping below the connection regions of the source S and the bulk B, the triggering of the parasitic NPN transistor in the inner area 1 will be delayed. This allows the PNP transistor to switch on first (in the corner regions 2a, 2b) and the trigger current of the thyristor (SCR) to increase, both of which are of advantage for the mode of operation.

(43) In the at least one P-well PWELL a doped region H-P+ is arranged, which is disposed below the at least one second p-doped region B-P+, this in section C′-C′. However, the doping concentration is lower than in the Pdiff region, where it is about 10.sup.15/cm.sup.2.

(44) In a fourth embodiment of the device according to the present invention, cf. FIG. 17 and FIG. 18, the bulk region PWELL is located in and/or on a p-type substrate.

(45) In a fifth embodiment of the device according to the present invention, the drain extension region HV-NWELL, i.e. the base of the PNP transistor, is configured preferably in the corner regions 2a, 2b with a floating potential, i.e. floating or n.c., as shown in FIGS. 19 and 20.

(46) The corresponding ESB is shown in FIG. 21.

(47) This variant is particularly suitable for use as an ESD protection device. The PNP transistor switches on more easily with a floating base than with a base that is shorted to the emitter. Triggering is effected, as described above, by pn breakdown or by a displacement current at the junction from the bulk region PWELL to the drain extension region HV-NWELL or by switching on the gate G, e.g. by means of capacitive gate coupling. This reduces the trigger voltage and the trigger current of the PNP transistor in the corner regions 2a, 2b, and this is advantageous for applications as ESD protection device, in particular for dynamic triggering. An example of an ESB as an ESD protection device with capacitive gate coupling is shown in FIG. 22.

(48) In a sixth embodiment of the device according to the present invention, which is shown in FIG. 23 and FIG. 24, an additional high-dose boron implant is introduced below the Ndiff source region S-N+ and the Pdiff bulk connection region B-P+ according to the third embodiment. This embodiment allows a particularly high increase in the trigger current I.sub.T.sup.(2) of the thyristor (SCR), which is shown in FIG. 11, the reduced trigger voltage of the PNP transistor being, however, maintained.

(49) In a seventh embodiment of the device, which is shown in FIG. 25 and FIG. 26, the Pdiff anode region A-P+ and the Ndiff drain diffusion region D-N+ are surrounded by an NWELL-region NWELL. This variant is advantageous for preventing a “punchthrough” (breakdown) between the Pdiff anode region A-P+ and the p-type substrate in the case of a low doped drain extension region HV-NWELL.

(50) In an eighth embodiment of the device, the Pdiff anode region and the Ndiff drain diffusion region are additionally surrounded by an NWELL-region in a device corresponding to the sixth embodiment.

(51) In a further embodiment, which is here not shown in the figures, the bulk region PWELL is located in the p-type substrate in a device corresponding to the third embodiment, as shown in the fourth example.

(52) In the case of even more variants of embodiments, the respective bulk region PWELL is located in the p-type substrate in the devices corresponding to the fifth to eighth embodiments according to these variants.

(53) Further variants of embodiments, which are here not shown in the figures, are ESD protection devices according to FIGS. 8 to 18, which are derived in the same way from depletion NLDMOS transistors. In addition, advantageous combinations of the features of the embodiments shown are possible.

(54) In summary, the trigger current of the thyristor (SCR) comprised in the described ESD semiconductor protection device can be set according to the respective embodiment in the following way: (1) Ratio of the width of the PNP transistor to the thyristor. Because of the higher ESD resistance per width of the thyristor compared with the PNP transistor, the thyristor can have a significantly smaller width than the PNP transistor. (2) Drain extension region HV-NWELL (PNP base) floating or connected to p-doped anode A. (3) Higher doping of the P-well PWELL or additional p-doping below Ndiff source S-N+− and Pdiff bulk connection region B-P+.
Between (3) and (5) point (4) is missing (5) Pdiff anode A-P+ surrounded or not surrounded by N-well NWELL. (6) Length of the Pdiff anode A-P+ in the inner region 1 of the device and/or (7) Exchange of Ndiff drain connection region D-N+ and Pdiff anode region A-P+ in the inner region 1 of the device.

(55) One respective measure alone or two or more measures in combination constitute the adjustability.

LIST OF REFERENCE NUMERALS (EXTRACT)

(56) 1 inner region 2a, 2b outer region (or corner region) W.sub.1 width of the inner region W.sub.2a, W.sub.2b width of the outer region (or corner region), variable A′-A′ section in the inner region B′-B′, C′-C′ sections in the outer region (or corner region) D drain A anode G gate S source B bulk N+ n-doped region, Ndiff region P+ p-doped region, Pdiff region D-N+ n-doped region at drain, Ndiff drain connection region A-P+ p-doped region at anode, Pdiff anode region S-N+ n-doped region at source, Ndiff source region B-P+ p-doped region at bulk, Pdiff bulk connection region isolation region HV-NWELL first N-well, drain extension region PWELL P-well, bulk region NWELL second N-well P-resurf p-doped region R.sub.PW ohmic resistance of the P-well R.sub.HVNW ohmic resistance of the N-well R ohmic resistance C.sub.GD gate-drain capacitance V.sub.H holding voltage of an SCR-LDMOS V.sub.H.sup.(1) holding voltage of the PNP transistor in a device according to an embodiment of the present invention V.sub.H.sup.(2) SCR holding voltage in a device according to an embodiment VT trigger current of an SCR-LDMOS V.sub.T.sup.(1) trigger current of the PNP transistor in a device according to an embodiment of the present invention V.sub.T.sup.(2) SCR trigger current in a device according to an embodiment I.sub.T trigger current of an SCR LDMOS I.sub.T.sup.(1) trigger current of the PNP transistor in a device according to an embodiment of the present invention I.sub.T.sup.(2) SCR trigger current in a device according to an embodiment