Common-mode feedback

Abstract

A common-mode feedback circuit for a fully differential amplifier comprises first (M.sub.B), second (M.sub.TP), and third (M.sub.TN) transistors, each having a respective drain, source, gate, and back-gate terminals. The drain terminal of the first transistor (M.sub.B) and the gate terminals of the first, second, and third transistors (M.sub.B, M.sub.TP, M.sub.TN) are connected together at a bias current terminal. The drain terminals of the second and third transistors are connected together at a tail current terminal. The source terminals of the first, second, and third transistors are connected together. The back-gate terminal of the first transistor (M.sub.B) is arranged to receive a common-mode reference voltage input (V.sub.CM), the back-gate terminal of the second transistor (M.sub.TP) is arranged to receive a positive output voltage (V.sub.P) from the fully differential amplifier, and the back-gate terminal of the third transistor (M.sub.TN) is arranged to receive a negative output voltage (V.sub.N) from the fully differential amplifier.

Claims

1. A common-mode feedback circuit for a fully differential amplifier, said common-mode feedback circuit comprising first, second, and third transistors, each having a respective drain terminal, source terminal, gate terminal, and back-gate terminal, wherein the common mode feedback circuit is arranged such that: the drain terminal of the first transistor and the gate terminals of the first, second, and third transistors are connected together at a bias current terminal; the drain terminals of the second and third transistors are connected together at a tail current terminal; and the source terminals of the first, second, and third transistors are connected together; wherein the back-gate terminal of the first transistor is arranged to receive a common-mode reference voltage input, the back-gate terminal of the second transistor is arranged to receive a positive output voltage from the fully differential amplifier, and the back-gate terminal of the third transistor is arranged to receive a negative output voltage from the fully differential amplifier.

2. The common-mode feedback circuit as claimed in claim 1, wherein the first, second, and third transistors comprise fully depleted semiconductor-on-insulator (FDSOI) transistors.

3. The common-mode feedback circuit as claimed in claim 1, wherein the first, second, and third transistors comprise n-type transistors.

4. The common-mode feedback circuit as claimed in claim 1, wherein the bias current terminal is connected to a bias current supply.

5. An electronic device comprising a fully differential amplifier and a common-mode feedback circuit, wherein the fully differential amplifier comprises: a positive input terminal and a negative input terminal arranged to receive a differential input voltage thereacross; a positive output terminal and a negative output terminal, wherein the fully differential amplifier is arranged to produce a differential output voltage across said output terminals, wherein said differential output voltage is at least partially dependent on said differential input voltage; and a supply current terminal arranged to receive a tail current for biasing the fully differential amplifier; wherein the common-mode feedback circuit comprises first, second, and third transistors, each having a respective drain terminal, source terminal, gate terminal, and back-gate terminal, wherein the common mode feedback circuit is arranged such that: the drain terminal of the first transistor and the gate terminals of the first, second, and third transistors are connected together at a bias current terminal; the drain terminals of the second and third transistors are connected together at a tail current terminal; and the source terminals of the first, second, and third transistors are connected together; wherein the back-gate terminal of the first transistor is arranged to receive a common-mode reference voltage input, the back-gate terminal of the second transistor is connected to the positive output voltage terminal, and the back-gate terminal of the third transistor is connected to the negative output voltage terminal.

6. The electronic device as claimed in claim 5, comprising a radio communication device.

7. The electronic device as claimed in claim 5, wherein the first, second, and third transistors comprise fully depleted semiconductor-on-insulator (FDSOI) transistors.

8. The electronic device as claimed in claim 5, wherein the first, second, and third transistors comprise n-type transistors.

9. The electronic device as claimed in claim 5, wherein the bias current terminal is connected to a bias current supply.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Certain embodiments of the present invention will now be described with reference to the accompanying drawings, in which:

(2) FIG. 1 is a block diagram of a fully differential amplifier with common-mode feedback;

(3) FIG. 2 is a schematic diagram of a prior art common-mode feedback circuit;

(4) FIG. 3 is a schematic diagram of a common-mode feedback circuit in accordance with an embodiment of the present invention; and

(5) FIG. 4 is a block diagram of a fully differential amplifier that uses the common-mode feedback circuit of FIG. 3.

DETAILED DESCRIPTION

(6) FIG. 1 is a block diagram of a prior art electronic device 100 that includes a fully differential amplifier 102 provided with a common-mode feedback circuit (CMFB) 104.

(7) The fully differential amplifier 102 has a positive input terminal and a negative input terminal and is arranged to receive a differential input voltage V.sub.IN across these input terminals. The amplifier has an associated differential-mode gain G.sub.DM, which is ideally high, and an associated common-mode gain G.sub.CM, which is ideally zero (or as low as possible).

(8) The differential input voltage V.sub.IN is amplified by the differential-mode gain G.sub.DM to produce a differential output voltage V.sub.OUT across the negative and positive output terminals of the fully differential amplifier 102.

(9) In general the differential output voltage V.sub.OUT_DM is equal to the difference between the positive input voltage V.sub.IN+ (i.e. the voltage at the positive input terminal) and the negative input voltage V.sub.IN (i.e. the voltage at the negative input terminal), multiplied by the differential-mode gain G.sub.DM, as per Equation 1 below:
V.sub.OUT_DM=G.sub.DM(V.sub.IN+V.sub.IN)(1)
Differential-mode output voltage of amplifier

(10) The common-mode gain G.sub.CM acts to amplify the average value of the input voltages, i.e. the common-mode component of the output voltage V.sub.OUT_CM is equal to the sum of the positive input voltage V.sub.IN+ and the negative input voltage V.sub.IN, divided by two, and multiplied by the common-mode gain G.sub.CM, as per Equation 2 below:

(11) $\begin{array}{cc}{V}_{\mathrm{OUT}\_\mathrm{CM}}=G_{\mathrm{CM}}\frac{\left(V_{\mathrm{IN}+}+V_{\mathrm{IN}-}\right)}{2}\mathrm{Common}-\mathrm{mode}\mathrm{output}\mathrm{voltage}\mathrm{of}\mathrm{amplifier}& \mathrm{Equation}2\end{array}$

(12) The CMFB 104 receives a bias current I.sub.Bias from an external current source (not shown). The CMFB 104 also receives a positive voltage V.sub.P and a negative voltage V.sub.N from the fully differential amplifier 102. In this particular example, these voltages are the positive and negative output voltages of the fully differential amplifier 102 themselves, however alternative arrangements in which the inputs to the CMFB 104 are instead be derived from the output of the fully differential amplifier 102 are envisaged.

(13) Depending on the common-mode voltage (which can be determined from the average of the positive voltage V.sub.P and the negative voltage V.sub.N) received from the fully differential amplifier 102 and how it compares to an externally supplied set point or reference voltage V.sub.CM, the CMFB 104 varies a tail current I.sub.Tail that is supplies the fully differential amplifier 102, where generally this tail current I.sub.Tail is supplied to transistors arranged in a differential pair configuration within the fully differential amplifier 102 in a manner well known in the art per se.

(14) A prior art arrangement used for the CMFB 104 can be seen in FIG. 2, which is a schematic diagram of the CMFB 104 used with the fully differential amplifier 102 of FIG. 1.

(15) As can be seen in FIG. 2, the CMFB 104 is constructed from five transistors: a bias transistor M.sub.B, common-mode reference transistor M.sub.C, tail transistor M.sub.T, positive input transistor M.sub.P, and negative input transistor M.sub.N. The bias transistor M.sub.B and the tail transistor M.sub.T are arranged to form a current mirror, such that the current that flows through the bias transistor M.sub.B is reflected through the tail transistor M.sub.T. This is achieved through having the bias transistor M.sub.B in a diode-connected configuration, where its gate and drain terminals are connected together. The gate terminal of the tail transistor M.sub.T is connected to the gate and drain terminals of the bias transistor M.sub.B. The drain terminal (and the gate terminal) of the bias transistor is connected to the external current source and the bias current I.sub.Bias passes through the bias transistor M.sub.B as if it were a diode.

(16) A common-mode reference voltage input V.sub.CM is applied to the gate terminal of the common-mode reference transistor M.sub.C. This externally supplied common-mode reference voltage input V.sub.CM acts as a set point, i.e. it is the value to which the common-mode voltage at the output of the fully differential amplifier 102 is driven towards. The magnitude of the current through the bias transistor M.sub.B depends on the reference voltage V.sub.CM applied to the gate terminal of the common-mode reference transistor M.sub.C. By controlling the conductance of the common-mode reference transistor M.sub.C, the total current flowing through the bias transistor M.sub.B, and thus through the tail transistor M.sub.T, can be controlledthough the current actually supplied by to the fully differential amplifier 102 is subject to further modulation by the common-mode feedback loop, as outlined below.

(17) The drain terminal of the tail transistor M.sub.T is connected to the fully differential amplifier 102 and acts to supply the tail current I.sub.Tail to the internal differential pair transistors within the fully differential amplifier 102. However, the tail current I.sub.Tail is not simply a copy of I.sub.Bias, but instead depends on the values of the output voltages V.sub.P and V.sub.N (i.e. the outputs of the fully differential amplifier 102) which are applied to the gate terminals of the positive input transistor M.sub.P and negative input transistor M.sub.N respectively.

(18) This arrangement results in the common-mode reference transistor M.sub.C, positive input transistor M.sub.P, and negative input transistor M.sub.N being biased in the triode region which causes these transistors to act like resistors. This results in a relatively low intrinsic gain of these devices. Additionally, due to the requirement for five transistors, the CMFB 104 of FIG. 2 typically consumes more power and requires more area on silicon than may otherwise be achieved using the arrangement of FIG. 3, as outlined below.

(19) FIG. 3 is a schematic diagram of a CMFB circuit 204 in accordance with an embodiment of the present invention, where the CMFB 204 can be used in place of the prior art CMFB 104 of FIGS. 1 and 2 to provide its benefits to the fully differential amplifier 102, where an example of such a device 300 is shown in FIG. 4.

(20) As can be seen in FIG. 3, the CMFB circuit 204 of the present invention includes only three transistors, rather than five. Specifically, the CMFB 204 comprises: a bias transistor M.sub.B, a positive tail transistor M.sub.TP, and a negative tail transistor M.sub.TN, where each of these transistors is an n-type FDSOI transistor, i.e. a four-terminal transistor.

(21) The CMFB 204 is arranged such the drain terminal of the bias transistor M.sub.B (the first transistor) and the gate terminals of all three transistors are connected together at a bias current terminal arranged to receive the bias current I.sub.Bias provided by an external current source (not shown) discussed previously.

(22) The drain terminals of the positive tail transistor M.sub.TP (the second transistor) and the negative tail transistor M.sub.TN (the third transistor) are connected together at a tail current terminal arranged to supply the tail current I.sub.Tail to the fully differential amplifier 102. The source terminals of all three transistors M.sub.B, M.sub.TP, M.sub.TN are directly connected together.

(23) In the embodiment of FIG. 3, the back-gate terminals of the transistors are used to provide the common-mode feedback loop. In particular, the back-gate terminal of the bias transistor M.sub.B is arranged to receive the common-mode reference voltage input V.sub.CM. The back-gate terminal of the positive tail transistor M.sub.TP is arranged to receive the positive output voltage V.sub.P from the fully differential amplifier 102, and the back-gate terminal of the negative tail transistor M.sub.TN is arranged to receive the negative output voltage V.sub.N from the fully differential amplifier 102.

(24) In effect, the arrangement of FIG. 3 consists only of the transistors used to form the current mirror, in which the previous tail transistor M.sub.T of FIG. 2 is split into two, i.e. its function is divided across the positive tail transistor M.sub.TP and the negative tail transistor M.sub.TN, where each of these tail transistors M.sub.TP, M.sub.TN forms a current mirror with the bias transistor M.sub.B. The back-gate terminals are then used to provide the common-mode feedback behaviour, rather than needing separate transistors as per the prior art arrangement of FIG. 2. Similarly, the role of the common-mode reference transistor M.sub.C in FIG. 2 is now performed by the bias transistor M.sub.B via its respective back-gate terminal.

(25) Depending on the values of V.sub.CM, V.sub.P, and V.sub.N, the respective threshold voltages of the bias transistor M.sub.B, the positive tail transistor M.sub.TP and the negative tail transistor M.sub.TN are varied in dependence of the common-mode component of the output voltage from the fully differential amplifier 102.

(26) Specifically, the CMFB 204 is arranged such that if the common-mode component of the voltage output of the differential amplifier 104 is approximately equal to the common-mode reference voltage V.sub.CM, i.e. if the average of V.sub.P and V.sub.N is approximately equal to V.sub.CM, the conductance of the two tail transistors M.sub.TP and M.sub.TN is maximised, and thus the tail current I.sub.Tail supplied to the fully differential amplifier 102 is maximised (i.e. the common-mode feedback loop is at its most conductive).

(27) However, if the average of V.sub.P and V.sub.N (i.e. the common-mode output of the amplifier 102) deviates from the common-mode reference voltage V.sub.CM, the threshold voltages of the two tail transistors M.sub.TP and M.sub.TN will increase due to the resulting back bias which reduces the conductance of these tail transistors M.sub.TP and M.sub.TN, thereby reducing the tail current I.sub.Tail supplied to the differential pair within the fully differential amplifier 102. This reduction in current leads to a reduction in the common-mode voltage.

(28) In this advantageous arrangement, the three FDSOI transistorsi.e. the bias transistor M.sub.B, the positive tail transistor M.sub.TP and the negative tail transistor M.sub.TNare biased in their respective pentode regions. This ensures a relatively high loop gain for a wide range of values of V.sub.CM, V.sub.P, and V.sub.N.

(29) Thus it will be appreciated that embodiments of the present invention provide an improved common-mode feedback circuit for use with a fully differential amplifier that makes use of the back-gate terminals of the transistors to provide the common-mode feedback behaviour. Such an arrangement may advantageously provide reductions in power consumption and/or silicon area requirements compared to conventional arrangements that do not make use of the back biasing ability afforded by newer technology nodes (e.g. FDSOI) as per embodiments of the present invention.

(30) While specific embodiments of the present invention have been described in detail, it will be appreciated by those skilled in the art that the embodiments described in detail are not limiting on the scope of the claimed invention.