Self-calibrating buffered-voltage DAC

Abstract

A self-calibrated buffered-voltage DAC includes a DAC configured to receive an input digital signal and output a first analog voltage signal, a buffer amplifier configured to receive the first voltage signal from the DAC and provide a buffered second analog voltage signal, a voltage to frequency converter configured to selectively receive the first and second voltage signals and provide first and second output signals at respective first and second frequencies, a counter configured to receive the output signals from the voltage to frequency converter and provide respective first and second digital output signals corresponding to the respective first and second frequencies, a comparator configured to receive the first and second digital output signals and provide a digital calibration offset, and a DAC error code module configured to receive a digital input code and the digital calibration offset and to provide an offset corrected input digital signal to the DAC.

Claims

1. A self-calibrating buffered-voltage DAC circuit comprising: a DAC configured to receive an input digital signal and output a first analog voltage signal; a buffer amplifier configured to receive the first analog voltage signal from the DAC and provide a buffered second analog voltage signal; a voltage to frequency converter configured to selectively receive the first analog voltage signal and the second analog voltage signal and provide first and second output signals at respective first and second frequencies; a counter configured to receive the first and second output signals from the voltage to frequency converter and provide respective first and second digital output signals corresponding to the respective first and second frequencies; a comparator configured to receive the first and second digital output signals and provide a digital calibration offset; and a DAC error code module configured to receive a digital input code and the digital calibration offset and to provide an offset corrected input digital signal to the DAC.

2. The self-calibrating buffered-voltage DAC circuit of claim 1, further comprising: a first switch switchably connecting an output of the DAC to an input of the voltage to frequency converter; and a second switch switchably connecting an output of the buffer amplifier to the input of the voltage to frequency converter.

3. The self-calibrating buffered-voltage DAC circuit of claim 2, further comprising a controller configured to provide first and second switching signals to control operation of the respective first and second switches.

4. The self-calibrating buffered-voltage DAC circuit of claim 3, wherein the controller is configured to: provide the first and second switching signals to open the first switch and close the second switch in a normal operation mode; and provide the first and second switching signals to sequentially open and close the first and second switches to sequentially provide the first and second voltage signals to the voltage to frequency converter in a calibration mode.

5. The self-calibrating buffered-voltage DAC circuit of claim 1, further comprising a clock signal generator configured to provide a clock signal at a clock signal frequency to the counter, the counter configured to provide the first and second digital output signals by dividing the clock signal frequency by the respective first and second frequencies.

6. The self-calibrating buffered-voltage DAC circuit of claim 5, further comprising a first frequency divider configured to divide the frequency of the clock signal to provide a divided clock signal to the counter.

7. The self-calibrating buffered-voltage DAC circuit of claim 5, further comprising a second frequency divider configured to divide the frequency of the first and second analog voltage signals and provide divided first and second output signals to the counter.

8. The self-calibrating buffered-voltage DAC circuit of claim 1, further comprising a memory module comprising first and second memory slots, the memory module configured to receive the first and second digital output signals and store the first and second digital output signals in the respective first and second memory slots.

9. The self-calibrating buffered-voltage DAC circuit of claim 8, wherein the comparator is configured to receive the first and second digital output signals from the respective first and second memory slots.

10. The self-calibrating buffered-voltage DAC circuit of claim 8, wherein the memory module comprises third and fourth switches configured to switchably connect the first and second digital output signals to the respective first and second memory slots.

11. The self-calibrating buffered-voltage DAC circuit of claim 1, wherein the comparator module is configured to calculate the digital calibration offset as a difference between the first and second digital output signals.

12. The self-calibrating buffered-voltage DAC circuit of claim 1, wherein the DAC error code module comprises a DAC error code logic module configured to: compare the digital calibration offset to a predetermined minimum offset; output the digital calibration offset to the DAC input summing module if the digital calibration offset is not less than the predetermined minimum offset; and output a zero value to DAC input summing module if the digital calibration offset is less than the predetermined minimum offset.

13. A method of calibrating a buffered-voltage DAC, the buffered-voltage DAC comprising a DAC configured to receive an input digital signal and provide a first analog voltage signal, and a buffer amplifier configured to receive the first analog voltage signal from the DAC and provide a buffered second analog voltage signal, the method comprising: providing the first analog voltage signal to a voltage to frequency converter; measuring a first frequency from a first output of the voltage to frequency converter; providing the buffered second analog voltage signal to the voltage to frequency converter; measuring a second frequency from a second output of the voltage to frequency converter; calculating a difference between the first and second frequencies; determining a digital calibration offset from the difference; combining the digital calibration offset with an input digital signal to provide an offset corrected input digital signal; and providing the offset corrected input digital signal to the DAC.

14. The method of claim 13, further comprising: connecting an output of the DAC to an input of the voltage to frequency converter with a first switch; and connecting an output of the buffer amplifier to the input of the voltage to frequency converter with a second switch.

15. The method of claim 14, further comprising: providing, by a controller, first and second switching signals to control operation of the respective first and second switches.

16. The method of claim 15, wherein the controller: provides the first and second switching signals to open the first switch and close the second switch in a normal operation mode; and provides the first and second switching signals to sequentially open and close the first and second switches to sequentially provide the first and second voltage signals to the voltage to frequency converter in a calibration mode.

17. The method of claim 13, further comprising: receiving, by a counter, the first and second output signals from the voltage to frequency converter; providing, by the counter, respective first and second digital output signals corresponding to the respective first and second frequencies; receiving, by a memory module comprising first and second memory slots, the first and second digital output signals and storing the first and second digital output signals in the respective first and second memory slots; and receiving, by a comparator, the first and second digital output signals and providing the digital calibration offset.

18. The method of claim 17, wherein the comparator receives the first and second digital output signals from the respective first and second memory slots.

19. The method of claim 17, wherein the memory module connects the first and second digital output signals to the respective first and second memory slots via respective third and fourth switches.

20. The method of claim 13, further comprising: comparing, by a logic module, the digital calibration offset to a predetermined minimum offset; outputting, by the logic module, the digital calibration offset to the DAC input summing module if the digital calibration offset is not less than the predetermined minimum offset; and outputting, by the logic module, a zero value to DAC input summing module if the digital calibration offset is less than the predetermined minimum offset.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) Embodiments will be described, by way of example only, with reference to the drawings, in which:

(2) FIG. 1 is a schematic diagram of an example buffered-voltage DAC;

(3) FIG. 2 is a schematic diagram of an example self-calibrated buffered voltage DAC;

(4) FIG. 3 is a schematic diagram of a further example self-calibrated buffered-voltage DAC;

(5) FIG. 4 is a schematic diagram of an example voltage to frequency circuit;

(6) FIG. 5 is an example plot of frequency as a function of input voltage for an example voltage to frequency converter circuit;

(7) FIG. 6 is an example plot of counter output as a function of input voltage; and

(8) FIG. 7 is an example flow diagram illustrating a method of calibrating a buffered-voltage DAC.

(9) It should be noted that the Figures are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of these Figures have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar feature in modified and different embodiments.

DETAILED DESCRIPTION OF EMBODIMENTS

(10) FIG. 1 illustrates an example buffered-voltage DAC 100. The buffered-voltage DAC 100 comprises a DAC 101 and an op-amp 102. The DAC 101, which may for example be an R-2R DAC, receives an input digital signal D.sub.in and outputs a first analog voltage signal V.sub.1. The op-amp 102 acts as a buffer amplifier, receiving the first voltage signal V.sub.1 from the DAC 101 at its non-inverting input and providing a buffered second analog voltage signal V.sub.2 at its output, with a gain between the input and output defined by a feedback resistance 103 connected between the inverting input and the output of the op-amp 102. The second analog voltage signal V.sub.2 may be used to pass a signal between two components of different impedances connected at the input of the DAC 101 and the output 107 of the buffered voltage DAC 100. In the embodiments described in this disclosure, a unity gain is used. In other embodiments, gain values other than unity may be selected.

(11) An input offset variation, represented here by voltage source 104 providing an offset voltage V.sub.os, is intrinsic to the op-amp 102 and, with a unity gain, leads to a voltage difference between the first and second analog voltage signals V.sub.1 and V.sub.2, i.e. V.sub.2=V.sub.1+V.sub.os. This voltage difference requires calibration to improve the accuracy of the buffered voltage DAC 100. A calibration may be applied to account for the offset voltage by adding a digital calibration signal to the input signal D.sub.in, but this requires an accurate measure of the voltage offset V.sub.os. To enable this, first and second switches 105, 106 are sequentially operated by respective switching signals PH1, PH2. Switching signals PH1 and PH2 may be provided externally via a computer/test bench or via a controller provided as part of a self-calibrated buffered voltage DAC circuit. The first switch 105 switchably connects the output of the DAC 101 to the output 107 of the buffered-voltage DAC 100, bypassing the op-amp 102. The second switch 106 switchably connects the output of the op-amp 102 to the output 107 of the buffered-voltage DAC 100. In a normal mode, the first switch 105 is open and the second switch 106 is closed. In a calibration mode, as described below, the switches 105, 106 are operated so that the voltage offset V.sub.os can be measured by measuring V.sub.1 and V.sub.2 separately and determining the difference. The difference is then used to provide a calibration offset D.sub.in that is applied to the input digital signal D.sub.in.

(12) FIG. 2 illustrates an example self-calibrating buffered voltage DAC 200 comprising the buffered-voltage DAC 100 as described above. The self-calibrating buffered voltage DAC 200 further comprises a voltage to frequency (V2F) converter 201, counter 202, comparator 203 and a DAC input summing module 204. The first and second voltage signals V.sub.1, V.sub.2 are measured by first converting to signals having respective frequencies f.sub.L1, f.sub.L2 by the V2F converter 201, measuring the frequencies with the counter 202 and determining a difference D.sub.in with the comparator 203, which is then combined with an input digital signal D.sub.in to provide an offset corrected input digital signal D.sub.inD.sub.in to the DAC 101.

(13) During a calibration mode, the voltage to frequency converter 201 receives the first voltage signal V.sub.1, providing a first output signal with a first frequency f.sub.L1 and receives the second voltage signal V.sub.2, providing a second output signal with a second frequency f.sub.L2. Operation of the first and second switches 105, 106 (FIG. 1) connects the first and second voltage signals to the V2F converter 201. The voltage to frequency converter 201 may comprise a voltage-controlled oscillator (VCO), for example in the form of a ring oscillator as described in more detail below with reference to FIG. 4.

(14) The counter 202 is configured to receive the first and second frequencies f.sub.L1, f.sub.L2 from the voltage to frequency converter 201 and provide respective first and second digital output signals D.sub.1 and D.sub.2 corresponding to the respective first and second frequencies f.sub.L1, f.sub.L2.

(15) The comparator 203 is configured to receive the first and second digital output signals D.sub.1, D.sub.2 and provide a digital calibration offset D.sub.in, which is determined by calculating D.sub.in=D.sub.1D.sub.2. The digital calibration offset D.sub.in corresponds to the offset error caused by the op-amp input offset variation V.sub.os.

(16) The DAC input summing module 204 is configured to receive the digital input code D.sub.in and the digital calibration offset D.sub.in. In certain embodiments, the digital input code D.sub.in may arise directly from connecting a physical component to the DAC input summing module 204 and in other embodiments it may be simulated by an external computer/test bench. The DAC input summing module 204 provides an offset corrected input signal D.sub.inD.sub.in to the buffered voltage DAC 100. This offset corrected input signal D.sub.inD.sub.in contains a correction for the op-amp input offset variation V.sub.os along with the desired input signal, such that the output 107 of the buffered-voltage DAC 100 in normal use has a correction for the offset voltage V.sub.os.

(17) FIG. 3 illustrates a more detailed example of a self-calibrating buffered voltage DAC 300. The self-calibrating buffered-voltage DAC 300 comprises the buffered-voltage DAC 100, V2F converter 201 and comparator 203 described above with reference to FIG. 2, together with other components that may feature in one or more embodiments. As described above in relation to FIG. 2, first and second voltage signals V.sub.1, V.sub.2 are measured by first converting to signals having respective frequencies f.sub.L1, f.sub.L2 by the V2F converter 201. These frequencies are measured by the counter 202 and a difference is determined by the comparator 203, the output from which is combined with an DAC input code D.sub.in by the DAC input summing module 204 to provide an offset corrected input to the buffered-voltage DAC 100.

(18) In this embodiment, the first and second frequencies f.sub.Lx are measured by the counter 202 counting pulses in the signals relative to a high frequency signal clock signal with a higher frequency f.sub.Hx., which is provided by a clock signal generator 301. The first and second frequencies f.sub.lx may for example be in the kHz region and the high frequency, or reference, clock signal provided by the clock signal generator 301 may be in the MHz region, corresponding to a three order of magnitude difference between the two frequencies. To provide a desired degree of accuracy in measuring the frequencies f.sub.Lx, the frequency f.sub.Hx of the clock signal may be greater than the frequencies f.sub.Lx multiplied by at least a range of the DAC 101. For example, a 12 bit DAC has a range of 2.sup.12=4,096 discrete steps. The frequency f.sub.Hx of the clock signal should therefore be at least 4,096f.sub.Lmax, where f.sub.Lmax is the maximum frequency resulting from an expected maximum offset voltage V.sub.os. With the frequencies f.sub.Lx for example between 10 and 100 kHz, the clock frequency f.sub.Hx may therefore be between around 50 MHz and 500 MHz. The counter 202 may provide a digital output signal having a range equal to or greater than that of the DAC 101. In particular embodiments, the range of the digital output signal provided by the counter 202 may be greater than the range of the DAC 101, for example by one bit or more, so that the counter 202 has a finer resolution than that of the DAC 101. If, for example, the DAC 101 has a 12 bit range, the counter may have a range of 13 bits or more.

(19) In some embodiments, the first and/or second frequencies f.sub.Lx may be scaled by a frequency divider before being provided to the counter 202. As shown in FIG. 3, a first frequency divider 302 divides the clock signal frequency by a factor M to provide the reference frequency f.sub.Hx, while a second frequency divider 303 divides the frequency of the output signal from the V2F converter 201 by N to provide the frequencies f.sub.Lx to the counter 202.

(20) The counter 202 counts the first and second frequencies f.sub.L1, f.sub.L2 by calculating D.sub.x=f.sub.h/f.sub.Lx to determine corresponding first and second digital output signals D.sub.1, D.sub.2. Because these signals are generated sequentially, the digital output signals may be stored in a memory module 304 prior to being provided to the comparator 203.

(21) The memory module 304 comprises first and second memory slots 307, 308 and third and fourth switches 305, 306. The third and fourth switches 305, 306 are configured to switchably connect the output of the counter 202 to the respective first and second memory slots 307, 308. The third and fourth switches 305,306 may be operated by respective switching signals PH1, PH2, which are the same switching signals used for operating the first and second switches 105, 106 connecting the buffered-voltage DAC to the V2F converter 201. Using the same switching signals PH1, PH2 means that, when the first switch 105 is closed, the third switch 305 is also closed and when the second switch 106 is closed, the fourth switch 306 is also closed. Synchronising action of the first and second switches 105, 106 with the third and fourth switches 305, 306 using switching signals PH1, PH2 allows access to the correct memory slot for the first and second digital output signals D.sub.1, D.sub.2. In a particular embodiment, the memory module 304 may be in the form of a flash erasable programmable read-only memory.

(22) The first and second switching signals PH1, PH2 may be provided by a controller 313, which is configured to control operation of the self-calibrated buffered-voltage DAC 300. The controller 313 may be provided as part of the same circuit 300 or may be a separate external component. In a normal operational mode, the controller 313 provides signals PH1, PH2 to close the second switch 106 and open the first switch 105 to enable the buffered-voltage DAC 100 to output a buffered output voltage signal V.sub.2. In a calibration mode, the controller 313 disables the DAC input code D.sub.in and operates the circuit 300 by sequentially closing switches 105, 106 and corresponding switches 305, 306 to determine the digital calibration offset D.sub.in. If the digital calibration offset D.sub.in is greater than a predetermined minimum, for example greater than a resolution of the DAC, the offset is provided to the DAC input summing module 204 to correct the offset in the buffered-voltage DAC 100.

(23) The first and second memory slots 307, 308 store the respective first and second digital output signals D.sub.1, D.sub.2 for later calculation. In a particular embodiment, the first digital output signal D.sub.1 is stored in the first memory slot 307 and the second digital output signal D.sub.2 is stored in the second memory slot 308.

(24) The comparator 203 comprises a comparator summing module 310 and a comparator logic module 309. The comparator summing module 310 is configured to receive the first and second digital output signals D.sub.x from the first and second memory slots 307, 308 once both digital output signals D.sub.1, D.sub.2 have been provided. The comparator logic module 309 provides a digital calibration offset D.sub.in. to the summing module 204 once the memory slots 307, 308 have both provided output values to the comparator summing module 310. The comparator logic module 309 may be implemented in various ways, for example using a successive approximation register. The comparator summing module 310 calculates a difference between the digital output signals D.sub.1, D.sub.2, i.e. D.sub.in=D.sub.1D.sub.2. The digital calibration offset D.sub.in corresponds to the error caused by the op-amp input offset variation V.sub.os. In a general aspect therefore, the comparator 203 receives the first and second digital output signals D.sub.1, D.sub.2 and provides a digital calibration offset D.sub.in to the summing module 311, the digital calibration offset D.sub.in being a difference between the first and second digital output signals D.sub.1 and D.sub.2.

(25) A DAC error code module 311 comprises the DAC input summing module 204 and a logic module 312. The logic module 312 receives the digital calibration offset D.sub.in and provides this to the DAC input summing module 204 depending on whether or not a calibration offset is required. The logic module 312 determines whether a calibration offset is required by comparing the magnitude of the digital calibration offset D.sub.in to a predetermined minimum offset value D.sub.min. The predetermined minimum offset value D.sub.min may be based on the specifications of the op-amp 102 or may be chosen to ensure that the error caused by the input offset falls within a desired range. If D.sub.in is greater than the minimum offset value D.sub.min then the logic module 312 sends the digital calibration offset D.sub.in to the DAC input summing module 204. If D.sub.in is less than the minimum accepted value D.sub.min, the logic module 311 provides a zero output to the DAC input summing module 204.

(26) The DAC input summing module 204 receives the digital input code D.sub.in and the calibration offset D.sub.in and to provides an offset corrected digital input signal D.sub.inD.sub.in to the DAC 101. The offset corrected input signal D.sub.inD.sub.in thereby contains a correction for the op-amp input offset variation V.sub.os.

(27) FIG. 4 illustrates an example voltage to frequency circuit 400 that may be provided as the V2F converter 201 in the embodiments described above. The voltage to frequency circuit 400 comprises a buffer 401, inverters 402a-c, 403a-c, a signal level indicator 404 and a set-reset flip-flop (SRFF) 405. The buffer 401 is configured to receive the output signal of the buffered voltage DAC 100, i.e. voltage signals V.sub.1, V.sub.2, when the circuit 300 is operating in calibration mode. The buffer 401 provides a means of impedance transformation from buffered voltage DAC 100 to the voltage to frequency circuit 201. The output signal from the buffer 401 is sent to the chain of inverters 402 a-c and 403a-c. Inverters 402 a-c form a ring oscillator 402. The feedback of the output of inverter 402c to the input of inverter 402a causes oscillations in output voltage from the ring oscillator 402 as a function of time. The ring oscillator provides an output signal with a frequency f.sub.Lx determined by

(28) $f_{\mathrm{Lx}}=\frac{1}{2t\left(V_x\right)n},$
where t(V.sub.x) is the voltage dependent gate delay for a single inverter and n is the number of inverters in the inverter chain 402a-c (in this case n=3).

(29) The output signal of the ring oscillator (with frequency f.sub.Lx) is inverted twice by inverters 403a and 403b before being provided to the OP input of the signal level indicator 404. Since this signal has been inverted twice it will have an identical phase to that of f.sub.Lx. The output signal of the ring oscillator (with frequency f.sub.Lx) is inverted three times by inverters 403a-c before being provided to the ON input of the signal level indicator 404. Since the signal has been inverted three times it will be exactly out of phase with respect to the signal with frequency f.sub.Lx. The signal level indicator is configured to receive signals OP and ON (as outlined above) at its input and measure the amplitude of the respective signals. When the signal OP reaches a pre-defined level a set signal is provided from the output of the signal level indicator 404 to the input of the SRFF module 405 via the set channel S. When signal ON reaches a pre-defined level a reset signal is sent from the output of the signal level indicator 404 to the input of the SRFF module 405 via the reset channel R.

(30) The SRFF module 405 is configured to receive set signal S at its set input and reset signal R at its reset input. The SRFF module 405 is triggered to a high state at Q by the set signal (S) and holds the high state until reset by a low signal at the reset input (R). Since there is exactly a phase difference between signals sent to OP and ON as described above, the set-reset flip-flop module 405 will remain in the high state for half a cycle of f.sub.Lx, and subsequently remain in the low state for half a cycle of f.sub.Lx, creating a square wave trace with the same frequency as the original signal f.sub.Lx. In other embodiments, other methods for converting a voltage to a frequency may be used.

(31) FIG. 5 illustrates an example plot of frequency f.sub.Lx as a function of input voltage V.sub.x for an example voltage to frequency converter circuit. This shows a consistent linear relationship between the input voltage V.sub.x from the buffered voltage DAC and the output frequency f.sub.Lx over a frequency range of between around 8 and 10 kHz. In a specific embodiment that uses the voltage to frequency converter 400 of FIG. 4 as part of the self-calibrating buffered-voltage DAC 300, the frequency range of the conversion may be altered by adding or removing inverters to the ring oscillator loop 402 (as long as the total number of inverters in the ring oscillator loop is odd) in accordance with

(32) $f_{Lx}=\frac{1}{2t\left(V_x\right)n}.$

(33) FIG. 6 illustrates an example plot of counter output

(34) $D_x=\frac{f_h}{f_{\mathrm{Lx}}}$
as a function of input voltage V.sub.x 107 for an example voltage to frequency converter circuit with f.sub.h=100 MHz. The gradient of the relationship is approximately 24 counts per 100 V, meaning that 1 count corresponds to a voltage V.sub.x of approximately 4 V.

(35) FIG. 7 is flow diagram illustrating an example method of operating the self-calibrated buffered-voltage DAC 300. The method may be carried out under control of the controller 313 as described above. In a first step 701, a mode of operation is determined. In a normal mode of operation, the switching signals PH1, PH2 are provided to close the second switch 106 and open the first switch 105 (step 702), thereby converting the input digital signal D.sub.in, together with any digital offset D.sub.in, to the DAC 101 and providing an output analog voltage signal V.sub.2 (step 703). In a calibration mode, the digital input signal D.sub.in is disabled and the switching signals PH1, PH2 are provided to close the first switch 105 and open the second switch 106 (step 704), causing the first analog voltage signal V.sub.1 to be converted to a first frequency f.sub.L1 and a first digital output value D.sub.1 counted and stored (step 705). The switching signals PH1, PH2 are then reversed (step 706), causing the second analog voltage signal V.sub.2 to be converted to a second frequency f.sub.L2 and a second digital output value D.sub.2 counted and stored (step 707). A difference between the first and second digital output values is then calculated (step 709). This difference is compared to a minimum threshold value (step 710) and, if the minimum threshold value is exceeded this is applied as an offset to the digital input signal D.sub.in (step 703), otherwise the offset correction is set to zero (step 711).

(36) The calibration mode may be performed in parallel with other modules operating alongside the DAC circuit and may be performed at regular intervals to maintain accuracy of the DAC, for example during variations in the offset voltage due to temperature variations. When the circuit is operating in normal mode, the components involved in calibration do not need to consume power. An advantage of the circuit as described herein is that the absolute accuracy of the op-amp can be reduced, thereby reducing the die area occupied by the op-amp, resulting in either a similar overall die area being taken up by the circuit or a reduced area overall.

(37) From reading the present disclosure, other variations and modifications will be apparent to the skilled person. Such variations and modifications may involve equivalent and other features which are already known in the art of digital to analog converters, and which may be used instead of, or in addition to, features already described herein.

(38) Although the appended claims are directed to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention.

(39) Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination. The applicant hereby gives notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

(40) For the sake of completeness it is also stated that the term comprising does not exclude other elements or steps, the term a or an does not exclude a plurality, a single processor or other unit may fulfil the functions of several means recited in the claims and reference signs in the claims shall not be construed as limiting the scope of the claims.