Probe card device

Abstract

A probe card device is provided, including a thin film substrate having opposite first and second surfaces; a plurality of probe pins disposed over the first substrate of the thin film substrate, wherein the probe pins are not deformable, and the probe pins and the thin film substrate are integrally formed; a ceramic substrate formed by a crystal growth method or glass substrate, having a first surface and a second surface opposite to each other which are electrically connected, the first surface of the ceramic substrate or the glass substrate is disposed on the second surface of the thin film substrate, and is electrically connected to the thin film substrate; and the second surface of the ceramic substrate or the glass substrate are electrically connected to the second surface for electrical connection to another circuit board.

Claims

1. A probe card device, comprising: a thin-film substrate having opposite first and second surfaces, wherein the thin-film substrate comprises a thin film body and a plurality of first connection points embedded in the thin film body; a plurality of probe pins disposed on the first surface of the thin film substrate, wherein one terminal of each of the probe pins is electrically connected to connection points embedded in the thin film body, and the other terminal of each of the probe pins is used to directly contact a chip contact of a chip for chip testing, wherein the probe pins are partially embedded in the thin film body, wherein the plurality of probe pins are not deformable, and the plurality of probe pins and the thin-film substrate are integrally formed; a ceramic substrate formed by crystal growth or glass substrate, having opposite first surface and second surfaces, wherein the ceramic substrate or the glass substrate comprises a plurality of vertical via holes filled with a conductive material, so that the first surface and the second surface of the ceramic substrate or the glass substrate are electrically connected, the first surface of the ceramic substrate or the glass substrate is disposed on the second surface of the thin film substrate and is electrically connected to the thin film substrate, wherein the ceramic substrate formed by crystal growth or glass substrate is processed by grinding and polishing, and then a dielectric layer is formed by spin coating or spray coating and baking and then the dielectric layer is attached to the ceramic substrate formed by crystal growth or glass substrate to form a completely sealed thin-film substrate with the probe pins; and a plurality of second connection points disposed on the second surface of the ceramic substrate or glass substrate to electrically connect to a circuit board.

2. The probe card device according to claim 1, wherein there is no gap between the first surface of the ceramic substrate or the glass substrate and the second surface of the thin film substrate.

3. The probe card device according to claim 1, wherein the ceramic substrate comprises aluminum oxide or aluminum nitride.

4. The probe card device according to claim 1, wherein the plurality of second connection points of the ceramic substrate or glass substrate are used to directly electrically connect to a testing machine, which generates and receives testing signals for the chip testing.

5. A probe card device, comprising: a thin-film substrate having opposite first and second surfaces, wherein the thin-film substrate comprises a thin film body and a plurality of connection points embedded in the thin film body; a plurality of probe pins disposed on the first surface of the thin film substrate, wherein one terminal of each of the probe pins is electrically connected to connection points embedded in the thin film body, and the other terminal of each of the probe pins is used to directly contact a chip contact of a chip for chip testing, wherein the probe pins are partially embedded in the thin film body, wherein the plurality of probe pins are not deformable, and the plurality of probe pins and the thin-film substrate are integrally formed; a ceramic substrate formed by crystal growth or glass substrate, having opposite first surface and second surfaces, wherein the ceramic substrate or the glass substrate comprises a plurality of vertical via holes filled with a conductive material, so that the first surface and the second surface of the ceramic substrate or the glass substrate are electrically connected, the first surface of the ceramic substrate or the glass substrate is disposed on the second surface of the thin film substrate and is electrically connected to the thin film substrate, wherein the ceramic substrate formed by crystal growth or glass substrate is processed by grinding and polishing, and then a dielectric layer is formed by spin coating or spray coating and baking and then the dielectric layer is attached to the ceramic substrate formed by crystal growth or glass substrate to form a completely sealed thin-film substrate with the probe pins; and another thin film substrate disposed on the second surface of the ceramic substrate or the glass substrate to electrically connect to a circuit board.

6. The probe card device according to claim 5, wherein there is no gap between the second surface of the ceramic substrate or the glass substrate and the another thin film substrate.

7. The probe card device according to claim 6, wherein horizontal stress of the thin film substrate and the another thin film substrate against the ceramic substrate or glass substrate is substantially the same to eliminate bending or deformation of the ceramic substrate or the glass substrate caused by unequal horizontal stress between the thin film substrate and the another thin film substrate.

8. The probe card device according to claim 5, wherein the ceramic substrate comprises aluminum oxide or aluminum nitride.

9. The probe card device according to claim 5, wherein the another thin film substrate is used to directly electrically connect to a testing machine, which generates and receives testing signals for chip testing.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) To detailly explain the technical schemes of the embodiments or existing techniques, drawings that are used to illustrate the embodiments or existing techniques are provided. Apparently, the illustrated embodiments are just a part of those of the present disclosure. It is easy for any person having ordinary skill in the art to obtain other drawings without labor for inventiveness.

(2) FIG. 1 is a schematic cross-section showing a probe card device according to a first embodiment of the present invention.

(3) FIG. 2 is a schematic cross-section showing a probe card device according to a second embodiment of the present invention.

(4) FIG. 3 is a schematic cross-section showing a ceramic substrate shown in FIGS. 1-2.

(5) FIG. 4 is a schematic cross-section showing a thin film substrate shown in FIGS. 1-2.

(6) FIG. 5 is a schematic cross-section showing an internal structure of the thin film substrate shown in FIG. 2.

(7) FIG. 6 is a schematic cross-section illustrating an example of chip testing according to an embodiment of the present invention.

(8) FIG. 7 is a schematic cross-section illustrating another example of chip testing according to an embodiment of the present invention.

DETAILED DESCRIPTION

(9) Probe card devices according to various embodiments of the present invention will be described below in conjunction with FIG. 1-5.

(10) Referring to FIG. 1, a cross-section of a probe card device 10 according to a first embodiment of the present invention is shown. The probe card device 10 comprises a thin film substrate 202, a ceramic substrate 204 formed by crystal growth, and a plurality of probe pins 2002. The thin film substrate 202 has an opposite first surface C (see FIG. 4) and a second surface D (see FIG. 4). A body of the ceramic substrate 204 comprises materials such as aluminum oxide (Al2O3) and has a first surface A (see FIG. 3) and a second surface B (see FIG. 3) opposite to each other. A plurality of vertical via holes 2042 and a conductive material 2044 partially filling the vertical via holes 2042 are formed in the ceramic substrate 204 so as to electrically connect the first surface A and the second surface B of the ceramic substrate 204. The first surface A of the ceramic substrate 204 is disposed on the second surface D of the thin film substate 202 to electrically connect the thin film substrate 202. The probe pins 2002 are disposed over a first surface C of the thin film substrate 202 with a predetermined pitch therebetween and partially embedded in the thin film substrate 202. The probe pins 2002 are not deformable and are integrally formed with thin film substate 202.

(11) Referring to FIG. 6, a plurality of electrical connection points 2046 are provided on the second surface B of the ceramic substrate 204 to electrically connect to a circuit board 3001. The circuit board 3001 is electrically connected to the ceramic substrate 204 and a testing machine 4001, and test signals generated by the testing machine 4001 is processed by the circuit board 3001, and then sent to inside of a chip 1001 through the connection points of the ceramic substrate 204, the film substrate 202, the probe pins 2002, chip connection point, and the chip 1001 that are electrically connected. The test signals are processed by the chip 1001 to generate output signals, and then enters the testing machine 4001 through the chip connection points, the probe pins 2002, the film substrate 202, the ceramic substrate 204, and the circuit board 3001. After the testing machine 4001 receives the test signals, a quality of the chip 1001 can be determined.

(12) Referring to FIG. 2, a schematic cross-section a probe card device 20 according to a second embodiment of the present invention is shown. The probe card device 20 comprises the thin film substrate 202, the plurality of probe pins 2002, the ceramic substrate 204 formed by crystal growth comprising aluminum oxide (Al2O3), and a thin film substrate 206. The structure and function of shown in FIG. 2 are the same as those in FIG. 1 in portions. In FIG. 2, the second surface B of the ceramic substrate 204 is electrically connected to the thin film substrate 206, and the thin film substrate 206 is electrically connected to another circuit board through a plurality of electrical connection points 2062. The function of the circuit board is the same as that of the circuit board 3001 in the first embodiment.

(13) Referring to FIG. 3, a schematic cross-section of the ceramic substrate 204 in the probe card device 10 and 20 in FIGS. 1 and 2 is shown, and a body 2040 thereof comprises materials such as aluminum oxide (Al.sub.2O.sub.3) or aluminum nitride (AlN). The vertical via holes 2042 can be filled with the conductive material 2044 such as copper, and the conductive material 2044 in the vertical via holes 2042 contact the electrical connection points of the film substrate 202 and the electrical connection points of the film substrate 206 respectively. The vertical via holes 2042 may be formed by methods such as laser drilling or etching.

(14) Referring to FIG. 4, the thin film substrate 202 shown in FIG. 1 and FIG. 2 is shown, comprising a thin film body 2032, a plurality of first connection points 2020 embedded in the thin film body 2032 and adjacent to the first surface C of the thin film substrate 202, a plurality of second connection points 2022 formed on the second surface D of the thin film body 2032, and at least one internal metal layer 2024 disposed inside the thin film body 2032. At least one of the first connection points 2020 is electrically connected to at least one of the second connection points 2022 through the at least one internal metal layer 2024, and a distance between two adjacent first connection points 2020 is less than a distance between two adjacent second connection points 2022. The thin film substrate 202 is used to electrically connect the probe pins 2002 with a narrow pitch to the ceramic substrate 204 with a wider pitch. The surfaces of the second connecting points 2022 comprise an electroless nickel electroless palladium and immersion Gold (ENEPIG), an electroless nickel immersion gold (ENIG), or an organic solderability preservative (OSP).

(15) One terminal of each of the probe pins 2002 is electrically connected to one of the first connecting points 2020, and the other terminal of each of the probe pins 2002 is electrically connected to a chip contact, which is a contact of a chip to be tested, as shown in FIGS. 6 and 7.

(16) Referring to FIG. 4, the thin film body 2032 comprises the first connection points 2020, the probe pins 2002, at least one internal metal layer 2024, and the second connection points 2022. The film body 2032 further comprises a first surface dielectric layer 2026, at least one internal dielectric layer 2028, and a second surface dielectric layer 2030. In this embodiment, the thin film substrate 202 comprises three internal metal layers 2024 and three internal dielectric layers 2028 but is not limited thereto.

(17) The first connecting points 2020 are embedded in the first surface dielectric layer 2026. The probe pins 2002 are also partially embedded in the first surface dielectric layer 2026 and surrounded by one of the first connecting points 2020. The internal metal layers 2024 are formed in the corresponding inner dielectric layers 2028, and the second connecting points 2022 are formed in the second surface dielectric layer 2030. The first connecting point 2020 and at least one of the probe pins 2002 are electrically connected to at least one of the second connecting points 2022 through at least one internal metal layer 2024.

(18) The thin film substrate 202 may comprise 4 layers to 20 layers. A thickness of each of the first surface dielectric layer 2026, the at least one inner dielectric layer 2028, and the second surface dielectric layer 2030 ranges from 5 m to 20 m. The first surface dielectric layer 2026, the at least one inner dielectric layer 2028, and the second surface dielectric layer 2030 may comprise organic dielectric materials such as polyimide. A height of each of the first connecting points 2020, a thickness of the at least one internal metal layer 2024, and a height of each of the second connecting points 2022 ranges from 1 m to 10 m. A line width of the at least one internal metal layer 2024 ranges from 2 m to 100 m. It is noted that the at least one internal metal layer 2024 may be a whole surface metal layer to be served as a power layer or a ground layer. A via size of the at least one internal metal layer 2024 is ranged from 3 m to 50 m.

(19) In the probe card devices 10 and 20 shown in FIGS. 1-2, the probe pins 2002 and the first connecting points 2020 can be formed by semiconductor processing. For example, after forming the first surface dielectric layer 2026, and after positions of the probe pins 2002 and the first connecting points 2020 are determined, a suitable opening is opened in the first surface dielectric layer 2026 by methods such as a laser opening or an organic dielectric layer etching to arrive a metal layer in which the first connecting point 2020 is located. A plurality of probe pins 2002 and a plurality of first connecting points 2020 are simultaneously formed in and over the first surface dielectric layer of the thin film substrate 202 by electroplating or a lithography process cooperating with a physical vapor deposition. The pitch between the probe pins 2002 can be appropriately adjusted by the control of the lithography process to reduce the pitch between the probe pins 2002 to within 30 micrometers, so that tens of thousands of probe pins 2002 can be simultaneously formed over the probe card device 10, thereby reducing the manufacturing cost of the probe card device 10.

(20) In short, due to the arrangement of the ceramic substrate 204, the flatness and support to the probe card devices 10 and 20 can be provided. Similarly, a well-fabricated glass substrate having similar functions of the ceramic substrate 204 can replace the ceramic substrate 204 in above embodiments. The compliance or buffering capability required for each probe pin 2002 to adapt to height differences of contacts of the wafer to be tested can be provided by the elasticity of the organic dielectric material located under the probe pins 2002 of the thin film substrate 202, so that the probe pins 2002 have the function of self-deforming ability of the conventional needles fixed to the needle housing. Thus, from a macroscopic point of view, the tens of thousands of probe pins 2002 disposed over the thin film substrate 202 can have a flatness equivalent to that of the ceramic substate or the glass substrate, and the individual probe pins 2002 also have the compliance or buffering capability of the contact height differences of a wafer to be tested from a microscopic point of view.

(21) Referring to FIG. 5, a structure of the thin film substrate 206 in the probe card device 20 of FIG. 2 is shown. The film substrate 206 comprises a thin film body 2072 having opposite first surfaces E and second surfaces F, the first connection points 2060, at least one internal metal layer 2064, and the second connection points 2062. The thin film body 2072 comprises a first surface dielectric layer 2066, at least one internal dielectric layer 2068, and a second surface dielectric layer 2070. In this embodiment, the thin film substrate 206 comprises three internal metal layers 2064 and three internal dielectric layers 2068 but is not limited thereto. The first connection points 2060 are electrically connected to the second surface of the ceramic substrate 204, and the second connection points 2062 are electrically connected to a circuit board, which has the same function as the first embodiment of the present invention.

(22) The first connecting points 2060 are embedded in the first surface dielectric layer 2066 and are exposed by the first surface E of the thin film substrate 206. The internal metal layers 2064 are formed in the corresponding inner dielectric layers 2068, and the second connecting points 2062 are formed in the second surface dielectric layer 2070 and are exposed by the second surface F of the thin film substrate 206. At least one of the first connecting points 2060 is electrically connected to at least one of the second connecting points 2062 through at least one internal metal layer 2064.

(23) The thin film substrate 206 may comprise 4 layers to 20 layers. A thickness of each of the first surface dielectric layer 2066, the at least one inner dielectric layer 2068, and the second surface dielectric layer 2070 ranges from 5 micrometers (m) to 20 m. The first surface dielectric layer 2066, the at least one inner dielectric layer 2068, and the second surface dielectric layer 2070 may comprise organic dielectric materials such as polyimide. A height of each of the first connecting points 2060, a thickness of the at least one internal metal layer 2064, and a height of each of the second connecting points 2062 ranges from 1 m to 10 m. A line width of the at least one internal metal layer 2064 ranges from 2 m to 100 m. It is noted that the at least one internal metal layer 2064 may be a whole surface metal layer to be served as a power layer or a ground layer. A via size of the at least one internal metal layer 2064 is ranged from 3 m to 50 m.

(24) Referring to FIG. 2, in another embodiment of the present invention, the thin film substrate 202 and the thin film substrate 206 have no gaps with the ceramic substrate 204, and the thin film substrate 202 and the thin film substrate 206 have substantially the same horizontal stress against the glass substrate so as to eliminate bending or deformation of the ceramic substrate or the glass substrate due to the unequal horizontal stress caused by the upper thin film substrate 202 and the lower thin film substrate 206.

(25) As mentioned above, the ceramic substrate or glass substrate after grinding and polishing can be used as a carrier plate, and a dielectric layer is formed by spin coating or spray coating and baking, and then the dielectric layer is attached to the carrier plate to form a completely sealed structure, and other structure or elements are the same as the description of the above-mentioned embodiment of FIG. 2. In order to make the horizontal stress of the thin film substrate 202 and the thin film substrate 206 substantially the same, the total film thickness of the dielectric layers in the thin film substrate 202 and the thin film substrate 206 are designed to be approximately the same, and the total film thickness of the metal layers in the thin film substrate 202 and the thin film substrate 206 are designed to be approximately the same.

(26) Referring to FIG. 1 and FIG. 2 and FIG. 7, in yet another embodiment of the present invention, the second connection points 2046 of the ceramic substrate or the connection points 2062 of the thin film substrate can be electrically connected to a testing machine 4001, and the testing machine 4001 generates and receives test signals for chip testing. It can be done by integrating the circuit board 3001 described in the above paragraph [0021] into the thin film substrate 202, or the circuit board described in the above paragraph [0022] into the thin film substrate 206.

(27) While the present disclosure has been described with the aforementioned preferred embodiments, it is preferable that the above embodiments should not be construed as limiting of the present disclosure. Anyone having ordinary skill in the art can make a variety of modifications and variations without departing from the spirit and scope of the present disclosure as defined by the following claims.