INTRA-SYMBOL VOLTAGE CHANGE ACCELERATION IN A WIRELESS TRANSMISSION CIRCUIT

Abstract

Intra-symbol voltage change acceleration in a wireless transmission circuit is disclosed. The wireless transmission circuit includes a power amplifier circuit that amplifies a radio frequency (RF) signal based on an average power tracking (APT) voltage supplied by a power management integrated circuit (PMIC). The RF signal is modulated in multiple modulation symbols, such as orthogonal frequency division multiplex (OFDM) symbols. To prevent distortion (e.g., amplitude clipping) in the RF signal, the PMIC is configured to increase the APT voltage during each of the modulation symbols whenever the RF signal exceeds a predefined power threshold. Further, the PMIC is configured according to various acceleration embodiments to complete each APT volage change within a defined temporal limit (e.g., <1 s). By supporting intra-symbol voltage change acceleration, the wireless transmission circuit can enable fast APT voltage adaptation to thereby improve operating efficiency of the power amplifier circuit.

Claims

1. A wireless transmission circuit comprising: a power amplifier circuit configured to amplify a radio frequency (RF) signal modulated in a plurality of modulation symbols based on an average power tracking (APT) voltage; a transceiver circuit configured to generate a target voltage in accordance with a time-variant power envelope of the RF signal; and a power management integrated circuit (PMIC) comprising: a voltage generation circuit configured to generate the APT voltage in each of the plurality of modulation symbols based on the target voltage; and a control circuit configured to: determine that the target voltage indicates one or more increased levels of the APT voltage relative to an average level of the APT voltage in a respective one of the plurality of modulation symbols; and control the voltage generation circuit to increase the APT voltage from the average level to each of the one or more increased levels within a defined temporal limit.

2. The wireless transmission circuit of claim 1, wherein the transceiver circuit is further configured to: compare the time-variant power envelope of the RF signal against a predefined power threshold; indicate the one or more increased levels of the APT voltage in the target voltage whenever the time-variant power envelope is higher than the predefined power threshold; and indicate the average level of the APT voltage in the target voltage whenever the time-variant power envelope is lower than or equal to the predefined power threshold.

3. The wireless transmission circuit of claim 2, wherein the transceiver circuit comprises: a digital baseband circuit configured to generate a digital signal associated with a time-variant amplitude envelope; a modulator circuit configured to convert the digital signal into the RF signal associated with the time-variant power envelope; an envelope detection circuit configured to compare the time-variant amplitude envelope against the predefined power threshold; a target voltage circuit configured to generate a digital target voltage to: indicate the one or more increased levels of the APT voltage whenever the time-variant power envelope is higher than the predefined power threshold; and indicate the average level of the APT voltage whenever the time-variant power envelope is lower than or equal to the predefined power threshold; and a digital-to-analog converter, DAC, configured to convert the digital target voltage into an analog target voltage.

4. The wireless transmission circuit of claim 3, wherein the transceiver circuit further comprises a digital predistortion (DPD) circuit coupled between the digital baseband circuit and the modulator circuit, the DPD circuit is configured to pre-distort the digital signal to thereby correct one or more of an amplitude-amplitude (AMAM) distortion and an amplitude-phase, AMPM, distortion in the RF signal.

5. The wireless transmission circuit of claim 3, wherein the transceiver circuit is further configured to generate the target voltage comprising the digital target voltage.

6. The wireless transmission circuit of claim 5, wherein, for each of the one or more increased levels of the APT voltage, the control circuit is further configured to: determine a sequence of voltage change segments each associated with a respective one of a sequence of voltage damping factors organized in an ascending order; and control the voltage generation circuit to increase the APT voltage from the average level to a respective one of the one or more increased levels in accordance with the sequence of voltage damping factors.

7. The wireless transmission circuit of claim 6, wherein the sequence of voltage change segments comprises: an over-damped segment associated with a smallest one of the sequence of voltage damping factors; a critical-damped segment with an intermediate one of the sequence of voltage damping factors; and an under-damped segment with a highest one of the sequence of voltage damping factors.

8. The wireless transmission circuit of claim 6, wherein the control circuit comprises: a timer configured to generate the sequence of voltage change segments; a lookup table (LUT), configured to store multiple loop coefficient values; an acceleration circuit configured to determine the sequence of voltage damping factors based on the multiple loop coefficient values stored in the LUT; and a voltage loop control configured to control the voltage generation circuit to increase the APT voltage from the average level to the respective one of the one or more increased levels in accordance with the sequence of voltage damping factors.

9. The wireless transmission circuit of claim 5, wherein, for each of the one or more increased levels of the APT voltage, the control circuit is further configured to: determine a sequence of voltage change segments each associated with a respective one of multiple voltage targets indicating a respective one of the one or more increased levels of the APT voltage, wherein an initial one of the multiple voltage targets is higher than the respective one of the one or more increased levels of the APT voltage in a respective one of the sequence of voltage change segments; and control the voltage generation circuit to increase the APT voltage from the average level to the respective one of the one or more increased levels in accordance with the multiple voltage targets.

10. The wireless transmission circuit of claim 3, wherein the transceiver circuit is further configured to generate the target voltage comprising the analog target voltage.

11. The wireless transmission circuit of claim 10, wherein, for each of the one or more increased levels of the APT voltage, the control circuit is further configured to: generate one or more acceleration currents from the analog target voltage; and inject the one or more acceleration currents into one or more selected injection points to thereby cause the voltage generation circuit to increase the APT voltage from the average level to a respective one of the one or more increased levels within the defined temporal limit.

12. The wireless transmission circuit of claim 11, wherein the control circuit comprises an acceleration circuit configured to generate the one or more acceleration currents based on the analog target voltage and inject the one or more acceleration currents into the one or more selected injection points.

13. The wireless transmission circuit of claim 12, wherein the one or more selected injection points comprise one or more of a voltage loop control, a current loop control, and an output of the voltage generation circuit.

14. A method for accelerating intra-symbol voltage change comprising: amplifying a radio frequency (RF) signal modulated in a plurality of modulation symbols based on an average power tracking (APT) voltage; generating a target voltage in accordance with a time-variant power envelope of the RF signal; generating the APT voltage in each of the plurality of modulation symbols based on the target voltage; determining that the target voltage indicates one or more increased levels of the APT voltage relative to an average level of the APT voltage in a respective one of the plurality of modulation symbols; and increasing the APT voltage from the average level to each of the one or more increased levels within a defined temporal limit.

15. The method of claim 14, further comprising: comparing the time-variant power envelope of the RF signal against a predefined power threshold; indicating the one or more increased levels of the APT voltage in the target voltage whenever the time-variant power envelope is higher than the predefined power threshold; and indicating the average level of the APT voltage in the target voltage whenever the time-variant power envelope is lower than or equal to the predefined power threshold.

16. The method of claim 14, wherein generating the target voltage comprises generating a digital target voltage.

17. The method of claim 16, further comprising, for each of the one or more increased levels of the APT voltage: determining a sequence of voltage change segments each associated with a respective one of a sequence of voltage damping factors organized in an ascending order; and increasing the APT voltage from the average level to a respective one of the one or more increased levels in accordance with the sequence of voltage damping factors.

18. The method of claim 16, further comprising, for each of the one or more increased levels of the APT voltage: determining a sequence of voltage change segments each associated with a respective one of multiple voltage targets indicating a respective one of the one or more increased levels of the APT voltage, wherein an initial one of the multiple voltage targets is higher than the respective one of the one or more increased levels of the APT voltage in a respective one of the sequence of voltage change segments; and increasing the APT voltage from the average level to the respective one of the one or more increased levels in accordance with the multiple voltage targets.

19. The method of claim 14, wherein generating the target voltage comprises generating an analog target voltage.

20. The method of claim 19, further comprising, for each of the one or more increased levels of the APT voltage: generating one or more acceleration currents from the analog target voltage; and injecting the one or more acceleration currents into one or more selected injection points to thereby increase the APT voltage from the average level to a respective one of the one or more increased levels within the defined temporal limit.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0013] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0014] FIG. 1 illustrates an exemplary time slot(s) as widely supported in a fifth generation (5G) or a 5G new-radio (5G-NR) system for modulating a radio frequency (RF) signal;

[0015] FIG. 2 is a schematic diagram of an exemplary wireless transmission circuit wherein a power management integrated circuit (PMIC) and a transceiver circuit can be configured according to various embodiments of the present disclosure to support intra-symbol voltage change acceleration;

[0016] FIG. 3 is a graphic diagram providing an exemplary illustration as to how the transceiver circuit in FIG. 1 can generate a target voltage to enable the PMIC to provide intra-symbol voltage change acceleration;

[0017] FIG. 4 is a graphic diagram providing an exemplary illustration of a multi-damping scheme that can be employed by the PMIC in FIG. 2 to support intra-symbol voltage change acceleration;

[0018] FIG. 5 is a schematic diagram of the PMIC in FIG. 2 configured according to one embodiment of the present disclosure to support intra-symbol voltage change acceleration based on the multi-damping scheme of FIG. 4;

[0019] FIG. 6 is a graphic diagram providing an exemplary illustration of a multi-target scheme that can be employed by the PMIC in FIG. 5 to support intra-symbol voltage change acceleration;

[0020] FIG. 7 is a graphic diagram illustrating the multi-injection scheme performed by the PMIC in FIG. 2 to support intra-symbol voltage change acceleration;

[0021] FIG. 8 is a schematic diagram of the PMIC in FIG. 2, which is configured according to another embodiment of the present disclosure to accelerate intra-symbol voltage change based on the multi-injection scheme in FIG. 7;

[0022] FIG. 9 is a schematic diagram of the transceiver circuit in FIG. 2 that can be configured according to an embodiment to generate the modulated target voltage in FIG. 3;

[0023] FIG. 10 is a schematic diagram of an exemplary user element wherein the wireless transmission circuits of FIG. 2 can be provided; and

[0024] FIG. 11 is a flowchart of an exemplary process that may be employed by the wireless transmission circuit of FIG. 2 for accelerating intra-symbol voltage change.

DETAILED DESCRIPTION

[0025] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0026] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items.

[0027] It will be understood that when an element such as a layer, region, or substrate is referred to as being on or extending onto another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly on or extending directly onto another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being over or extending over another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly over or extending directly over another element, there are no intervening elements present. It will also be understood that when an element is referred to as being connected or coupled to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being directly connected or directly coupled to another element, there are no intervening elements present.

[0028] Relative terms such as below or above or upper or lower or horizontal or vertical may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms a, an, and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes, and/or including when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0031] Embodiments of the disclosure relate to intra-symbol voltage change acceleration in a wireless transmission circuit. The wireless transmission circuit includes a power amplifier circuit that amplifies a radio frequency (RF) signal based on an average power tracking (APT) voltage supplied by a power management integrated circuit (PMIC). The RF signal is modulated in multiple modulation symbols, such as orthogonal frequency division multiplex (OFDM) symbols. To prevent distortion (e.g., amplitude clipping) in the RF signal, the PMIC is configured to increase the APT voltage during each of the modulation symbols whenever the RF signal exceeds a predefined power threshold.

[0032] Further, the PMIC is configured according to various acceleration embodiments to complete each APT volage change within a defined temporal limit (e.g., <1 s). By supporting intra-symbol voltage change acceleration, the wireless transmission circuit can enable fast APT voltage adaptation to thereby improve operating efficiency of the power amplifier circuit.

[0033] Before discussing intra-symbol voltage modulation according to the present disclosure, starting at FIG. 2, an overview of orthogonal frequency division multiplexing (OFDM) symbols, which can be used to define durations of voltage modulation intervals, is first provided with reference to FIG. 1.

[0034] FIG. 1 illustrates an exemplary time slot 10 as widely supported in a fifth generation (5G) and 5G new-generation (5G-NR) system for modulating an RF signal. The time slot(s) 10 is configured to include multiple OFDM symbols. In an exemplary configuration, the time slot 10 can include fourteen (14) OFDM symbols 12(1)-12(14).

[0035] As previously shown in Table 1, each of the symbols 12(1)-12(14) has a symbol duration that depends on the subcarrier spacing (SCS). In this regard, once the SCS is chosen, the duration and the CP of each of the symbols 12(1)-12 (14) are set accordingly. Hereinafter, each of the symbols 12(1)-12(14) is referred to generally as a modulation symbol.

[0036] Each of the symbols 12(1)-12(14) has a respective boundary, defined by a start time Ts and an end time T.sub.E, and includes a cyclic prefix (CP) and a coded bit(s). Herein, the term intra-symbol voltage change refers generally to changing a voltage one or more times within the respective boundary of any of the symbols 12(1)-12(14).

[0037] FIG. 2 is a schematic diagram of an exemplary wireless transmission circuit 14 wherein a PMIC 16 and a transceiver circuit 18 can be configured according to various embodiments of the present disclosure to support intra-symbol voltage change acceleration within the respective boundary of any of the OFDM symbols 12(1)-12(14) in FIG. 1. For the convenience of illustration, a pair of consecutive modulation symbols S.sub.N-1, S.sub.N are used to represent any pair of consecutive symbols among the OFDM symbols 12(1)-12(14). Understandably, the modulation symbol S.sub.N-1 is an immediately preceding modulation symbol of the modulation symbol S.sub.N. Accordingly, the modulation symbol S.sub.N is an immediate succeeding modulation symbol of the modulation symbol S.sub.N-1.

[0038] Herein, the wireless transmission circuit 14 includes a power amplifier circuit 20. The power amplifier circuit 20 is configured to amplify an RF signal 22 based on an APT voltage V.sub.CC. The PMIC 16 is configured to generate the APT voltage V.sub.CC based on a target voltage V.sub.TGT. The transceiver circuit 18 is configured to generate the RF signal 22 associated with a time-variant power envelope P(t) and provide the RF signal 22 to the power amplifier circuit 20. The transceiver circuit 18 is also configured to generate the target voltage V.sub.TGT in accordance with the time-variant power envelope P(t) and provide the target voltage V.sub.TGT to the PMIC 16.

[0039] The PMIC 16 is configured to include a voltage generation circuit 24 and a control circuit 26. In an embodiment, the voltage generation circuit 24 may be a direct-current-to-direct-current (DC-DC) converter circuit, which can operate in a buck mode and/or a boost mode, to generate the APT voltage V.sub.CC. The control circuit 26, on the other hand, can be configured according to various embodiments to accelerate intra-symbol changes of the APT voltage V.sub.CC. As described in detail below, the control circuit 26 is configured to determine whether the target voltage V.sub.TGT indicates an increased level(s) (denoted as V.sub.CC+ hereinafter) of the APT voltage V.sub.CC relative to an average level (denoted as V.sub.CC-AVG hereinafter) of the APT voltage V.sub.CC in any modulation symbol, such as any of the OFDM symbols 12(1)-12(14) in FIG. 1. In response to determining that the target voltage V.sub.TGT does indicate the increased level(s) of the APT voltage V.sub.CC, the control circuit 26 will control the voltage generation circuit 24, based on a multi-damping scheme, a multi-target scheme, or a multi-injection scheme, to increase the APT voltage V.sub.CC from the average level to the increased level(s) within a defined temporal limit (e.g., <1 microsecond). By supporting the intra-symbol voltage change acceleration, the wireless transmission circuit 14 can adapt the APT voltage V.sub.CC in a timely manner to thereby improve operating efficiency of the power amplifier circuit 20 and prevent unwanted distortion (e.g., amplitude clipping) in the RF signal 22.

[0040] FIG. 3 is a graphic diagram providing an exemplary illustration as to how the transceiver circuit 18 in FIG. 1 can generate the target voltage V.sub.TGT to enable the PMIC 16 to accelerate intra-symbol change of the APT voltage V.sub.CC. In an embodiment, the transceiver circuit 18 is configured to generate the target voltage V.sub.TGT by comparing the time-variant power envelope P(t) of the RF signal 22 against a predefined power threshold P.sub.TH. Specifically, the transceiver circuit 18 will generate the target voltage V.sub.TGT to indicate the increased level(s) of the APT voltage V.sub.CC whenever the time-variant power envelope P(t) is higher than the predefined power threshold P.sub.TH or to generate the target voltage V.sub.TGT to indicate the average level of the APT voltage V.sub.CC whenever the time-variant power envelope P(t) is lower than or equal to the predefined power threshold P.sub.TH.

[0041] For example, during the modulation symbol S.sub.N-1, the transceiver circuit 18 detects that the time-variant power envelope P(t) is higher than the predefined power threshold P.sub.TH at times T.sub.X, T.sub.Y, and T.sub.Z. Accordingly, the transceiver circuit 18 will generate the target voltage V.sub.TGT to indicate the increased levels V.sub.CC+ of the APT voltage V.sub.CC at times T.sub.X, T.sub.Y, and T.sub.Z. In contrast, during the modulation symbol S.sub.N, the time-variant power envelope P(t) is always lower than the predefined power threshold P.sub.TH. As a result, the transceiver circuit 18 will generate the target voltage V.sub.TGT to indicate the average level V.sub.CC-AVG for an entire duration of the modulation symbol S.sub.N. Herein, the transceiver circuit 18 may generate the target voltage V.sub.TGT as a digital target voltage V.sub.TGT-D and/or as an analog target voltage V.sub.TGT-A.

[0042] To satisfy increasingly stringent switching budgets demanded by such advanced wireless communication systems as fifth generation (5G), 5G new-radio (5G-NR), and/or sixth generation (6G) systems, the PMIC 16 must be able to increase the APT voltage V.sub.CC from the average level V.sub.CC-AVG to each of the increased levels V.sub.CC+ within the defined temporal limit. In this regard, the wireless transmission circuit 14 of FIG. 2 can be configured to accelerate each change of the APT voltage V.sub.CC within the defined temporal limit based on various embodiments described below.

[0043] In one embodiment, the wireless transmission circuit 14 can be configured to accelerate an intra-symbol voltage change based on a multi-damping scheme. FIG. 4 is a graphic diagram providing an exemplary illustration of the multi-damping scheme that can be employed by the PMIC in FIG. 2 to support intra-symbol voltage change acceleration.

[0044] As an example, each change of the APT voltage V.sub.CC from the average level V.sub.CC-AVG to an increased level V.sub.CC+ during any of the modulation symbols S.sub.N-a 1, S.sub.N can be made based on a sequence of voltage change segments S.sub.G1, S.sub.G2, and S.sub.G3. Each of the voltage change segments S.sub.G1, S.sub.G2, and S.sub.G3 is associated with a respective one of a sequence of voltage damping factors .sub.1, .sub.2, and .sub.3 (.sub.1.sub.2.sub.3).

[0045] Understandably, a voltage damping factor is typically defined as a ratio between a load impedance (Z.sub.L) and a source impedance (Z.sub.S) (=Z.sub.L/Z.sub.S) of a particular circuit. For a voltage converter, such as a DC-DC converter, the damping factor inversely determines a voltage settling time of the voltage converter. More specifically, the smaller the damping factor, the faster the voltage converter can change from one voltage level to another.

[0046] According to an embodiment of the present disclosure, the PMIC 16 is configured to increase the APT voltage V.sub.CC at a fastest rate during the voltage change segment S.sub.G1 based on an over-damped voltage damping factor .sub.1 (.sub.1<1). During the voltage change segment S.sub.G2, the PMIC 16 is configured to increase the APT voltage V.sub.CC at a slower rate than that of the voltage change segment S.sub.G1 based on a critical-damped damping factor .sub.2 (.sub.2=1). Subsequently during the voltage change segment S.sub.G3, the PMIC 16 is configured to increase the APT voltage V.sub.CC at an even slower rate than that of the voltage change segment S.sub.G2 based on an under-damped damping factor .sub.3 (.sub.3>1).

[0047] In this regard, the voltage change segments S.sub.G1, S.sub.G2, and S.sub.G3 can be referred to as an over-damped segment, a critical-damped segment, and an under-damped segment, respectively. In a non-limiting example, the PMIC 16 is configured to increase the APT voltage V.sub.CC to approximately 90% of the increased level V.sub.CC+ during the voltage change segment S.sub.G1 based on the over-damped voltage damping factor .sub.1 and to approximately 98% of the increased level V.sub.CC+ during the voltage change segment S.sub.G2 based on the critical-damped voltage damping factor .sub.2.

[0048] FIG. 5 is a schematic diagram of the PMIC 16 in FIG. 2 configured according to one embodiment of the present disclosure to support intra-symbol voltage change acceleration based on the multi-damping scheme of FIG. 4. Herein, the PMIC 16 includes a voltage generation circuit 28, a control circuit 30, and a digital interface 32. In a non-limiting example, the digital interface 32 can be an RF frontend (RFFE) interface. In an embodiment, the transceiver circuit 18 may be configured to provide the digital target voltage V.sub.TGT-D during or prior to each of the modulation symbols S.sub.N-1, S.sub.N via multiple RFFE writes. The RFFE writes may be distributed uniformly or non-uniformly during a respective one of the symbols S.sub.N-1, S.sub.N.

[0049] In an embodiment, the voltage generation circuit 28 may be a DC-DC converter that can operate in a buck mode and/or a boost mode. The control circuit 30 is configured to receive the digital target voltage V.sub.TGT-D from the transceiver circuit 18 via the digital interface 32 and control the voltage generation circuit 28 to generate the APT voltage V.sub.CC in accordance with the digital target voltage V.sub.TGT-D. Specifically, the control circuit 30 is configured to determine whether the target voltage V.sub.TGT-D indicates a change of the APT voltage V.sub.CC from the average level V.sub.CC-AVG to the increased level V.sub.CC+ in any of the modulation symbols S.sub.N-1, S.sub.N. If so, the control circuit 30 will control the voltage generation circuit 28 based on the multi-damping scheme to change the APT voltage V.sub.CC from the average level V.sub.CC-AVG to each of the increased levels V.sub.CC+ within the defined temporal limit. Otherwise, the control circuit 30 will control the voltage generation circuit 28 to generate the APT voltage at the average level V.sub.CC-AVG.

[0050] In a non-limiting example, the control circuit 30 can include a timer 34, an acceleration circuit 36, a lookup table (LUT) 38, a voltage loop control 40, and a feedback circuit 42. The LUT 38 may be used to store different loop coefficient values that are needed for the voltage loop control 40 for controlling the voltage generation circuit 28 based on the damping factors .sub.1, .sub.2, and .sub.3. The timer 34 may generate the sequence of voltage change segments S.sub.G1, S.sub.G2, S.sub.G3. The acceleration circuit 36 may determine the damping factors .sub.1, .sub.2, and .sub.3 for the voltage change segments S.sub.G1, S.sub.G2, S.sub.G3 based on the loop coefficient values retrieved from the LUT 38 and provide the damping factors .sub.1, .sub.2, and .sub.3, and corresponding voltage change segments S.sub.G1, S.sub.G2, S.sub.G3, to the voltage loop control 40. The voltage loop control 40, in turn, may control the voltage generation circuit 28 to change the APT voltage V.sub.CC from the average level V.sub.CC-AVG to the increased level V.sub.CC+ based on the determined damping factors .sub.1, .sub.2, and .sub.3. In an embodiment, the voltage loop control 40 may include a memory, a state machine engine, and/or an internal counter (not shown) to keep track of the position of the current settling process. The feedback circuit 42 may provide feedback of the APT voltage V.sub.CC (denoted as V.sub.CC-FB) and/or feedback of a load current I.sub.CC (denoted as I.sub.CC-FB) caused by the APT voltage V.sub.CC to the voltage loop control 40.

[0051] Alternative to supporting intra-symbol voltage change acceleration based on the multi-damping scheme, the PMIC 16 may be configured to support intra-symbol voltage change acceleration based on a multi-target scheme. In this regard, FIG. 6 is a graphic diagram providing an exemplary illustration of a multi-target scheme that can be employed by the PMIC 16 in FIG. 5 to support intra-symbol voltage change acceleration.

[0052] Herein, the acceleration circuit 36 may determine a sequence of voltage change segments S.sub.G1, S.sub.G2 each associated with a respective one of multiple voltage targets V.sub.TGT1, V.sub.TGT2. More specifically, the acceleration circuit 36 may set an initial one of the voltage targets V.sub.TGT1, V.sub.TGT2 (a.k.a. V.sub.TGT1) in an initial one of the voltage change segments S.sub.G1, S.sub.G2 (a.k.a. S.sub.G1) to be higher than the increased level V.sub.CC+ in a respective one of the modulation symbols S.sub.N-1, S.sub.N. By setting the initial target voltage V.sub.TGT1 above the increased level V.sub.CC+, the voltage generation circuit 28 can increase the APT voltage V.sub.CC in the initial voltage change segment S.sub.G1 along a steeper curve 44. In contrast, if the initial target voltage V.sub.TGT1 is not set above the increased level V.sub.CC+, the voltage generation circuit 28 can increase the APT voltage V.sub.CC in the initial voltage change segment S.sub.G1 along a shallower curve 46. In addition, the acceleration circuit 36 may set a subsequent one of the voltage targets V.sub.TGT1, V.sub.TGT2 (e.g., V.sub.TGT2) in a subsequent one of the voltage change segments S.sub.G1, S.sub.G2 (e.g., S.sub.G2) to be equal to the increased level V.sub.CC+ in a respective one of the modulation symbols S.sub.N-1, S.sub.N.

[0053] In another embodiment, the wireless transmission circuit 14 of FIG. 2 can be configured to accelerate intra-symbol voltage change based on a multi-injection scheme. In this regard, FIG. 7 is a graphic diagram illustrating a multi-injection scheme performed by the PMIC 16 in FIG. 2 to support intra-symbol voltage change acceleration.

[0054] As described in detail below, the PMIC 16 can be configured to inject one or more acceleration currents into one or more selected injection points to help accelerate a change of the APT voltage V.sub.CC from the average level V.sub.CC-AVG to the increased level V.sub.CC+ in a respective one of the modulation symbols S.sub.N-1, S.sub.N. As illustrated in FIG. 7, by injecting the acceleration currents into the selected injection points, the APT voltage V.sub.CC will increase from the average level V.sub.CC-AVG to the increased level V.sub.CC+ along a steeper curve 48. Without the acceleration currents, the APT voltage V.sub.CC may have to increase from the average level V.sub.CC-AVG to the increased level V.sub.CC+ along a shallower curve 50.

[0055] FIG. 8 is a schematic diagram of the PMIC 16 in FIG. 2, which is configured according to another embodiment of the present disclosure to accelerate intra-symbol voltage change based on the multi-injection scheme in FIG. 7. Common elements between FIGS. 5 and 8 are shown therein with common element numbers and will not be re-described herein.

[0056] Herein, the PMIC 16 includes a control circuit 52 and an analog interface 54. In an embodiment, the transceiver circuit 18 may be configured to provide the analog target voltage V.sub.TGT-A during or prior to each of the modulation symbols S.sub.N-1, S.sub.N via the analog interface 54. The PMIC 16 may also include the digital interface 32, which may receive the digital target voltage V.sub.TGT-D from the transceiver circuit 18, in addition to the analog target voltage V.sub.TGT-A.

[0057] In an embodiment, the control circuit 52 includes an acceleration circuit 56, a voltage loop control 58, a current loop control 60, and a comparator 62. The acceleration circuit 56 is configured to generate one or more of multiple acceleration currents I.sub.ACC-1, I.sub.ACC-2, I.sub.ACC-3, and I.sub.ACC-4 based on the analog target voltage V.sub.TGT-A. Specifically, the acceleration circuit 56 may inject the acceleration current I.sub.ACC-1 into the voltage loop control 58 via a first transconductance circuit Gm-V and inject the acceleration current I.sub.ACC-2 into the current loop control 60 via a second transconductance circuit Gm-I. The acceleration circuit 56 may also inject the acceleration current I.sub.ACC-3 into an output 64 of the voltage generation circuit 28 via a third transconductance circuit Gm-O.

[0058] The acceleration circuit 56 may further inject the acceleration current I.sub.ACC-4 into an input 66 of the comparator 62 via a compensation circuit 68. The compensation circuit 68 may include variable components that may be needed when a pre-distortion of the target voltage is used. The PMIC 16 can also include a feedback circuit 70. The feedback circuit 70 can provide feedback of the APT voltage V.sub.CC (denoted as V.sub.CC-FB) and feedback of the load current I.sub.CC (denoted as I.sub.CC-FB) to the voltage loop control 58 and the current loop control 60, respectively.

[0059] FIG. 9 is a schematic diagram of the transceiver circuit 18 in FIG. 2 that can be configured according to an embodiment to generate the modulated target voltage V.sub.TGT in FIG. 3. Common elements between FIGS. 2 and 9 are shown therein with common element numbers and will not be re-described herein.

[0060] In an embodiment, the transceiver circuit 18 includes a digital baseband circuit 72, an envelope detection circuit 74, a target voltage circuit 76, and a modulator circuit 78. The digital baseband circuit 72 is configured to generate a digital signal 80, which can include an in-phase (I) component and a quadrature (Q) component. The I component and the Q component collectively define a time-variant amplitude envelope {square root over (I.sup.2+Q.sup.2)}. The envelope detection circuit 74 is configured to compare the time-variant amplitude envelope {square root over (I.sup.2+Q.sup.2)} against the predefined power threshold P.sub.TH to determine whether to indicate the increased levels V.sub.CC+ of the APT voltage V.sub.CC in the target voltage V.sub.TGT. The target voltage circuit 76 is configured to generate the digital target voltage V.sub.TGT-D to indicate the increased levels V.sub.CC+ in a respective one of the modulation symbols S.sub.N-1, S.sub.N whenever the envelope detection circuit 74 determines that the time-variant amplitude envelope {square root over (I.sup.2+Q.sup.2)} is above the predefined power threshold P.sub.TH. The transceiver circuit 18 may include a digital-to-analog converter (DAC) 82, which may convert the digital target voltage V.sub.TGT-D into the analog target voltage V.sub.TGT-A.

[0061] The modulator circuit 78 is configured to convert the digital signal 80 into the RF signal 22. The modulator circuit 78 is also configured to generate the time-variant power envelope P(t) from the time-variant amplitude envelope {square root over (R.sup.2+Q.sup.2)}. The modulator circuit 78 may be further configured to upshift the RF signal 22 from a baseband frequency to an intermediate frequency (IF) or a carrier frequency.

[0062] The transceiver circuit 18 may further include a digital predistortion (DPD) circuit 84. The DPD circuit 84 can be configured to pre-distort the digital signal 80 to thereby correct potential amplitude-amplitude (AMAM) and/or amplitude-phase (AMPM) distortion in the RF signal 22 when the RF signal 22 is amplified at the power amplifier circuit 20. In an embodiment, the envelope detection circuit 74 may feed additional information into the DPD circuit 84 to help correct the AMAM and/or AMPM distortion.

[0063] The wireless transmission circuit 14 of FIG. 2 can be provided in a user element to support intra-symbol voltage change acceleration according to embodiments described above. In this regard, FIG. 10 is a schematic diagram of an exemplary user element 100 wherein the wireless transmission circuit 14 of FIG. 1 can be provided.

[0064] Herein, the user element 100 can be any type of user elements, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications. The user element 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 110, multiple antennas 112, and user interface circuitry 114. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 108 receives radio frequency signals via the antennas 112 and through the antenna switching circuitry 110 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converter(s) (ADC).

[0065] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0066] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas 112 through the antenna switching circuitry 110. The multiple antennas 112 and the replicated transmit and receive circuitries 106, 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0067] The wireless transmission circuit 14 of FIG. 2 can be configured to accelerate intra-symbol voltage change in accordance with a process. In this regard, FIG. 11 is a flowchart of an exemplary process 200 that can be employed by the wireless transmission circuit 14 of FIG. 2 for accelerating intra-symbol voltage change.

[0068] Herein, the power amplifier circuit 20 is configured to amplify the RF signal 22, which is modulated in the modulation symbols S.sub.N-1, S.sub.N, based on the APT voltage V.sub.CC (step 202). The transceiver circuit 18 is configured to generate the target voltage V.sub.TGT in accordance with the time-variant power envelope P(t) of the RF signal 22 (step 204). The voltage generation circuit 24 is configured to generate the APT voltage V.sub.CC in each of the modulation symbols S.sub.N-1, S.sub.N based on the target voltage V.sub.TGT (step 206). The control circuit 26 is configured to determine that the target voltage V.sub.TGT indicates the increased levels V.sub.CC+ of the APT voltage V.sub.CC relative to the average level V.sub.CC-AVG of the APT voltage V.sub.CC in a respective one of the modulation symbols S.sub.N-1, S.sub.N (step 208). Accordingly, the voltage generation circuit 24 increases the APT voltage V.sub.CC from the average level V.sub.CC-AVG to each of the increased levels V.sub.CC+ within the defined temporal limit (step 210).

[0069] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.