Passive equalizer

Abstract

One example discloses s passive equalizer circuit, including: an input configured to receive an input signal having an input frequency band; a transfer function circuit configured to transform the input frequency band into an output frequency band; and an output configured to be coupled to an active equalizer circuit and carry an output signal having the output frequency band; wherein the transfer function circuit includes a variable impedance configured to adjust a mid-band frequency gain of the output signal.

Claims

1. A passive equalizer circuit, comprising: an input configured to receive an input signal having an input frequency band; a transfer function circuit configured to transform the input frequency band into an output frequency band; and an output configured to be coupled to an active equalizer circuit and carry an output signal having the output frequency band; wherein the transfer function circuit includes a variable impedance circuit configured to adjust a mid-band frequency gain of the output signal; wherein the variable impedance circuit includes a first variable capacitor (C.sub.4) having a variable capacitance in parallel with the active equalizer circuit; wherein the first variable capacitor adjusts a set of mid-band frequency gains of the output frequency band; wherein the first variable capacitor is in parallel with a first resistor (R.sub.4) having a resistance and in series with a second resistor (R.sub.3) having a resistance; and wherein the second resistor (R.sub.3) is coupled to the output.

2. The passive equalizer circuit of claim 1: wherein the passive equalizer circuit includes only passive resistive, and/or capacitive elements.

3. The passive equalizer circuit of claim 1: wherein a value of the first variable capacitor is statically trimmed using a set of one-time-adjustable passive elements.

4. The passive equalizer circuit of claim 1: wherein a value of the first variable capacitor is dynamically trimmed using a controller.

5. The passive equalizer circuit of claim 1: wherein the first variable capacitor includes a set of switches each coupled in series with a separate capacitor; and wherein an open and closed state of the set of switches adjusts the first variable capacitor.

6. The passive equalizer circuit of claim 1: wherein a pole of the set of mid-band frequency gains is equal to 1/(R.sub.4*C.sub.4).

7. The passive equalizer circuit of claim 1: wherein the variable impedance circuit further includes a second variable capacitor (C.sub.2) having a variable capacitance in series with the active equalizer circuit; and wherein the second variable capacitor adjusts a zero frequency of the output frequency band.

8. The passive equalizer circuit of claim 7: wherein the first variable capacitor includes a first set of switches each coupled in series with a separate capacitor; wherein an open and closed state of the first set of switches adjusts the first variable capacitor; wherein the second variable capacitor includes a second set of switches each coupled in series with a separate capacitor; and wherein an open and closed state of the second set of switches adjusts the second variable capacitor.

9. The passive equalizer circuit of claim 7: wherein the second variable capacitor is in parallel with a third resistor (R.sub.2) having a resistance and in series with a fourth resistor (R.sub.1) having a resistance; wherein the fourth resistor (R.sub.1) is coupled to the input; and wherein the third resistor (R.sub.2) and the second variable capacitor are coupled to the output.

10. The passive equalizer circuit of claim 9: wherein a ratio of the first (R.sub.4) to the second resistance (R.sub.3) is equal to a ratio of the third resistance (R.sub.2) to the fourth resistance (R.sub.1).

11. The passive equalizer circuit of claim 9: wherein a zero of the set of mid-band frequency gains is equal to 1/(R.sub.2*C.sub.2).

12. The passive equalizer circuit of claim 1: further comprising the active equalizer circuit coupled to the passive equalizer circuit.

13. The passive equalizer circuit of claim 1: wherein the active equalizer circuit is a continuous-time linear equalizer (CTLE).

14. The passive equalizer circuit of claim 1: wherein the active equalizer circuit is a linear equalizer.

15. The passive equalizer circuit of claim 1: wherein the active equalizer circuit is a decision-feedback equalizer (DFE).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A represents an example first active equalizer.

(2) FIG. 1B represents an example DC gain and transfer function for the example first active equalizer.

(3) FIG. 2A represents an example first passive equalizer.

(4) FIG. 2B represents an example combination of the first passive equalizer and an example second active equalizer.

(5) FIGS. 3A and 3B represent example mid-band frequency gain variation for the example combination.

(6) FIG. 4A represents an example second passive equalizer.

(7) FIG. 4B represents an example first set of frequency AC response curves.

(8) FIG. 4C represents an example second set of frequency AC response curves.

(9) FIG. 4D represents the second passive equalizer with capacitors Cs and Cp shown.

(10) FIG. 4E represents an example third set of frequency AC response curves showing an effect of the capacitors Cs and Cp on the example second set of frequency response curves.

(11) FIG. 5 represents an example of a third passive equalizer.

(12) FIG. 6 represents an example of a fourth passive equalizer.

(13) FIG. 7A represents an example set of mid-band frequency adjustments using either the second, third or fourth passive equalizers.

(14) FIG. 7B represents an example set of zero frequency adjustments using either the second, third or fourth passive equalizers.

(15) While the disclosure is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that other embodiments, beyond the particular embodiments described, are possible as well. All modifications, equivalents, and alternative embodiments falling within the spirit and scope of the appended claims are covered as well.

DETAILED DESCRIPTION

(16) Equalizers are employed at a receiver (RX) front end to compensate for channel loss and provide equalized low-jitter output signals. Linear equalizers ensure precursor as well as postcursor equalization. Continuous-time linear equalizers (CTLEs) are one class of linear equalizers. Nonlinear equalization techniques, like decision-feedback equalization (DFE), only realize postcursor equalization.

(17) The goal of an equalizer is to realize a transfer function which can be tuned such that it is the inverse of the channel transfer function. If properly tuned, the equalizer improves the receiver performance parameters, such as BER and jitter tolerance. A conventional capacitive source-degenerated first order equalizer, with one zero and two poles, provides limited capability to control the shape of equalizer transfer function.

(18) Equalizers are often coupled to other circuits and channels with long cables or PCB traces, resulting in non-linear insertion loss (e.g. frequency specific insertion losses). Since one role of an equalizer is compensation for such insertion losses, equalizers with higher loss compensation/higher order pole/zero enables compensation for higher losses.

(19) FIG. 1A represents an example first active equalizer 100. FIG. 1B represents an example DC gain and transfer function 102 for the example first active equalizer 100. The DC gain and transfer function 102 can be written as:

(20) $\begin{array}{cc}{A}_{\mathrm{dc}}=R_L/\left(R_g+1/g_m\right)& \left(1\right)\end{array}$$\begin{array}{cc}H\left(s\right)A_{\mathrm{ac}}\left(1+s{R}_g{C}_g\right)/\left(\left(1+2s{C}_g/g_m\right)\left(1+s\mathrm{RL}\mathrm{CL}\right)\right)& \left(2\right)\end{array}$

(21) where g.sub.m/2 is transconductance of differential pair transistors. As it is seen from equation 1, R.sub.g adjustment will change DC gain and zero location. It is difficult to get a high peaking gain and equal gain steps from the conventional architecture.

(22) The maximum gain will be:

(23) $\begin{array}{cc}{A}_{\mathrm{pk}}=g_m*R_L& \left(3\right)\end{array}$

(24) Although a CMOS based circuit is shown, a BJT based circuit follows the same rules.

(25) For conventional equalizer, the tuning of this type of equalizer is to change different source degeneration resistor for CMOS circuit or emitter degeneration resistor for BJT circuit. In this way, the DC attenuation will be changed while the peaking gain is fixed (Maximum peaking gain=g.sub.m.Math.R.sub.L), so that we can get different peaking of this equalizer.

(26) A problem of conventional structure is when we only change the degeneration resistor, the peaking frequency will change because the zero created by degeneration RC pair (.sub.zero=1/R.sub.g C.sub.g) while the capacitor is fixed. To keep the peak frequency fixed, R.sub.g and C.sub.g need to be tuned/adjusted to get different peaking gain and maintain the same peaking frequency.

(27) But for high speed applications, this tuning method can cause problems. Due to parasitic components, using discrete tuning steps, means there should be different resistor and capacitor settings for each step. In a fabricated circuit, the switches of all these steps will further introduce parasitic resistances and capacitances. These parasitic resistances and capacitances can't be well controlled and will cause unexpected peaking at low frequency or reduce the expected tuning range because the parasitic resistor and capacitor need to be calculated into the total amount of caps and resistors we can have for the tuning part, so the actual tuning range will be reduced by these parasitic effects.

(28) If varactors are used in the tuning capacitor, the varactors will introduce less parasitic to circuit, but the problem is the tuning is not predictable because the exact value of the varactor is unknown. Adding another tuning/trimming for varactor is expensive and adds more parasitic components.

(29) VT (voltage and temperature) variations can still affect the equalizer's gains after tuning/trimming, due to gain variations at zero and pole frequencies. Due to these many parasitic and PVT variation of components (L, R, C, g.sub.m), the middle frequency is particularly challenging.

(30) Programmable high-frequency peaking gain equalizers are able to compensate for frequency dependent insertion loss but are more complicated and require advanced techniques. For example, due to the nature of insertion loss variations and wide-band equalizer input signals, some programmability of DC gain and/or peaking gain is needed to provide the best equalization. Programming will need switchable components which have parasitic components which can't be handled easily by non-programmable circuits, so more advanced techniques are needed to make a programmable high frequency equalizer.

(31) Programmable high-frequency peaking gain equalizers with a more predictable equalization, require more precise peaking gain control. Circuit trimming/tuning schemes can help reduce some peaking gain variations, but trimming is usually applied only at DC and Nyquist frequency peaking gains.

(32) Even trimming at the peaking gain is itself a challenge since trimming while can be done at certain frequencies, there are gain variation at other frequencies can be more than the gain variations at the trimmed frequencies.

(33) Active component equalizers thus may not have a desired peaking gain control for many high-frequency applications. Cascading two active equalizers would result in even greater variations of peaking gain over PVT. Cascading an active equalizer with a passive equalizer is another possibility.

(34) FIG. 2A represents an example first passive equalizer 200. This passive equalizer's 200 transfer function can be written as: OUT/IN=Z.sub.2/(Z.sub.1+Z.sub.2)

(35) FIG. 2B represents an example combination 202 of the first passive equalizer 200 and an example second active equalizer 204 that is a generalized version of the first active equalizer 100. This combination 202 enables a sharper positive/negative gain slope. While the added passive equalizer 200 will bring some low frequency loss, extra poles and zeros will be added to it frequency response (e.g. AC response) transfer function. Such combination 202 however still includes gain variations, particularly in mid-band frequencies.

(36) FIGS. 3A and 3B represent example mid-band frequency variation 300, 302 for a simulation of the example combination for 200 and 202. In these example, the pole/zero results in a +/1, 2, 3 dB gain/loss at a 4 GHz mid-band frequency.

(37) Thus a proper gain or loss at mid-band frequencies can have a considerable effect on eye-height and eye-width. Thus the mid-band frequency gain needs to be predictable and stable to enable the combination equalizer 202 to be used reliably in a lossy system. Final effect varies for different set ups and system, but the achieved information is valid as general impact of mid-band signal spectrum on output eye-diagram.

(38) Now discussed are example embodiments of a passive equalizer circuit that provides a simpler, more predictable, and tunable equalization curve when cascaded with an active equalizer, particularly at zero and mid-band frequencies. The passive equalizer circuit components have lower gain variations over PVT (process, voltage, temperature). The zero and mid-band frequencies of the equalization curve can be tuned either statically (using trimming elements) or dynamically (using a controller).

(39) The passive equalizer circuit can be applied in any circuit where equalization is needed such as a signal conditioner/redriver for USB3, USB4, DP, PCIe4, PCIe5, PCIe6 or any other wired high speed communication standards.

(40) FIG. 4A represents an example second passive equalizer 400. The second passive equalizer 400 is shown in a single ended form and includes a signal input (V.sub.IN), a signal output (V.sub.OUT), a resistor R.sub.1, a resistor R.sub.2, a variable capacitance C.sub.2, a resistor R.sub.3, a resistor R.sub.4, and a variable capacitance C.sub.4.

(41) Since capacitors are open at low frequencies, gain at low frequency can be calculated as: Gain(low frequency)=(R.sub.3+R.sub.4)/(R.sub.1+R.sub.2+R.sub.3+R.sub.4). Also since capacitors are shorted at high frequencies, gain at high frequency: can be calculated as: Gain(high-frequency)=R.sub.3/(R.sub.1+R.sub.3). A zero frequency is defined as 1/(R.sub.2C.sub.2). A mid-band pole frequency is defined as 1/(R.sub.4C.sub.4). For equal high-frequency and low-frequency gains R.sub.3/R.sub.4=R.sub.1/R.sub.2.

(42) The passive equalizer circuit's 400 input VIN is configured to receive an input signal having an input frequency band. The passive equalizer circuit 400 operates as a transfer function circuit that transform the input frequency band into an output frequency band. The output VOUT in some example embodiments is configured to be coupled to an active equalizer circuit 401 (e.g. see FIGS. 1 and 2B) and carries an output signal having the output frequency band. The passive equalizer circuit 400 includes a first variable impedance (e.g. C4, but could also be R4, or a combination of both elements) configured to adjust a mid-band frequency gain of the output signal.

(43) The passive equalizer circuit 400 also includes a second variable impedance (e.g. C.sub.2, but could also be R.sub.2, or a combination of both elements) configured to adjust a zero frequency gain of the output signal.

(44) Peaking gain at low-frequencies and high-frequencies will be equal, but at mid-band frequencies the peaking gain will vary depending on the selected values for C.sub.2 and C.sub.4.

(45) In this example embodiment, C2 and C4 include trimmable elements and/or are programmable using a controller 403. By varying C2 and C4, the zero and mid-band pole frequencies can be independently set as desired.

(46) In other example embodiments, R.sub.2 and R.sub.4 include statically/one-time trimmable elements and/or are programmable using a controller and can also independently set the zero frequency and the mid-band pole frequency. In various example embodiments, R.sub.2, C.sub.2, R.sub.4 and C.sub.4 all include statically/one-time trimmable elements and/or are programmable using a controller.

(47) Those skilled in the art will recognize that high frequency and low frequencies are relative and depend upon the applications that include the second passive equalizer 400.

(48) FIG. 4B represents an example set of zero frequency AC response curves 402. In this example embodiment, the zero frequency AC response curve 402 is shifted to the right (i.e. higher Fzero=1/R.sub.2C.sub.2) as C.sub.2 is decreased while C.sub.4=0.

(49) FIG. 4C represents an example set of mid-band pole frequency AC response curves 404. In this example embodiment, the pole frequency AC response curve 404 is shifted to the right (i.e. higher Fpole=1/R.sub.4C.sub.4) as C.sub.4 is decreased while C.sub.2=0.

(50) FIG. 4D represents the second passive equalizer 400 with capacitors Cs and Cp shown. In various example embodiments, Cp can be a parasitic input capacitance of a next equalizer stage or other circuit. Cs is then added to compensate for Cp.

(51) FIG. 4E represents an example set of combined zero and mid-band pole frequency AC response curves 406 showing an effect of Cs and the parasitic Cp on the example second set of frequency response curves 404.

(52) FIG. 5 represents an example of a third passive equalizer 500. The third passive equalizer 500 is shown in differential form and includes a differential signal input (V.sub.IN, V.sub.IP), a signal output (V.sub.ON, V.sub.OP), resistors R.sub.1, resistors R.sub.2, capacitances C.sub.2, resistors R.sub.3, a resistor 2*R.sub.4, and a variable capacitance matrix.

(53) The variable capacitance matrix includes M capacitive array elements. Each capacitive array element including first capacitance C.sub.4, switch SWm, and a second capacitance C.sub.4,m, where variable m ranges from 1 to M.

(54) The third passive equalizer 500 operates the same as the second passive equalizer circuit 400 except that zero frequency capacitances C.sub.2 are fixed. Values of C.sub.4,1 to C.sub.4,M will be selected for the needed mid-band frequency programmability.

(55) FIG. 6 represents an example of a fourth passive equalizer 600. The fourth passive equalizer 600 is also shown in differential form and includes a differential signal input (V.sub.IN, V.sub.IP), a signal output (V.sub.ON, V.sub.OP), resistors R.sub.1, resistors R.sub.2, a first variable capacitance matrix for varying C.sub.2, resistors R.sub.3, a resistor 2*R.sub.4, and a second variable capacitance matrix for varying C.sub.4.

(56) The first variable capacitance matrix for varying C.sub.2 includes N capacitive array elements. Each capacitive array element including a switch SWn, and a capacitance C.sub.4,n, where variable n ranges from 1 to N.

(57) The second variable capacitance matrix for varying C.sub.4 includes M capacitive array elements. Each capacitive array element including first capacitance C.sub.4, switch SWm, and a second capacitance C.sub.4,m, where variable m ranges from 1 to M.

(58) The fourth passive equalizer 600 operates the same as the second passive equalizer circuit 400. Values of C.sub.2,1 to C.sub.2,N will be selected for the needed zero frequency programmability, and values of C.sub.4,1 to C.sub.4,M will be selected for the needed mid-band frequency programmability.

(59) FIG. 7A represents an example set of mid-band frequency adjustments 700 using either the second, third or fourth passive equalizers 400, 500, 600. In various example embodiments, adjusting the mid-band frequency is more important for enabling a stable equalization.

(60) FIG. 7B represents an example set of zero frequency adjustments 702 using either the second, third or fourth passive equalizers 400, 500, 600. This Figures shows that an equalizer's zero frequency can be better controlled as well.

(61) It will be readily understood that the components of the embodiments as generally described herein and illustrated in the appended figures could be arranged and designed in a wide variety of different configurations. Thus, the detailed description of various embodiments, as represented in the figures, is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

(62) The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by this detailed description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

(63) Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present invention should be or are in any single embodiment of the invention. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. Thus, discussions of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same embodiment.

(64) Furthermore, the described features, advantages, and characteristics of the invention may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize, in light of the description herein, that the invention can be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the invention.

(65) Reference throughout this specification to one embodiment, an embodiment, or similar language means that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present invention. Thus, the phrases in one embodiment, in an embodiment, and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.