ZENER DIODE

Abstract

A Zener diode comprising: a PN junction formed in a semiconductor material; and one or more stress-inducing regions configured to impart a compressive stress in the PN junction along a current flow direction of the PN junction.

Claims

1. A Zener diode comprising: a PN junction formed in a semiconductor material; and one or more stress-inducing regions configured to impart a compressive stress in the PN junction along a current flow direction of the PN junction.

2. The Zener diode of claim 1, wherein the PN junction comprises a N-type region in contact with a P-type region and the one or more stress-inducing regions comprise one or more of: a first stress-inducing region in contact with the P-type region; and a second stress-inducing region in contact with the N-type region.

3. The Zener diode of claim 1, wherein one or more dimensions of the one or more stress-inducing regions is selected to control a value of the compressive stress in the PN junction along the current flow direction of the PN junction.

4. The Zener diode of claim 1, wherein the Zener diode comprises a layered structure including: a first layer formed in the semiconductor material; a second layer formed in the semiconductor material between the first layer and a surface of the semiconductor material; and a stress-inducing layer positioned on the surface of the semiconductor material to form one of the one or more stress-inducing regions, wherein the first layer and the second layer each comprise a different one of a P-type region and a N-type region to form the PN junction.

5. The Zener diode of claim 4, wherein the stress-inducing layer comprises a tensile stressed layer configured to impart a tensile stress to the second layer in one or more axes parallel to a plane of the second layer.

6. The Zener diode of claim 5, wherein the stress-inducing layer comprises a biaxial tensile stressed layer.

7. The Zener diode of claim 4, wherein the stress-inducing layer is indirectly positioned on the surface of the semiconductor material and an oxide layer is positioned between the surface of the semiconductor material and the stress-inducing layer.

8. The Zener diode of claim 1, wherein the PN junction comprises a N-type region positioned adjacent to a P-type region with an interface between the N-type region and the P-type region being perpendicular to a top surface of the semiconductor material, wherein the one or more stress-inducing regions comprise one or more of: a first stress-inducing region adjacent to the P-type region on an opposite side to the N-type region; and a second stress-inducing region adjacent to the N-type region on an opposite side to the P-type region.

9. The Zener diode of claim 8, wherein the one or more stress-inducing regions each comprise a shallow trench isolation feature.

10. The Zener diode of claim 8, wherein the one or more stress-inducing regions comprise: a first stress-inducing region adjacent to the P-type region on an opposite side to the N-type region; and a second stress-inducing region adjacent to the N-type region on an opposite side to the P-type region, wherein a separation of the first stress-inducing region and the second stress-inducing region is selected to control a value of the compressive stress in the PN junction in the current flow direction.

11. The Zener diode of claim 1, wherein the Zener diode comprises: a first region formed in the semiconductor material; and a second region formed in the semiconductor material and surrounding the first region to form a PN junction in a junction plane, wherein the first region and the second region each comprise a different one of a P-type region and a N-type region to form the PN junction, wherein the one or more stress-inducing regions include a stress-inducing region surrounding the second region.

12. The Zener diode of claim 11, wherein the stress-inducing region comprises a shallow trench isolation feature.

13. The Zener diode of claim 1, wherein the semiconductor material comprises Silicon.

14. An integrated circuit comprising the Zener diode of claim 1.

15. A method of manufacturing a Zener diode comprising the steps of: providing a semiconductor material; forming a PN junction in the semiconductor material; and forming one or more stress-inducing regions in or on the semiconductor material, wherein the one or more stress-inducing regions are configured to impart a compressive stress in the PN junction along a current flow direction of the PN junction.

16. The method of claim 15, wherein forming the PN junction comprises: forming a N-type region; and forming a P-type region in contact with the N-type region; and wherein forming the one or more stress-inducing regions comprises: forming a first stress-inducing region in contact with the P-type region; or a second stress-inducing region in contact with the N-type region.

17. The method of claim 15, comprising selecting one or more dimensions of the one or more stress-inducing regions to control a value of the compressive stress in the PN junction along the current flow direction of the PN junction.

18. The Zener diode of claim 4, wherein: the first layer comprises a P-type region and the second layer comprises a N-type region; or the first layer comprises a N-type region and the second layer comprise a P-type region.

19. The Zener diode of claim 4, wherein the current flow direction is perpendicular to the interface of the first layer and the second layer.

20. The Zener diode of claim 4, wherein the semiconductor material comprises Silicon.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0046] One or more embodiments will now be described by way of example only with reference to the accompanying drawings in which:

[0047] FIG. 1A shows an example Zener diode according to an embodiment of the present disclosure;

[0048] FIG. 1B shows a second example Zener diode according to an embodiment of the present disclosure;

[0049] FIG. 1C shows a third example Zener diode according to an embodiment of the present disclosure;

[0050] FIGS. 2A to 2E illustrate a process for manufacturing the Zener diode of FIG. 1A according to an embodiment of the present disclosure;

[0051] FIGS. 3A to 3D illustrate a process for manufacturing the Zener diode of FIG. 1B according to an embodiment of the present disclosure;

[0052] FIG. 4 illustrates a method of manufacturing a Zener diode according to an embodiment of the present disclosure;

[0053] FIG. 5A illustrates a measured variation in breakdown voltage in response to the application of compressive stress along a current flow direction of a PN junction of a Zener diode;

[0054] FIG. 5B illustrates a measured variation in breakdown voltage in response to the application of tensile stress along a current flow direction of a PN junction of a Zener diode; and

[0055] FIG. 6 illustrates a simulation of the variation in Zener breakdown voltage in dependence of stress along the current flow direction.

DETAILED DESCRIPTION

[0056] Precision analog circuitry can require accurate voltage reference circuits. A Zener diode can be a critical component in circuit operation of Zener reference circuits. An integrated circuit (IC) chip may undergo multiple thermal cycles during qualification that change the package stress. The resulting stress buildup can impact a Zener breakdown voltage of the Zener diode and affect the accuracy of the analog circuitry. One such application of Zener reference circuits is a battery management system (BMS). A BMS can require a battery cell voltage measurement accuracy of +/1 mV over a 5 V cell (+/0.02%). However, drift in the Zener breakdown voltage due to packaging and aging can be on the order of 0.1%.

[0057] Hence there is a need for a stress immune Zener diode design.

[0058] The present disclosure provides a Zener diode incorporating built-in compressive stress along a current flow direction that provides for reduced sensitivity of the Zener breakdown voltage to package stress or external stress.

[0059] FIGS. 1A to 1C illustrate example Zener diodes 100 according to respective embodiments of the present disclosure. The figures illustrate a cross-section of the Zener diode 100. FIG. 1C further illustrates a plan view of the respective Zener diode.

[0060] The Zener diode 100 comprises a PN junction 102 formed in a semiconductor material 104, and one or more stress-inducing regions 106-1, 106-2 configured to impart a compressive stress (illustrated by arrows 107) in the PN junction 102 along a current flow direction 108 of the PN junction 102.

[0061] The PN junction 102 may comprise a N-type region 110 in contact with a P-type region 112. The current flow direction 108 is perpendicular to an interface 114 of the N-type region 110 with the P-type region 112 (i.e. the PN junction 102). In other words, the current flow direction 108 is perpendicular to the PN junction 102. The current flow direction 108 is illustrated as being from the P-type region 112 to the N-type region 110 and vice-versa because the current flow direction 108 will vary depending on whether the PN junction 102 is forward biased or reverse biased.

[0062] The one or more stress-inducing regions 106-1, 106-2 may comprise either or both of: (i) a first stress-inducing region 106-1 in contact with the P-type region 112; and (ii) a second stress-inducing region 106-2 in contact with the N-type region 114. For example, the Zener diode of FIG. 1A may have the positions of the N-type region 110 and the P-type region 112 reversed such that the N-type region 110 is in contact with the stress-inducing region.

[0063] The semiconductor material 104 may comprise a semiconductor substrate such as a semiconductor epitaxial layer.

[0064] Turning specifically to the first example of FIG. 1A, the Zener diode 100 can comprise a layered structure. In this example, the N-type region 110 comprises a first layer formed in the semiconductor material 104 and the P-type region 112 comprises a second layer formed in the semiconductor material 104 positioned between the first layer and a surface of the semiconductor material 104. As referred to herein, the surface of the semiconductor material 104 may refer to a top surface or a contact surface of the semiconductor material 104, i.e. the top surface as illustrated in each of FIGS. 1A-1C, 2A-2E and 3A-3D. In other examples, the N-type region 110 may form the second layer and the P-type region 112 may form the first layer.

[0065] The first layer and the second layer both extend along orthogonal axes (X, Z) parallel to a (XZ) plane of the surface of the semiconductor material 104. In other words, the first and second layers extend in a plane parallel to the place of the surface of the semiconductor material 104. The first layer and the second layer form the PN junction 102. As a result, the current flow direction 108 is in an axis (Y) perpendicular to the interface 114 of the PN junction (interface of first and second layers), i.e. in an axis (Y) perpendicular to the (XZ) plane of the surface of the semiconductor material 104.

[0066] In this example, the one or more stress-inducing regions 106-1, 106-2 comprise a stress-inducing layer 106-1 positioned on the surface of the semiconductor material 104. In some examples, the stress-inducing layer 106-1 may be positioned directly on the surface of the semiconductor material 104 (as illustrated). In other examples, the stress-inducing layer 106-1 may be positioned indirectly on the surface of the semiconductor material 104 with one or more intervening layers positioned between the semiconductor surface and the stress-inducing layer 106-1. In this example, a surface of the second layer forms the surface of the semiconductor material 104 such that the stress-inducing layer 106-1 is positioned on the second layer.

[0067] The stress-inducing layer 106-1 may comprise a tensile stressed layer 106-1 that imparts a tensile stress in one or more axes parallel to the (XZ) plane of the second layer/surface of the semiconductor material 104 (as illustrated in the figure by arrows 111). In other words, the tensile stressed layer 106-1 stretches the PN junction 102 laterally along one or more axes parallel to the (XZ) plane of the second layer/surface, i.e. perpendicular to the current flow direction 108. By stretching the PN junction 102 perpendicular to the current flow direction 108, the tensile stress layer imparts a compressive stress to the PN junction 102 along the current flow direction 108.

[0068] In this example, the tensile stressed layer 106-1 comprises a biaxial tensile stressed layer that imparts the tensile stress along two axes that are both parallel to the plane of the surface of the semiconductor material 104. The biaxial tensile stressed layer may comprise a Silicon Nitride layer. A tensile stressed silicon nitride layer can be deposited, for example, by Low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition from reactants including dichlorosilane and ammonia. The deposition conditions, reactants, and reactant flows can be adjusted to desired stress value. In other examples, the tensile stressed layer 106-1 may comprise a uniaxial tensile stressed layer that imparts the tensile stress along a single axis parallel to the plane of the surface of the semiconductor material 104.

[0069] As illustrated, the PN junction 102 is formed at the top surface of the semiconductor material 104, with the N-type layer 110 formed in the semiconductor material 104 and the P-type layer 112 formed on top of the N-type layer 110 with the top surface of the P-type layer 112 forming the top surface of the semiconductor material 104. The stress-inducing layer 116-1 is formed/deposited on top of the P-type layer 112/top surface of the semiconductor material 104.

[0070] In some examples, one or more dimensions (thickness/depth, area, width, length etc) of the stress-inducing layer/region 106-1 may be selected to control the value of the compressive stress along the current direction 108 in the PN junction 102.

[0071] FIGS. 2A to 2E illustrate an example process for forming the Zener diode of FIG. 1A. Features of FIGS. 2A to 2E that are also present in FIGS. 1a-1C have been given corresponding numbers in the 200 series and will not necessarily be described again here.

[0072] In a first stage, illustrated in FIG. 2A, a first N-type region, NW, 210 and a second N-type region, NW2, are formed in a semiconductor material 204. In this example, the semiconductor material 204 comprises a P-type Silicon epitaxial substrate, P-epi. The first N-type region 210 corresponds to the N-type region of the PN junction and in this example comprises a N-Well region formed by heavy N-type implantation/doping (e.g. Phosphorous implantation). The second N-type region, NW2, comprises a lighter doped N-type region for cathode coupling. The different first and second N-type regions may be formed by suitable known masking and implantation steps.

[0073] In a second stage illustrated in FIG. 2B, the semiconductor material 204 is implanted with P-type material to form the P-type region, PW, 212 of the PN junction. In this example, the P-type region comprises a P-Well region formed by heavy P-type implantation/doping (e.g. Boron implantation). As with the first stage, formation of the P-type region may be performed using known masking and implantation steps.

[0074] The doping level of the P-type region 212, the first N-type region 212 and the second N-type region may respectively comprise 10.sup.19-10.sup.20 cm.sup.3, 10.sup.18-10.sup.19 cm.sup.3 and 10.sup.17-10.sup.18 cm.sup.3.

[0075] In a third stage, illustrated in FIG. 2C, the stress-inducing layer 206 is deposited on a surface of the semiconductor material 204. In some examples, the stress-inducing layer 206 may be deposited directly on the surface of the semiconductor material 204.

[0076] In other examples, like the example illustrated, the stress-inducing layer 206 may be deposited indirectly on the surface of the semiconductor material 204 with an intervening layer positioned between the stress-inducing layer 206 and the top surface of the semiconductor material 204. In this example, a silicon oxide layer 216 is deposited on the surface of the semiconductor material 204 prior to depositing the stress-inducing layer 206. The oxide layer 216 provides a dielectric barrier on top of the doped semiconductor material 204. In this example, the stress-inducing layer 206 comprises a biaxially tensile stressed layer and in particular a nitride layer, such as Silicon Nitride. The stress-inducing layer 206 may comprise a thickness of 10 nm or greater.

[0077] In a fourth stage, illustrated in FIG. 2D, heavily doped P-type contact regions, P+, are formed in the P-type region 212 and heavily doped N-type contact regions, N+, are formed in the second N-type region, NW2. Windows are etched in the silicon oxide layer 216 prior to implantation with the corresponding dopant material to form the heavily doped contact regions N+, P+. Known masking and implantation techniques may be used to form the heavily doped contact regions, N+, P+.

[0078] In a fifth stage, illustrated in FIG. 2E, an insulating layer 218 is deposited over the semiconductor material 204. In this example the insulating layer comprises Tetraethyl Orthosilicate (TEOS). Openings are etched in the TEOS in line with, and down to the surface of, the heavily doped contact regions, N+, P+. The openings are filled with a metal (e.g. Copper, Gold etc) to create contacts 220 for the Zener diode. In this example, the Zener diode has structural symmetry about an axis along the current flow direction, such that the heavily doped N-type contact region, N+, heavily doped P-type region, P+, and corresponding metal contacts 220 form respective ring regions and contacts. In other words, there is one anode ring contact coupled to the ring structured heavily doped P-type region, P+, and one cathode ring contact coupled to the ring structured heavily doped N-type region, N+.

[0079] Returning to FIG. 1B, a second example Zener diode 100 is illustrated according to an embodiment of the present disclosure.

[0080] In this example, the PN junction 102 is formed laterally in the semiconductor material 104. The N-type region 110 is positioned adjacent to the P-type region 112 (in the same layer) and the interface 114 of the PN junction 102 is perpendicular to the top surface of the semiconductor material 104. As a result, the current flow direction 108 is parallel to the (XZ) plane of the top-surface of the semiconductor material 104.

[0081] The one or more stress-inducing regions 106-1, 106-2 may comprise either or both of: a first stress-inducing region 106-1 adjacent to the P-type region 112 (and at an opposite side to the N-type region 110); and (ii) a second stress-inducing region 106-2 adjacent to the N-type region 110 (and at an opposite side to the P-type region 112). In the example, shown, the PN junction 102 is formed between a first stress-inducing region 106-1 and a second stress-inducing region 106-2.

[0082] In this example, the one or more stress-inducing regions 106-1, 106-2 comprise shallow trench isolation (STI) features. STI is a feature used in ICs to prevent electric current leakage between adjacent semiconductor device components. They are typically formed by etching a trench in the semiconductor material 104 and depositing a dielectric such as silicon dioxide into the trench. Due to different mechanical properties of oxide and silicon, compressive stress can develop laterally along the current flow direction 108. STI features can exhibit residual thermal stress following the fabrication process (due to a difference in thermal expansion coefficient between the semiconductor material 104 and the dielectric material). The STI features may impart the residual thermal stress in a lateral (X-axis) direction parallel to the (XZ) plane of the surface of the semiconductor material 104. In this way, the STI features can act as stress-inducing regions 106-1, 106-2 and impart compressive stress on the PN junction 102 in the current flow direction 108.

[0083] In some examples, a separation of the first stress-inducing region 106-1 and the second stress-inducing region 106-2 may be selected to control a value of the compressive stress along the current direction 108 in the PN junction 102. In some examples, one or more dimensions (thickness/depth, area, width, length etc) of the one or more stress-inducing regions 106-1, 106-2 may be selected to control the value of the compressive stress along the current direction 108 in the PN junction 102.

[0084] FIG. 1C illustrates a further example Zener diode 100 according to an embodiment of the present disclosure. The Zener diode has a lateral structure similar to that of FIG. 1B, however, the structure also has circular symmetry about a vertical (Y) axis as illustrated by the plan view in the lower half of the figure.

[0085] The PN junction 102 comprises a P-type region 112 surrounded by a N-type region 110 within a junction layer of the semiconductor material 104. The junction layer extends in a (XZ) plane parallel to the (XZ) plane of the top surface of the semiconductor material 104. The interface 114 between the P-type region 112 and the N-type region 110 is perpendicular to the surface of the semiconductor material 104 and extends circumferentially around the P-type region 112. The current flow direction 108 is perpendicular to the interface 114 and extends radially from the centre of the P-type region 112.

[0086] The PN junction 102 is surrounded by a stress-inducing region 106-1. In other words, the N-type region 110 is surrounded by the stress-inducing region 106-1. The stress-inducing region 106-1 imparts compressive stress to compress the PN junction 102 in a radial direction towards the centre of the P-type region 112. In this way, the stress-inducing region 106-1 imparts compressive stress in the current flow direction 108.

[0087] In this example, the P-type region 112 is surrounded by the N-type 110 region, however in other examples, the N-type region 110 may be surrounded by the P-type region 112. In some examples, the diode 100 may comprise a lower level of rotational symmetry than circular symmetry, for example, order 8, order 6, order 4 or order 2 rotational symmetry. For example, the P-type region 112, N-type region 110 and stress-inducing region 106-1 may have a rectangular structure when viewed from above.

[0088] In some examples, one or more of: the radius of the P-type region 112; the radius of the N-type region 110; and the radius of the stress-inducing region 106-1 may be selected to control a value of the compressive stress in the current flow direction 108 within the PN junction 102. In some examples, the depth or width of the stress-inducing region 106-1 may be selected to control the value of the compressive stress in the current flow direction 108 within the PN junction 102.

[0089] FIGS. 3A to 3D illustrate an example process for forming the Zener diode of FIGS. 1B and 1C. Features of FIGS. 3A to 3D that are also present in FIGS. 1A-1C and 2A-2E have been given corresponding numbers in the 300 series and will not necessarily be described again here.

[0090] In a first stage, illustrated in FIG. 3A, a N-type region, N, is formed in a semiconductor material 304. In this example, the semiconductor material 304 comprises a P-type Silicon epitaxial substrate, P-epi. A portion of the N-type region, N, will form the N-type region 310 of the PN junction 302 and in this example comprises a N-Well region formed by heavy N-type implantation/doping (e.g. Phosphorous implantation). The N-type region, N, may be formed by suitable known masking and implantation steps.

[0091] In a second stage, illustrated in FIG. 2B, one or more stress-inducing regions 306-1, 306-2 are formed in the semiconductor material 204. In this example, the stress-inducing regions 306-1, 306-2 are formed as STI features by etching a trench in the semiconductor material 304 and depositing a dielectric material such as Silicon Dioxide in the trench. The portion of the N-type region between a first stress-inducing region 306-1 and a second stress-inducing region 306-2 forms the N-type region 310 of the PN junction 302.

[0092] In a third stage, illustrated in FIG. 3C, a silicon oxide layer 316 is deposited on the surface of the semiconductor material 304. The oxide layer 316 provides a dielectric barrier on top of the doped semiconductor material 304. Following deposition of the oxide layer 316, a mask layer 322 is deposited on the oxide layer, so that a portion of the N-type region 310 between the STI regions 306-1, 306-2 is partially exposed. In this example the mask layer 322 comprises a nitride layer.

[0093] In a fourth stage, illustrated in FIG. 3D, a heavily doped P-type contact region, P+, and a heavily doped N-type contact region, N+, are formed in the N-type region, N, Windows may be etched in the silicon oxide layer 316 prior to implantation with the corresponding dopant material to form the heavily doped contact regions N+, P+. Known masking and implantation techniques may be used to form the heavily doped contact regions, N+, P+. The P-type contact region, P+, is formed by implanting P-type dopants in the N-type region, N, between the first and second STI regions 306-1, 306-2. In this way, the PN junction 302 is formed between the first and second stress-inducing regions 306-1, 306-2 and the stress-inducing regions impart a compressive stress in the PN junction 302 in the current flow direction. A TEOS layer 318 is deposited over the semiconductor material 304 and metal contacts 320 are formed as described above.

[0094] FIG. 4 illustrates a method 430 of manufacturing a Zener diode according to an embodiment of the present disclosure.

[0095] A first step 432 comprises providing a semiconductor material. A second step 434 comprises forming a PN junction in the semiconductor material. A third step 436 comprises forming one or more stress-inducing regions in or on the semiconductor material, wherein the one or more stress-inducing regions are configured to impart a compressive stress in the PN junction along a current flow direction of the PN junction.

[0096] There now follows a description of the theory underlying the improvement in Zener diode performance arising from the compressive stress in the current flow direction.

[0097] FIGS. 5A and 5B illustrate the effects of tensile stress and compressive stress on the performance of a PN junction.

[0098] FIG. 5A illustrates a change in breakdown voltage 546 in response to the application of compressive stress along the current flow direction 508 of a PN junction 502. The PN junction 502 is formed at a top surface of a semiconductor material 504. Force is then applied to bend the semiconductor material into a n-shape. This results in tensile stress (illustrated by arrows 511) on the PN-junction 502 in a lateral direction i.e. parallel to the XZ plane of the top surface. The tensile lateral stress 511 results in compressive stress 507 in the current flow direction 508 of the PN junction 502.

[0099] The plot illustrates the measured increase in breakdown voltage 544 resulting from this increase in compressive stress 507 along the current flow direction 508.

[0100] FIG. 5B illustrates a change in breakdown voltage 544 in response to the application of tensile stress along the current flow direction 508 of a PN junction 502. The PN junction 502 is formed at a top surface of a semiconductor material 504. Force is then applied to bend the semiconductor material into a U-shape. This results in compressive stress (illustrated by arrows 540) on the PN-junction in a lateral direction i.e. parallel to the plane of the top surface. The compressive lateral stress 540 results in tensile stress 542 in the current flow direction 508 of the PN junction.

[0101] The plot illustrates the measured decrease in breakdown voltage 546 resulting from this increase in tensile stress along the current flow direction 508.

[0102] FIG. 6 illustrates a simulation of the variation in Zener breakdown voltage in dependence of stress along the current flow direction. Positive values of stress correspond to tensile strain and negative values correspond to compressive strain.

[0103] A nominally unstressed region 646 of the plot has a relatively steep gradient illustrating that nominally unstressed Zener diodes are subject to relatively high variations in breakdown voltage when subject to stress along the current flow direction of the PN junction.

[0104] At a certain compressive stress, the plot reaches a peak region 648 and shows a smaller sensitivity to a variation in stress resulting from external or packaging stress. The disclosed Zener diodes comprise one or more stress-inducing regions for imparting compressive stress along the current flow direction of the PN junction to move the Zener diode to this region 648 of reduced breakdown voltage sensitivity. As a result, the disclosed Zener diodes advantageously exhibit a reduced breakdown voltage sensitivity to external stress and packaging stress.

[0105] The shape of the plot of FIG. 6 can be explained as follows. The breakdown voltage relates inversely to the tunnel rate, , of electrons, which can be described by the equation:

[00001]$=\exp \left(-\frac{4}{3}\frac{\sqrt{2m*}}{q}\frac{E_g^{3/2}}{}\right)$

[0106] Here, q is the electron charge, h is the reduced Planck constant, is a correction factor for the Band-gap, E.sub.g, of the semiconductor material and m* is the tunnel mass of the electron. The tunnel rate, , increases with both increasing tunnel mass, m*, and increasing band-gap, E.sub.g. The tunnel mass may be approximated as the effective mass of the electron at the bottom of the conduction band, m.sub.c. Due to anisotropy in the Silicon conduction band, the conduction mass, m.sub.c, increases while the band gap, E.sub.g, decreases when compressive stress is applied along the current flow direction. This leads to the cross-over point/peak 648 in the plot (at lower values of compressive stress, the increase in the conduction mass, m.sub.c, dominates, at higher values, the decrease in band gap energy, E.sub.g, dominates). For the application of tensile stress along the current flow direction, both the conduction mass, m.sub.c, and the bandgap, E.sub.g, decrease leading to an increase in tunnelling rate and lower breakdown voltage.

[0107] In view of the above, the one or more stress-inducing regions of the disclosed Zener diodes may impart compressive stress along the current flow direction of the PN junction, such that the breakdown voltage of the Zener diode has a reduced sensitivity to a variation in stress along the current flow direction (relative to the unstressed state). In other words, the value of the compressive stress is selected to reduce a derivative of the breakdown voltage with respect to the compressive stress. In some examples, the compressive stress may be between 150 MPa and 200 MPa.

[0108] The present disclosure provides example Zener diodes incorporating built-in compressive stress along a current flow direction that provides for reduced sensitivity of the Zener breakdown voltage to package stress or external stress. This is in contrast to conventional Zener diode design in which stress within the diode and PN junction is typically minimized.

[0109] The instructions and/or flowchart steps in the above figures can be executed in any order, unless a specific order is explicitly stated. Also, those skilled in the art will recognize that while one example set of instructions/method has been discussed, the material in this specification can be combined in a variety of ways to yield other examples as well, and are to be understood within a context provided by this detailed description.

[0110] In some example embodiments the set of instructions/method steps described above are implemented as functional and software instructions embodied as a set of executable instructions which are effected on a computer or machine which is programmed with and controlled by said executable instructions. Such instructions are loaded for execution on a processor (such as one or more CPUs). The term processor includes microprocessors, microcontrollers, processor modules or subsystems (including one or more microprocessors or microcontrollers), or other control or computing devices. A processor can refer to a single component or to plural components.

[0111] In other examples, the set of instructions/methods illustrated herein and data and instructions associated therewith are stored in respective storage devices, which are implemented as one or more non-transient machine or computer-readable or computer-usable storage media or mediums. Such computer-readable or computer usable storage medium or media is (are) considered to be part of an article (or article of manufacture). An article or article of manufacture can refer to any manufactured single component or multiple components. The non-transient machine or computer usable media or mediums as defined herein excludes signals, but such media or mediums may be capable of receiving and processing information from signals and/or other transient mediums.

[0112] Example embodiments of the material discussed in this specification can be implemented in whole or in part through network, computer, or data based devices and/or services. These may include cloud, internet, intranet, mobile, desktop, processor, look-up table, microcontroller, consumer equipment, infrastructure, or other enabling devices and services. As may be used herein and in the claims, the following non-exclusive definitions are provided.

[0113] In one example, one or more instructions or steps discussed herein are automated. The terms automated or automatically (and like variations thereof) mean controlled operation of an apparatus, system, and/or process using computers and/or mechanical/electrical devices without the necessity of human intervention, observation, effort and/or decision.

[0114] It will be appreciated that any components said to be coupled may be coupled or connected either directly or indirectly. In the case of indirect coupling, additional components may be located between the two components that are said to be coupled.

[0115] In this specification, example embodiments have been presented in terms of a selected set of details. However, a person of ordinary skill in the art would understand that many other example embodiments may be practiced which include a different selected set of these details. It is intended that the following claims cover all possible example embodiments.