CIRCUIT AND CONTROL METHOD FOR PREVENTING FALSE TURN-ON OF SEMICONDUCTOR SWITCHING DEVICE

Abstract

A circuit for preventing false turn-on of a semiconductor switching device includes an active clamp circuit, a control circuit, a power amplifier circuit, and a suppression circuit. The control circuit is coupled to an input of the power amplifier circuit. An output of the power amplifier circuit is coupled to a gate of the semiconductor switching device. The active clamp circuit is configured to operate within a preset period when a voltage between the first end of the semiconductor switching device and a second end of the semiconductor switching device is greater than a preset voltage. The suppression circuit includes a controllable switch, which is configured to turn on after the operation of the active clamp circuit is completed, such that potential at the input of the power amplifier circuit is clamped to a fixed potential.

Claims

1. A circuit for preventing false turn-on of a semiconductor switching device, comprising: a power amplifier circuit; a control circuit, electrically coupled to an input end of the power amplifier circuit; a semiconductor switching device, wherein the gate of the semiconductor switching device is electrically coupled to an output end of the power amplifier circuit; an active clamp circuit having a first end and a second end, wherein the first end of the active clamp circuit is electrically connected to a first end of the semiconductor switching device, and the second end of the active clamp circuit is electrically connected to the input end of the power amplifier circuit, and the active clamp circuit is configured to operate within a preset period from a time point when a voltage between the first end of the semiconductor switching device and a second end of the semiconductor switching device is greater than a preset voltage; and a suppression circuit, wherein a first end of the suppression circuit is electrically connected to the control circuit, and a second end of the suppression circuit is electrically connected to the input end of the power amplifier circuit, and a third end of the suppression circuit is electrically connected to a node having a fixed potential; wherein the suppression circuit further comprises a controllable switch, and the controllable switch is configured to turn on after operation of the active clamp circuit is completed, such that the input end of the power amplifier circuit is clamped to the fixed potential.

2. The circuit according to claim 1, further comprising: an input resistor electrically coupled between the control circuit and the input end of the power amplifier circuit; and a driving resistor electrically coupled between the output end of the power amplifier circuit and the gate of the semiconductor switching device.

3. The circuit according to claim 1, wherein the controllable switch is configured to turn off when the control circuit outputs a high level or a gate voltage of the semiconductor switching device is greater than a preset gate voltage.

4. The circuit according to claim 1, wherein the controllable switch is configured to turn on when the operation of the active clamp circuit is completed and a gate voltage of the semiconductor switching device is equal to a preset gate voltage, wherein the preset gate voltage is less than a gate voltage threshold of the semiconductor switching device.

5. The circuit according to claim 1, wherein the controllable switch is configured to turn off within the preset period.

6. The circuit according to claim 1, wherein a fourth end of the suppression circuit is coupled to the gate of the semiconductor switching device and receives a gate voltage of the semiconductor switching device.

7. The circuit according to claim 6, wherein the suppression circuit further comprises: a first diode, wherein an anode of the first diode is coupled to the first end of the suppression circuit, and a cathode of the first diode is coupled to a gate of the controllable switch; a second diode, wherein an anode of the second diode is coupled to the second end of the suppression circuit, and a cathode of the second diode is coupled to a first end of the controllable switch; a first capacitor coupled between the first end of the controllable switch and the gate of the controllable switch; a first resistor; and a third diode, wherein the first resistor and the third diode are connected in series and coupled between the gate of the controllable switch and the fourth end of the suppression circuit; wherein a second end of the controllable switch is coupled to the third end of the suppression circuit.

8. The circuit according to claim 7, wherein the first capacitor is a parasitic capacitor between the first end of the controllable switch and the gate of the controllable switch.

9. The circuit according to claim 1, wherein a gate of the controllable switch is connected to the first end of the suppression circuit, a first end of the controllable switch is connected to the second end of the suppression circuit, and a second end of the controllable switch is coupled to the third end of the suppression circuit; and the control circuit is configured to control the controllable switch to turn on or turn off according to a gate voltage of the semiconductor switching device and a control signal outputted by the control circuit.

10. The circuit according to claim 1, wherein the suppression circuit comprises: a fourth diode, wherein an anode of the fourth diode is coupled to the first end of the suppression circuit, and a cathode of the fourth diode is coupled to a gate of the controllable switch; a fifth diode, wherein an anode of the fifth diode is coupled to the second end of the suppression circuit, and a cathode of the fifth diode is coupled to a first end of the controllable switch; a second resistor; a sixth diode, wherein the sixth diode and the second resistor are connected in series and coupled between the gate of the controllable switch and the anode of the fourth diode; and a second capacitor, wherein the second capacitor is coupled between the first end of the controllable switch and the gate of the controllable switch; wherein a second end of the controllable switch is coupled to the third end of the suppression circuit.

11. The circuit according to claim 1, wherein the fixed potential is less than a gate voltage threshold of the semiconductor switching device.

12. The circuit according to claim 1, wherein the controllable switch is a PNP-type transistor; and the first end of the controllable switch is an emitter of the PNP-type transistor, and the second end of the controllable switch is a collector of the PNP-type transistor.

13. The circuit according to claim 1, wherein the active clamp circuit comprises a seventh diode, a plurality of TVS Diodes, at least one third capacitor and a fourth resistor; the plurality of TVS Diodes, the seventh diode and the fourth resistor are connected in series between the first end of the semiconductor switching device and the input end of the power amplifier circuit, wherein the plurality of TVS Diodes are arranged in a same direction and opposite to a direction of the seventh diode, and at least one of the plurality of TVS Diodes is connected in parallel to the at least one third capacitor.

14. A control method for preventing false turn-on of a semiconductor switching device, comprising: providing a circuit architecture comprising an active clamp circuit, a control circuit, a power amplifier circuit and a suppression circuit; wherein the control circuit is coupled to an input end of the power amplifier circuit; an output end of the power amplifier circuit is coupled to a gate of the semiconductor switching device; a first end of the active clamp circuit is connected to a first end of the semiconductor switching device, and a second end of the active clamp circuit is connected to the input end of the power amplifier circuit; the suppression circuit comprises a controllable switch; a first end of the suppression circuit is connected to the control circuit, a second end of the suppression circuit is connected to the input end of the power amplifier circuit, and a third end of the suppression circuit is connected to a fixed potential point; determining a preset period during which the active clamp circuit operates according to a voltage between the first end of the semiconductor switching device and a second end of the semiconductor switching device; and turning on the controllable switch after operation of the active clamp circuit is completed, such that the input end of the power amplifier circuit is clamped to a fixed electrical potential.

15. The control method according to claim 14, wherein the fixed electrical potential is less than a gate voltage threshold of the semiconductor switching device.

16. The control method according to claim 14, wherein when the control circuit outputs a high level or a gate voltage of the semiconductor switching device is greater than a preset gate voltage, the controllable switch is turned off.

17. The control method according to claim 14, wherein when the operation of the active clamp circuit is completed and a gate voltage of the semiconductor switching device is a preset gate voltage, the controllable switch is turned on.

18. The control method according to claim 14, wherein the controllable switch is turned off within the preset period during which the active clamp circuit operates.

19. The control method according to claim 14, wherein the active clamp circuit operates from a first time to a second time, and the first time is defined as the time point when a voltage between the first end and the second end of the semiconductor switching device is greater than a preset voltage, and the second time is defined as the time point when a gate voltage of the semiconductor switching device is a preset gate voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG. 1 is a schematic diagram of the conventional active clamp circuit.

[0025] FIG. 2 is a schematic diagram of a displacement current feedback type active clamp circuit.

[0026] FIG. 3 is a schematic diagram of a first embodiment of a circuit for preventing false turn-on of a semiconductor switching device according to the present disclosure.

[0027] FIG. 4 is a control timing diagram in FIG. 3.

[0028] FIG. 5 is a schematic diagram of a second embodiment of a circuit for preventing false turn-on of a semiconductor switching device according to the present disclosure.

[0029] FIG. 6 is a control timing diagram in FIG. 5.

[0030] FIG. 7 is a schematic diagram of one embodiment of a suppression circuit according to the present disclosure.

[0031] FIG. 8 is a schematic diagram of a third embodiment of a circuit for preventing false turn-on of a semiconductor switching device according to the present disclosure.

[0032] FIG. 9 is a schematic diagram of one embodiment of a suppression circuit according to the present disclosure.

[0033] FIG. 10 is a flow chart of a method for preventing false turn-on of a semiconductor switching device according to the present disclosure.

DETAILED EMBODIMENTS OF THE INVENTION

[0034] Hereinafter the technical solution of the invention is described in detail with reference to the accompanying drawings and the detailed embodiments, to further understand the object, solution, and effect of the invention, rather than to limit the protection scope of the appended claims of the invention.

[0035] FIG. 3 is a schematic diagram of a first embodiment of a circuit for preventing false turn-on of a semiconductor switching device. As shown in FIG. 3, in the exemplary embodiment, the circuit includes an active clamp circuit 31, a control circuit 32, a power amplifier circuit 33, and a suppression circuit 34.

[0036] In detail, the control circuit 32 is coupled to an input end of the power amplifier circuit 33. An output end of the power amplifier circuit 33 is coupled to a gate 351 of the semiconductor switching device. For example, the semiconductor switching device may be IGBT. A first end of the active clamp circuit 31 is connected to a first end 352 of the semiconductor switching device, a second end of the active clamp circuit 31 is connected to the input end of the power amplifier circuit 33, and the active clamp circuit 31 is configured to operate within a preset period from a time point when a voltage between the first end 352 of the semiconductor switching device and a second end 353 of the semiconductor switching device is greater than a preset voltage. The suppression circuit 34 includes a controllable switch 341. A first end 342 of the suppression circuit 34 is connected to the control circuit 32, a second end 343 of the suppression circuit 34 is connected to the input end of the power amplifier circuit 33, and a third end 344 of the suppression circuit 34 is connected to the node 36 having a fixed potential. Further, the controllable switch 341 is configured to turn on after operation of the active clamp circuit 31 is completed, such that the input end of the power amplifier circuit 33 is clamped to the fixed potential.

[0037] As can be seen, after operation of the active clamp circuit 31 is completed, i.e., after the active clamp circuit 31 completes voltage clamping, by controlling the controllable switch of the suppression circuit 34 to turn on, the input end of the power amplifier circuit 33 is clamped to the fixed potential so as to limit a gate voltage at the gate 351 of the semiconductor switching device, such that the active clamp circuit 31 is disabled after the semiconductor switching device is completely turned off, thereby blocking a transmission path of an interference signal. As such, the problem of false turn-on of the semiconductor switching device is solved without affecting the normal operation of the power amplifier circuit 33 and the active clamp circuit 31.

[0038] As shown in FIG. 3, the circuit further includes an input resistor 37 and a driving resistor 38. The input resistor 37 is coupled between the control circuit 32 and the input end of the power amplifier circuit 33. The driving resistor 38 is coupled between the output end of the power amplifier circuit 33 and the gate 351 of the semiconductor switching device.

[0039] As shown in FIG. 3, the suppression circuit 34 further includes a delay module 345. The delay module 345 is coupled to the first end 342 of the suppression circuit 34 and the controllable switch 341, respectively, and the delay module is used to receive a control signal, which may be a Pulse Width Modulation (PWM) signal, outputted by the control circuit 32, and to control the controllable switch 341 to turn on after a preset delay time, such that the input end of the power amplifier circuit 33 may be clamped to the fixed potential, thereby blocking a transmission path of an interference signal. As such, the problem of false turn-on of the semiconductor switching device is solved without affecting the normal operation of the semiconductor switching device and the active clamp circuit 31.

[0040] FIG. 4 is a control timing diagram in FIG. 3. In FIG. 4, a longitudinal axis represents a voltage, a horizontal axis represents a time t, PWM represents a control signal of the control circuit 32, and a line Vge represents a gate voltage of the semiconductor switching device. As shown in FIG. 4, in phase 1, the PWM signal outputted by the control circuit 32 is at a high level, and the controllable switch 341 of the suppression circuit 34 is in a non-conductive state according to the high level, while the semiconductor switching device is turned on and works normally. In phase 2, the PWM signal outputted by the control circuit 32 is at a low level, and the delay module 345 works. When a voltage between the first end 352 and the second end 353 of the semiconductor switching device is greater than a preset voltage, the active clamp circuit 31 operates, and an electric charge flowing out of the first end 352 of the semiconductor switching device is injected into the gate 351 of the semiconductor switching device through the active clamp circuit 31. The gate voltage at the gate 351 of the semiconductor switching device increases, such that the gate voltage is greater than a preset gate voltage and the semiconductor switching device is delayed to turn off, thereby limiting a voltage peak between the first end 352 and the second end 353 of the semiconductor switching device, and allowing the semiconductor switching device not to be damaged. The preset period during the operation of the active clamp circuit 31 starts at a time point when the voltage between the first end 352 and the second end 353 of the semiconductor switching device is greater than the preset voltage, and ends at a time point when the operation of the active clamp circuit 31 is completed. In phase 3, after operation of the active clamp circuit 31 is completed, the PWM signal outputted by the control circuit 32 is still at a low level, and operation of the delay module 345 is completed, so the gate of the semiconductor switching device is at a preset gate voltage. The preset gate voltage may be less than a gate voltage threshold of the semiconductor switching device so that the controllable switch 341 turns on, and the input end of the power amplifier circuit 33 is clamped to the fixed potential, thereby blocking the interference signal from affecting the turn-off of the semiconductor switching device through the active clamp circuit, and ensuring reliable turn-off of the semiconductor switching device. The fixed potential may be lower than the gate voltage threshold of the semiconductor switching device. For example, when the gate voltage threshold is 6 Volt, the fixed electrical potential is less than 6 Volt and may be any voltage between 0 and −20 Volt. It shall be noted that a preset time delayed by the delay module 345 corresponds to a period in phase 2, i.e., a preset delay time starts at a time point when the PWM signal is converted from the high level into the low level and ends at a time point when the operation of the active clamp circuit is completed.

[0041] In this solution, the preset delay time shall be designed by an operation time of the active clamp circuit in the worst working conditions. Since a difference between the operation times of the active clamp circuit in different working conditions may amount to several microseconds, and issues of precision and temperature drift of the components shall be taken into consideration, the preset delay time is far larger than the operation time of the active clamp circuit, such that the suppression circuit cannot work immediately after operation of the active clamp circuit is completed. The solution is complicated in design, while also bringing a protection blind zone, and reducing reliability. It shall be further improved.

[0042] FIG. 9 is a schematic diagram of one embodiment of an interference suppression circuit according to the present disclosure. As shown in FIG. 9, a suppression circuit 94 includes a fourth diode 901, a fifth diode 902, a sixth diode 903, a second resistor 904, a third resistor 906 and a second capacitor 905. An anode of the fourth diode 901 is coupled to the first end of the suppression circuit 94, and a cathode of the fourth diode 901 is coupled to a gate of the controllable switch 941. An anode of the fifth diode 902 is coupled to the second end of the suppression circuit 94, and a cathode of the fifth diode 902 is coupled to a first end of the controllable switch 941. The sixth diode 903 and the second resistor 904 are coupled in series between the gate of the controllable switch 941 and the anode of the fourth diode 901. The second capacitor 905 is coupled between the first end of the controllable switch 941 and the gate of the controllable switch 941. The third resistor 906 is connected between the cathode of the fifth diode 902 and the cathode of the fourth diode 901. A second end of the controllable switch 941 is coupled to the third end of the suppression circuit 94, and the third end of the suppression circuit 94 is connected to the node 96 having a fixed potential.

[0043] As shown in FIG. 9, when the PWM signal is at a high level, the fourth diode 901 is turned on, a voltage potential at the gate of the controllable switch 941 is pulled up, such that the controllable switch 941 is turned off, and the PWM signal is amplified by the power amplifier circuit 93 and the amplified PWM signal drives the semiconductor switching device to turn on. When the PWM signal is at a low level, if a voltage between the first end and the second end of the semiconductor switching device is greater than a preset voltage, the active clamp circuit operates, and the fifth diode 902 and the sixth diode 903 are turned on, and the second capacitor 905 is discharged through the second resistor 904. Accordingly, the controllable switch 941 is in a non-conductive state, and current flows into the gate of the semiconductor switching device, such that a gate voltage of the semiconductor switching device increases, and the semiconductor switching device is turned on. After the operation of the active clamp circuit is completed and the PWM signal is still at a low level, once an interference signal is injected into the second capacitor 905 through the active clamp circuit to charge the second capacitor 905 reversely, such that a gate voltage of the controllable switch 941 reaches a gate voltage threshold, the controllable switch 941 is turned on, and the input end of the power amplifier circuit 93 is clamped to the fixed potential.

[0044] In the embodiment of the present disclosure, the delay module includes the second resistor 904 and the second capacitor 905, and when the PWM signal is at a low level, the delay module produces a preset delay time to ensure that the controllable switch 941 is turned on after operation of the active clamp circuit is completed.

[0045] In the embodiment of the present disclosure, the fixed potential is less than a gate voltage threshold of the semiconductor switching device, such that the input end of the power amplifier circuit 93 is clamped to the fixed potential, thereby preventing false turn-on of the semiconductor switching device.

[0046] As shown in FIG. 9, in one embodiment of the present disclosure, the controllable switch 941 may be a PNP-type transistor, and the first end of the controllable switch 941 is an emitter of the PNP-type transistor, and the second end of the controllable switch 941 is a collector of the PNP-type transistor.

[0047] FIG. 5 is a schematic diagram of a second embodiment of a circuit for preventing false turn-on of a semiconductor switching device. As shown in FIG. 5, in the exemplary embodiment, the circuit architecture includes an active clamp circuit 51, a control circuit 52, a power amplifier circuit 53, and a suppression circuit 54.

[0048] In detail, the control circuit 52 is coupled to an input end of the power amplifier circuit 53. An output end of the power amplifier circuit 53 is coupled to a gate 551 of the semiconductor switching device. A first end of the active clamp circuit 51 is connected to a first end 552 of the semiconductor switching device, a second end of the active clamp circuit 51 is connected to the input end of the power amplifier circuit 53. The active clamp circuit 51 is configured to operate within a preset period from a time point when a voltage between the first end 552 of the semiconductor switching device and a second end 553 of the semiconductor switching device is greater than a preset voltage. The suppression circuit 54 includes a controllable switch 541. A first end 542 of the suppression circuit 54 is connected to the control circuit 52, a second end 543 of the suppression circuit 54 is connected to the input end of the power amplifier circuit 53, and a third end 544 of the suppression circuit 54 is connected to the node 56 having a fixed potential, and a fourth end 545 of the suppression circuit 54 is connected to the gate 551 of the semiconductor switching device. Further, the controllable switch 541 is configured to turn on after operation of the active clamp circuit 51 is completed, i.e., a gate voltage of the semiconductor switching device is a preset gate voltage, and the controllable switch 541 is turned on, such that the input end of the power amplifier circuit 53 is clamped to the fixed potential.

[0049] FIG. 6 is a control timing diagram in FIG. 5. In FIG. 6, a longitudinal axis represents a voltage, a horizontal axis represents a time t, PWM represents a control signal outputted by the control circuit 52, and a line Vge represents a gate voltage of the semiconductor switching device. As shown in FIG. 6, in phase 1, the PWM signal outputted by the control circuit 52 is at a high level, so the controllable switch 541 is in a non-conductive state according to the high level. In phase 2, the PWM signal outputted by the control circuit 52 is at a low level. When a voltage between the first end 552 and the second end 553 of the semiconductor switching device is greater than a preset voltage, the active clamp circuit 51 operates, so the gate voltage of the semiconductor switching device is greater than a preset gate voltage, and the controllable switch 541 is in a non-conductive state. In phase 3, operation of the active clamp circuit 51 is completed, and the PWM signal outputted by the control circuit 52 is still at a low level, so the gate of the semiconductor switching device is a preset gate voltage, the controllable switch 541 is controlled to turn on according to the preset gate voltage, and the input end of the power amplifier circuit 53 is clamped to the fixed potential. In addition, the preset gate voltage is less than a gate voltage threshold of the semiconductor switching device. A turn-on time point of the controllable switch can be automatically set according to an adjustable operation time of the active clamp circuit. And the delay time is nearly zero and greatly reduces a protection blind zone and improves reliability.

[0050] FIG. 7 is one embodiment of a suppression circuit according to the present disclosure. As shown in FIG. 7, in the exemplary embodiment, the circuit architecture includes an active clamp circuit 71, a control circuit 72, a power amplifier circuit 73 and a suppression circuit 74.

[0051] In detail, the control circuit 72 is coupled to an input end of the power amplifier circuit 73. An output end of the power amplifier circuit 73 is coupled to a gate 753 of the semiconductor switching device. A first end of the active clamp circuit 71 is connected to a first end 751 of the semiconductor switching device, a second end of the active clamp circuit 71 is connected to the input end B of the power amplifier circuit 73. The active clamp circuit 71 is configured to operate within a preset period from a time point when a voltage between the first end 751 of the semiconductor switching device and a second end 752 of the semiconductor switching device is greater than a preset voltage. The suppression circuit 74 further includes a controllable switch 741. A first end A of the suppression circuit 74 is connected to the control circuit 72, a second end of the suppression circuit is connected to the input end B of the power amplifier circuit 73, a third end of the suppression circuit 74 is connected to the node 742 having a fixed potential, and a fourth end of the suppression circuit 74 is connected to the gate 753 of the semiconductor switching device. The controllable switch 741 is configured to turn on after operation of the active clamp circuit 71 is completed, such that the input end B of the power amplifier circuit 73 is clamped to the fixed potential.

[0052] As can be seen, in the above embodiment, by use of the suppression circuit 74, the electrical potential at the input end B of the power amplifier circuit 73 is clamped to the fixed potential after operation of the active clamp circuit 71 is completed, thereby limiting a gate voltage at the gate 753 of the semiconductor switching device, and effectively preventing false turn-on of the semiconductor switching device.

[0053] As shown in FIG. 7, in another embodiment of the present disclosure, the circuit further includes an input resistor 76 and a driving resistor 77. The input resistor 76 is coupled between the control circuit 72 and the input end B of the power amplifier circuit 73. The driving resistor 77 is coupled between the output end of the power amplifier circuit 73 and the gate 753 of the semiconductor switching device.

[0054] Referring to FIGS. 6 and 7, the controllable switch 741 is configured to turn off when the control circuit 72 outputs a high level (phase 1), or the gate voltage of the semiconductor switching device is greater than a preset gate voltage (phase 2). Therefore, the controllable switch 741 is turned off in phase 1 and phase 2, and the suppression circuit 74 does not operate.

[0055] Referring to FIGS. 6 and 7, in another embodiment of the present disclosure, the controllable switch 741 is configured to turn on when the operation of the active clamp circuit 71 is completed and the gate voltage of the semiconductor switching device is a preset gate voltage (phase 3), and the preset gate voltage is less than a gate voltage threshold of the semiconductor switching device. As can be seen, in phase 3, the active clamp circuit 71 does not work, so false turn-on of the semiconductor switching device shall be prevented, the controllable switch 741 is turned on, the suppression circuit is put into use, and a voltage at the input end B is clamped to the fixed potential, thereby effectively preventing false turn-on of the semiconductor switching device.

[0056] Referring to FIG. 7, in another embodiment of the present disclosure, a fourth end of the suppression circuit 74 is electrically coupled to the gate of the semiconductor switching device and the junction node therebetween is labeled as C. The suppression circuit receives the gate voltage, such that determination of phase 2 in FIG. 6 is completed using the gate voltage.

[0057] Referring to FIG. 7, in another embodiment of the present disclosure, the suppression circuit 74 further includes a first diode 742, a second diode 743, a third diode 744, a first resistor 745 and a first capacitor 746. An anode of the first diode 742 is coupled to the first end of the suppression circuit 74, and a cathode of the first diode 742 is coupled to a gate of the controllable switch 741. An anode of the second diode 743 is coupled to the second end of the suppression circuit 74, and a cathode of the second diode 743 is coupled to a first end of the controllable switch 741. The first capacitor 746 is coupled between the first end of the controllable switch 741 and the gate of the controllable switch 741. The first resistor 745 and the third diode 744 are connected in series and then coupled between the gate of the controllable switch and the fourth end of the suppression circuit 74. A second end of the controllable switch 741 is coupled to the third end of the suppression circuit 74, and the third end of the suppression circuit 74 is connected to the node 742 having the fixed potential.

[0058] In another embodiment, the first capacitor 746 may be a parasitic capacitor between the first end of the controllable switch 741 and the gate of the controllable switch.

[0059] As shown in FIG. 7, in one embodiment of the present disclosure, the controllable switch 741 is a PNP-type transistor. Further, the first end of the controllable switch 741 is an emitter of the PNP-type transistor, and the second end of the controllable switch 741 is a collector of the PNP-type transistor.

[0060] As shown in FIG. 7, in one embodiment of the present disclosure, the active clamp circuit 71 includes a seventh diode 711, a plurality of TVS Diodes 712, at least one third capacitor 713, and a fourth resistor 714. The plurality of TVS Diodes 712, the seventh diode 711, and the fourth resistor 714 are connected in series between the first end 751 of the semiconductor switching device and the input end of the power amplifier circuit 73. The plurality of TVS Diodes 712 is arranged in the same direction, opposite to a direction of the seventh diode 711. And at least one of the plurality of TVS Diodes 712 is connected in parallel to the at least one third capacitor 713.

[0061] As shown in FIG. 7, when the controllable switch 741 is turned on, a potential at the input end B of the power amplifier circuit 73 is clamped to a low fixed potential (such as grounded potential), so a transmission path of flowing energy fed back by the active clamp circuit 71 to the gate is blocked. When the controllable switch 741 is turned off, the transmission path of flowing energy fed back by the active clamp circuit 71 to the gate is open again. Control timing of the circuit is shown in FIG. 6. In phase 1, the PWM signal is at a high level, so a potential at node A is higher than a potential at node B, such that a gate and an emitter of the controllable switch 741 are biased in reverse direction and the controllable switch 741 is turned off. In phase 2, during the operation of the active clamp circuit, the potential at node B is lower than the electrical potential of the gate 753 of the semiconductor switching device, and the gate and the emitter of the controllable switch 741 are biased in reverse direction and the controllable switch 741 is turned off. In phase 3, operation of the active clamp circuit is completed, and potentials of the base of the controllable switch 741 and the gate 753 of the semiconductor switching device are at a low level, so interfering energy is injected via the active clamp circuit, such that the electrical potential at the node B is increased instantly, and the base and the emitter of the controllable switch 741 are biased in position direction and the controllable switch 741 is turned on, thereby injecting interfering energy into the fixed potential to avoid false turn-on of the semiconductor switching device.

[0062] FIG. 8 is a schematic diagram of a third embodiment of a circuit for preventing false turn-on of a semiconductor switching device. In the exemplary embodiment, the circuit includes a fully-controlled switch Q. A gate of the fully-controlled switch Q is connected to a first end of the suppression circuit 84, and a first end of the fully-controlled switch Q is connected to a second end (a node B in the figure) of the suppression circuit 84, and a second end of the fully-controlled switch Q is coupled to a third end (a fixed potential node 86) of the suppression circuit 84. The control circuit 82 is configured to control the fully-controlled switch Q to turn on or turn off according to a working state of the active clamp circuit and a control signal outputted by the control circuit 82. In the phase during which the semiconductor switching device is turned on and the active clamp circuit operates, the control circuit 82 turns off the fully-controlled switch Q, and after operation of the active clamp circuit is completed, the control circuit 82 turns on the fully-controlled switch Q and pulls the electrical potential at the input end B of the power amplifier circuit 83 to a low potential. The control timing is shown in FIG. 6, and a specific control process is as follows: when the PWM signal outputted by the controller is at a high level, the controller sends a turn-off signal to the fully-controlled switch Q, and when the controller judges that the operation phase of the active clamp circuit is completed, the controller turns on the fully-controlled switch Q and disables the active clamp circuit. The signal for judging completion of the active clamp phase may be the gate voltage of the semiconductor switching device, and may also be other signals. If the gate voltage of the semiconductor switching device is used as a turn-on signal of the fully-controlled switch Q, it may be designed that when the gate voltage of the semiconductor switching device is less than a voltage b, the fully-controlled switch Q is turned on, where the value of b shall be set to avoid influence on the active clamp function. The lower the b value is, the less the influence on voltage clamping will be.

[0063] FIG. 10 is a flow chart of a method for preventing false turn-on of a semiconductor switching device. Referring to FIGS. 3 and 10, in the exemplary method, the control method may be realized by step 210 to step 230.

[0064] step 210, providing a circuit for preventing false turn-on of a semiconductor switching device. The circuit includes an active clamp circuit 31, a control circuit 32, a power amplifier circuit 33, and a suppression circuit 34. The control circuit 32 is coupled to an input of the power amplifier circuit 33. An output of the power amplifier circuit 33 is coupled to a gate 351 of the semiconductor switching device. A first end of the active clamp circuit 31 is connected to a first end 352 of the semiconductor switching device, and a second end of the active clamp circuit 31 is connected to the input of the power amplifier circuit 33. The suppression circuit 34 includes a controllable switch 341. A first end of the suppression circuit 34 is connected to the control circuit 32, a second end of the suppression circuit 34 is connected to the input of the power amplifier circuit 33, and a third end of the suppression circuit 34 is connected to the node 36 having a fixed potential.

[0065] step 220, determining a preset period during which the active clamp circuit operates according to a voltage between the first end of the semiconductor switching device and a second end of the semiconductor switching device; and

[0066] step 230, after the operation of the active clamp circuit is completed, turning on the controllable switch, so that the input of the power amplifier circuit is clamped to a fixed potential.

[0067] In one method embodiment, when the PWM signal outputted by the control circuit 32 is at a high level, the semiconductor switching device is turned on, and the controllable switch is turned off. When the PWM signal outputted by the control circuit 32 is converted from a high level into a low level, and the voltage between the first end of the semiconductor switching device and the second end of the semiconductor switching device is greater than a preset voltage, the active clamp circuit begins to operate.

[0068] As can be seen, in a period during which the PWM signal outputted by the control circuit 32 is at a low level and the active clamp circuit does not work, the electrical potential is clamped through the suppression circuit to block the gate of the semiconductor switching device from exceeding a gate voltage threshold, thereby preventing false turn-on.

[0069] In one method embodiment, the fixed potential is less than a gate voltage threshold of the semiconductor switching device.

[0070] In one method embodiment, when the control circuit outputs a high level, or a gate voltage of the semiconductor switching device is greater than a preset gate voltage, the controllable switch is turned off.

[0071] In one method embodiment, when the operation of the active clamp circuit is completed, and a gate voltage of the semiconductor switching device is a preset gate voltage, the controllable switch is turned on.

[0072] In one method embodiment, the controllable switch is turned off during the preset period when the active clamp circuit operates.

[0073] In one method embodiment, the operation of the active clamp circuit starts at the time point when a voltage between the first end and the second end of the semiconductor switching device is greater than a preset gate voltage, and ends at the time point when a gate voltage of the semiconductor switching device is the preset gate voltage.

[0074] As can be known, the present disclosure includes at least one of the following advantages:

[0075] 1. Suitable for semiconductor switching devices, and also suitable for applications of a small voltage margin and a fast switching speed, and effectively solves the interference problem of the gate drive of the semiconductor switching device.

[0076] 2. Suitable for a wide application, and the anti-interference circuit may be used in combination with various active clamp circuits.

[0077] 3. Simple design parameters, and it is unnecessary to design delay parameters according to the operation time of the active clamp circuit.

[0078] 4. High reliability, and the circuit minimizes the delay time and greatly reduces the protection blind zone.

[0079] Of course, the present disclosure may have various other embodiments, and without departing from the spirit and essence of the application, those skilled in the art shall make various corresponding modifications and variations to the application, but these corresponding modifications and variations shall belong to the scope protected by the appended claims of the application.