Fluxgate current transducer

Abstract

Fluxgate current transducer including a control circuit and a fluxgate measuring device comprising a fluxgate magnetic field detector, the fluxgate magnetic field detector comprising a saturable soft magnetic core surrounded by an excitation coil, the control circuit comprising an excitation coil drive circuit connected to the excitation coil and a controller connected to the excitation coil drive circuit configured to generate an alternating excitation current I.sub.fx to alternatingly saturate the soft magnetic core. The controller is in the form of a FPGA (Field Programmable Gate Array) comprising at least one input comprising a 1 bit sigma delta analog-to-digital converter (ADC) connected to the excitation coil to receive a measurement signal output by the excitation coil.

Claims

1. A fluxgate current transducer including a control circuit and a fluxgate measuring device comprising a fluxgate magnetic field detector, the fluxgate magnetic field detector comprising a saturable soft magnetic core surrounded by an excitation coil, the control circuit comprising an excitation coil drive circuit connected to the excitation coil and a controller connected to the excitation coil drive circuit configured to generate an alternating excitation current I.sub.fx to alternatingly saturate the soft magnetic core, wherein the controller is in the form of a FPGA (Field Programmable Gate Array) comprising a plurality of input circuit portions, each comprising a 1 bit sigma delta analog-to-digital converter (ADC) connected to the excitation coil to receive a measurement signal output by the excitation coil, each input circuit portion comprising a LVDS (low voltage differential signaling) comparator input of the FPGA, wherein bit stream output signals of said 1 bit sigma delta analog-to-digital converters are added before being fed into a digital filter.

2. The fluxgate current transducer according to claim 1, wherein the 1 bit sigma delta analog-to-digital converter (ADC) comprises a first resistor (R1) connected in series to a first input of the LVDS, a first capacitor (C1) connected between a reference potential and the first input, and a feedback loop from an output of the LVDS and the first input, the feedback loop comprising a 1 bit DAC and second resistor (R2).

3. The fluxgate current transducer according to claim 1, wherein the FPGA comprises a 1 bit sigma delta digital-to-analog (DAC) output connected to the excitation coil via a RC filter to supply a voltage control signal that is fed into an amplifier of the excitation coil drive circuit to supply the excitation coil of the fluxgate detector with an alternating excitation current.

4. The fluxgate current transducer according to claim 1, further comprising a compensation coil and the control circuit comprises a compensation coil drive circuit to supply the compensation coil of the fluxgate measuring device with a compensation current Is seeking to cancel the magnetic field of a primary current Ip, the FPGA comprising a 1 bit sigma delta digital-to-analog (DAC) output connected to the compensation current coil via an RC filter to supply a voltage control signal to the compensation coil drive circuit.

5. The fluxgate current transducer according to claim 1, further comprising a ripple cancellation coil and the control circuit comprises a ripple cancellation coil drive circuit to supply the compensation coil of the fluxgate measuring device with a compensation current Is seeking to cancel the magnetic field of a primary current Ip, the FPGA comprising a 1 bit sigma delta digital-to-analog (DAC) output connected to the ripple current cancellation coil via an RC filter to supply a voltage control signal to the ripple cancellation coil drive circuit.

6. The fluxgate current transducer according to claim 1, wherein the FPGA comprises an excitation voltage control circuit portion configured to generate an excitation voltage control signal Ve for the excitation coil having a trapezoidal shaped waveform.

7. A method of operating a fluxgate current transducer according to claim 1, wherein the method includes generating an excitation signal for the excitation coil of the fluxgate magnetic field detector as a trapezoidal shaped waveform.

8. The method according to claim 7, wherein the trapezoidal shaped waveform is generated using a fluxgate excitation lookup table stored in a memory of the FPGA.

Description

(1) Further objects and advantageous features of the invention will be apparent from the claims, from the detailed description, and annexed drawings, in which:

(2) FIG. 1 is a schematic block diagram of a current transducer with fluxgate detector according to an embodiment of the mention;

(3) FIG. 2a is a schematic circuit diagram of a portion of an input circuit to a Field Programmable Gate Array (FPGA) of a transducer control circuit according to an embodiment of the invention;

(4) FIG. 2b is a figure similar to FIG. 2a of a variant;

(5) FIG. 2c is a figure similar to FIG. 2b of yet another a variant;

(6) FIG. 3a is a schematic graphical representation of plots of a sinusoidal excitation voltage and associated excitation current of an excitation coil driver according to the prior art;

(7) FIG. 3b is a schematic graphical representation of plots of a square excitation voltage and associated excitation current of an excitation coil driver according to the prior art;

(8) FIG. 4 is a schematic graphical representation of plots of a hybrid excitation voltage according to an embodiment of the invention and associated excitation current signal.

(9) Referring to FIG. 1, an electrical current transducer 2 for measuring a primary current I.sub.P flowing in a primary conductor 1 comprises a fluxgate measuring device 7 and a control circuit 3.

(10) The fluxgate measuring device comprises a fluxgate magnetic field detector 4 and a secondary coil 6.

(11) As is per se well known in the art, the secondary coil acts as a compensation coil that is supplied with electrical current I.sub.S in a feedback loop 12 connected to the fluxgate detector 4 that seeks to cancel the magnetic field generated by a primary conductor 1 carrying the current I.sub.P to be measured, the primary conductor extending through a central passage 10 of the transducer.

(12) The fluxgate magnetic field detector 4 comprises a saturable soft magnetic core surrounded by an excitation coil that is connected to an excitation coil drive circuit 14 that generates an alternating excitation current I.sub.fx configured to alternatingly saturate the soft magnetic core.

(13) The current transducer may further comprise a ripple compensation circuit 28 connected to a ripple compensation coil 26 to perform a ripple compensating function for instance as per se known from WO2016/016038.

(14) The ripple compensation circuit 28 is configured to generate a ripple compensation current I.sub.R that seeks to cancel the ripple signal caused by the excitation current I.sub.fx of the fluxgate detector 4.

(15) The excitation voltage signal I.sub.fx for the excitation coil of the fluxgate magnetic field detector 4 is generated by the control circuit 3, in particular the controller 18 connected to the excitation coil drive circuit 14 which comprises an amplifier 20 to amplify the excitation coil control signal 17 output by the controller 18.

(16) According to a first aspect of the invention, the controller 18 is in the form of a FPGA (Field Programmable Gate Array) comprising at least one LVDS (low voltage differential signaling) input connected to the excitation coil.

(17) The LVDS input forms part of a 1 bit sigma delta analog-to-digital converter (ADC) 21 connected to the excitation coil to receive a measurement signal 19 output by the excitation coil.

(18) In the embodiment illustrated in FIG. 1, there are two LVDS inputs forming part of two 1 bit sigma delta analog-to-digital converters (ADC) 21 connected to the excitation coil, however the FPGA may comprise only one or more than two LVDS inputs connected to the excitation coil within the scope of the invention. Preferably the FPGA comprises more than two LVDS inputs connected to the excitation coil, for instance 6, 8, or more.

(19) The 1 bit sigma delta analog-to-digital converter (ADC) 21 comprises a first resistor R1 connected in series to a first input 23 of the LVDS, a first capacitor C1 connected between a reference potential (e.g. ground) and the first input 23, and a feedback loop from an output 29 of the LVDS and the first input 23, the feedback loop comprising a 1 bit DAC 27d and second resistor R2. A second input of the LVDS is connected to a reference voltage, for instance a mid-point of the FPGA LVDS bank may be used.

(20) In the input line of the LVDS, the R1-C1 circuit components forms an integrator for the sigma delta conversion, and the amplifier 15 serves to adjust the voltage to the LVDS input and act as a low impedance output and allow the sigma delta conversion to work properly.

(21) Basically, the ADCs 21 comprise an oversampling modulator followed by a digital/decimation filter that together produce a high-resolution data-stream output. The R1-C1 and Rx-Cx circuit components act as integrators and the LVDS inputs act as comparators. The clock frequency of the system (for instance a frequency >100 MHz) will then generate a 1 bit stream for each ADC 21 that are added before the digital filter 32. Adding a plurality of 1 bit sigma delta converters 21 increases the resolution of the bit stream and reduces noise.

(22) Advantageously, the 1 bit sigma delta analog-to-digital converter (ADC) 21 configured using a LVDS input of the FPGA is very cost effective to implement yet allows high precision due to the high frequency operational capability of a FPGA LVDS, typically greater than 100 MHz, and the digital signal processing of the subsequent measurement signal output by the LVDS. Moreover the 1 bit sigma delta analog-to-digital converter (ADC) 21 configured using a LVDS input 29 of the FPGA exhibits little or no drift and stable measurement accuracy over a typical operating temperature range for fluxgate current transducers.

(23) Another important advantage of the FPGA is that it starts very rapidly, typically in less than 500 ms, compared to a DSP which needs about 8 seconds.

(24) The FPGA may advantageously further comprise a 1 bit sigma delta digital-to-analog (DAC) output 27a connected to the excitation coil via a low pass RC filter 31a to supply a voltage control signal that is fed into the amplifier 20 of the excitation coil drive circuit 14 to supply the excitation coil of the fluxgate detector with an alternating excitation current. The FPGA advantageously allows high frequency 1 bit DAC that can be filtered only using first order low pass filters with simple RC circuit components, whereby no active filter is needed.

(25) The fluxgate Excitation LUT (Lookup table) is a table of N points defined that is read at a dedicated frequency to generate the fluxgate excitation signal. Each output value of this table can be adjusted dynamically by a gain circuit 31 and compensated in temperature or other parameters such as magnetic material fluctuations by an excitation adjustment circuit portion 30.

(26) In a variant (not shown), the FPGA may comprise two 1 bit sigma delta digital-to-analog (DAC) outputs 27a to generate a differential output DAC to the excitation coil via low pass RC filters 31a to supply a voltage control signal that is fed into the amplifier 20 of the excitation coil drive circuit 14 to supply the excitation coil of the fluxgate detector with an alternating excitation current.

(27) The FPGA may advantageously further comprise a 1 bit sigma delta digital-to-analog (DAC) output 27b connected to the compensation current coil via a low pass RC filter to supply a voltage control signal that is fed into the amplifier 20b of the compensation coil drive circuit 13 to supply the compensation coil of the transducer device 7 with a compensation current Is seeking to cancel the magnetic field of the primary current Ip. ADC inputs are fed into a digital filter 32 to digitalize the fluxgate current thanks to a CIC filter (Cascaded-Integrator-Comb-Filter) and a decimation filter. Then the digitalized fluxgate current is processed to evaluate with a simple calculation the even harmonics of the fluxgate current which should be compensated to perform the regulation.

(28) In a variant (not shown), the FPGA may comprise two 1 bit sigma delta digital-to-analog (DAC) outputs 27b to generate a differential output DAC connected to the compensation current coil via low pass RC filters to supply a voltage control signal that is fed into the amplifier 20b of the compensation coil drive circuit 13.

(29) The FPGA may advantageously further comprise a 1 bit sigma delta digital-to-analog (DAC) output 27c connected to the ripple current cancellation coil 26 via a low pass RC filter 31c to supply a voltage control signal that is fed into the amplifier 20c of the ripple coil drive circuit 28 to supply the ripple current cancellation coil 26 of the transducer device 7 with a ripple coil cancellation current Ir.

(30) In a variant (not shown), the FPGA may comprise two 1 bit sigma delta digital-to-analog (DAC) outputs 27c to generate a differential output DAC connected to the ripple current cancellation coil 26 via low pass RC filter 31c to supply a voltage control signal that is fed into the amplifier 20c of the ripple coil drive circuit 28.

(31) The ripple signal generation uses a similar block as described in relation with the excitation signal generation. There is a lookup table that is read at a specific frequency by the FPGA. The output can be adjusted dynamically with a gain circuit portion 39 and compensated in temperature by a temperature adjustment circuit portion 37. To be able to compensate the transducer noise some delay is added by a delay circuit portion 38 to this ripple compensation to compensate the noise properly.

(32) FIGS. 2a and 2b shows another embodiment of the invention using the 1 bit sigma delta ADC in pseudo differential mode to improve resolution and noise. In FIG. 2b, the LVDS input 21b is shifted to get the opposite bitstream of the LVDS input 21a. In FIG. 2a, an inverting amplifier 33 is used to avoid inverting the LVDS input to generate the pseudo differential mode.

(33) In FIG. 2C we use a differential amplifier 35 comprising two outputs used to generate the pseudo differential mode.

(34) According to a second aspect of the invention, the shape of the excitation voltage signal for the excitation coil of the fluxgate magnetic field detector is provided as a trapezoidal shaped waveform Ve with rounded corners (FIG. 4). The aim is to reduce the high frequency content of the excitation current signal Ie compared to a voltage signal square wave (FIG. 3a), while obtaining a higher mean value of a signal half cycle compared to a sinusoidal signal of same peak value (FIG. 3b). This allows to saturate the fluxgate core using a lower peak voltage than would be required using a sinusoidal signal without however the drawbacks of using a square voltage that generates high frequency noise that adversely affects the output measurement signal. The FPGA comprises an excitation voltage control circuit portion 22 configured to generate an excitation voltage control signal for the excitation coil having a trapezoidal shaped waveform with rounded corners. The trapezoidal shaped waveform may be generated using a fluxgate excitation lookup table 29 stored in a memory of the FPGA or externally with an EPROM or flash memory.

LIST OF FEATURES

(35) primary conductor 1 electrical current transducer 2 fluxgate measuring device 7 fluxgate magnetic field detector 4 saturable soft magnetic core excitation coil secondary coil 6 ripple compensation coil 26 control circuit 3 feedback loop 12 compensation current drive circuit 13 excitation coil drive circuit 14 amplifier 20 ripple compensation circuit 28 FPGA controller 18 1 bit sigma delta analog-to-digital converter (ADC) 21 LVDS input 29a 1 bit sigma delta digital-to-analog (DAC) outputs 27a, 27b, 27c, 27d RC filter 31a, 31b, 31c primary current I.sub.P secondary current I.sub.S alternating excitation current I.sub.fx ripple cancellation current I.sub.R