MULTI-LEVEL INVERTER

Abstract

Method of controlling a multi-level inverter having inputs connected to a gate drive unit controlling the inverter and an output connected to a load, the multi-level inverter capable of generating a PWM voltage signal having three or more modulation levels, the inverter powered by a voltage supply and comprising at least one neutral point (NP), the method comprising operating the multi-level inverter in a standard modulation pattern having three or more modulation levels when one or more parameters representative of neutral point stability each have a value within a first range indicative of a high neutral point stability, and operating the multi-level inverter with a two-level modulation pattern when said one or more parameters representative of neutral point stability each have a value within a second range indicative of a low neutral point stability, the first range separated from the second range by a threshold value.

Claims

1.-15. (canceled)

16. Method of controlling a multi-level inverter having inputs connected to a drive unit controlling the inverter and an output connected to a load, the multi-level inverter capable of generating a PWM voltage signal having three or more modulation levels, the inverter powered by a voltage supply and comprising at least one neutral point, the method comprising operating the multi-level inverter in a standard modulation pattern having three or more modulation levels when one or more parameters representative of neutral point stability each have a value within a first range indicative of a high neutral point stability, and operating the multi-level inverter with a two-level modulation pattern when said one or more parameters representative of neutral point stability each have a value within a second range indicative of a low neutral point stability, the first range separated from the second range by a threshold value.

17. Method according to claim 16, wherein the load is a multiphase electric motor, and the inverter comprises a multi-level modulation circuit for each phase leg, each multi-level modulation circuit having an output connected to a corresponding phase of the electric motor.

18. Method according to claim 16, wherein the parameters representative of neutral point stability include any one or more of: TABLE-US-00013 V.sub.np Neutral point voltage; ω Motor stator frequency; ε.sub.np Deviation of neutral point voltage ( | V.sub.DC/2 − V.sub.NP | ) in %; cos(φ) Motor power factor = Real power/Apparent power; I.sub.ph Motor phase current; ƒ.sub.pwm Modulation (PWM) frequency.

19. Method according to claim 16, wherein said threshold values of parameters representative of low neutral point stability include any one or more of: TABLE-US-00014 ω.sub.min Minimum motor stator frequency Threshold value having a value between 0 to 40% of nominal speed; ε.sub.np_max Allowed deviation of neutral Threshold value having a value point voltage in % between 0 to 50 [%]; PF.sub.min Motor minimum power factor Threshold value having a value between 0 to 0.7 [—]; I.sub.ph_min Motor minimum phase current Threshold value having a predetermined value depending on the characteristics of the motor [A]; ƒ.sub.pwm_min Minimum PWM frequency Threshold value having a value between 0 to 50 [kHz].

20. Method according to claim 19, wherein the threshold value for each of the one or more parameters are selected as: TABLE-US-00015 ω.sub.min Minimum motor stator frequency Threshold value having a value between 5% to 30% of nominal speed, ε.sub.np Allowed deviation of neutral Threshold value having a value point voltage in % between 5 to 30 [%], PF.sub.mi Motor minimum power factor Threshold value having a value between 0.1 to 0.5 [—], I.sub.ph_ min Motor minimum phase current 5% to 40% of Nominal current [A], ƒ.sub.pwm_min Minimum PWM frequency Threshold value having a value between 1 to 30 [kHz].

21. Method according to claim 20, wherein the threshold value for each of the one or more parameters are selected as: TABLE-US-00016 ω.sub.min Minimum motor stator frequency Threshold value having a value between 5% to 15% of nominal speed, ε.sub.np Allowed deviation of neutral Threshold value having a value point voltage in % between 10 to 20 [%], PF.sub.mi Motor minimum power factor Threshold value having a value between 0.1 to 0.3 [—], I.sub.ph_ min Motor minimum phase current 10% to 30% of Nominal current [A], ƒ.sub.pwm_min Minimum PWM frequency Threshold value having a value between 5 to 15 [kHz].

22. A drive for an electrical motor comprising a power electronics module and a gate drive unit connected to a controller and to the power electronics module to control the motor, the power electronics module comprising a multi-level inverter having at least one output connected to at least one phase of the motor, the multi-level inverter capable of generating a PWM voltage signal having three or more modulation levels, the inverter powered by a voltage supply and comprising at least one neutral point, wherein the controller is configured to control the gate drive unit to: operate the multi-level inverter in a standard modulation pattern having three or more modulation levels when one or more parameters representative of neutral point stability each have a value within a first range indicative of a high neutral point stability, and to operate the multi-level inverter with a two-level modulation pattern when said one or more parameters representative of neutral point stability each have a value within a second range indicative of a low neutral point stability, the first range separated from the second range by a threshold value.

23. The drive of claim 22, wherein the controller receives voltage (V.sub.DC, V.sub.NP) and phase current (i.sub.u, i.sub.w, i.sub.v) measurement inputs from a power supply and the motor, the power supply comprising a DC voltage supply.

24. The drive of claim 22, wherein the motor is a multi-phase (U, V, W) motor and the inverter is a multi-phase inverter having one said output for each phase.

25. The drive of claim 22, wherein the inverter is a diode clamped inverter.

26. The drive of claim 22, wherein the inverter comprises a neutral point clamped (NPC) inverter circuit topology per phase leg.

27. The drive of claim 22, wherein the inverter comprises a T-type three-level inverter circuit topology per phase leg.

28. The drive of claim 22, wherein the threshold values are stored in, or computed from values stored in a non-transient memory of the drive and wherein an executable control algorithm is stored in a non-transient memory of the drive, the control algorithm executable by the controller to control the gate drive unit.

29. The drive of claim 22, wherein the threshold values include any one or more of the values set forth in claim 19.

30. The drive of claim 22, wherein the parameters representative of neutral point stability include any one or more of: TABLE-US-00017 V.sub.np Neutral point voltage; ω Motor stator frequency; ε.sub.np Deviation of neutral point voltage ( | V.sub.DC/2 − V.sub.NP | ) in %; cos(φ) Motor power factor = Real power/Apparent power; I.sub.ph Motor phase current; ƒ.sub.pwm Modulation (PWM) frequency.

Description

[0034] Further objects and advantageous features of the invention will be apparent from the claims, from the detailed description, and annexed drawings, in which:

[0035] FIG. 1a is a schema of a circuit of a three-level inverter, per se known, that may be used in a multi-level inverter according to a first embodiment of the invention;

[0036] FIG. 1b is a schema of a circuit of another three-level inverter, per se known, that may be used in a multi-level inverter according to a second embodiment of the invention;

[0037] FIG. 2 is a flow diagram illustrating schematically an overall method of controlling a multi-level inverter according to an embodiment of the invention;

[0038] FIG. 3 is a flow diagram illustrating schematically a method of controlling a multi-level inverter according to an embodiment of the invention;

[0039] FIG. 4a is a schema illustrating a three-level PWM signal and corresponding output signal when the multi-level inverter according to an embodiment of the invention is operating in three-level mode;

[0040] FIG. 4b is a schema illustrating a two-level PWM signal and corresponding output signal when the multi-level inverter according to an embodiment of the invention is operating in two-level mode.

[0041] FIG. 5 is a simplified block schema illustrating an electrical motor system according to an embodiment of the invention, including an electrical motor connected to a gate drive unit and a power electronics unit comprising an inverter, according to an embodiment of the invention;

[0042] FIG. 6 is a schema of a circuit of a three phase motor connected to a three phase three-level inverter according to an embodiment of the invention.

[0043] Referring to the FIGS. 1a and 1b, two different 3-level inverter topologies for one phase leg are illustrated. Both of these 3-level inverter topologies are per se known. FIG. 1a illustrates a neutral point clamped (NPC) inverter circuit topology (for one phase leg) whereas FIG. 1b illustrates a T-type three-level inverter circuit topology (for one phase leg).

[0044] In the illustrated embodiments, the inverters 2 are diode clamped inverters, however it will be appreciated that other inverter types such as flying capacitor inverters may be employed without departing from the scope of the invention.

[0045] Moreover, FIGS. 1a and 1b illustrate only one phase of a three-level inverter, but it will be appreciated that the inverter according to embodiments of the invention may be a multiphase inverter having two, three or more phases depending on the application.

[0046] For instance, as illustrated in FIGS. 5 and 6, many electrical motors are three phase U, V, W and thus the inverter according to an embodiment of the invention for such application is a three phase inverter. The principles described herein for one phase leg apply to each phase leg of the multiphase inverter.

[0047] Referring to FIGS. 5 and 6, according to an aspect of the invention, an electrical motor system comprises a multiphase U, V, W electrical motor 3 connected to a drive 1 and a DC power supply 4. The drive 1 comprises a power electronics module 5 connected to a gate drive unit 6. The gate drive unit includes or is connected to a control module 7 that receives voltage V.sub.DC, V.sub.NP and phase current i.sub.u, i.sub.w, i.sub.v measurement inputs 8, 9 from the power supply 4 and motor 3 to control the gate drive and power electronics for control of the motor 3.

[0048] The power electronics module 5 comprise a multi-level multi-phase inverter 2 according to embodiments of the invention, as illustrated in FIGS. 5 and 6.

[0049] Although the illustrated embodiments show a three-level inverter for each phase leg, the invention also applies to higher level inverters, such as five level or seven level inverters per phase leg that enable the generation of smoother stepped output waveforms with lower harmonic distortions, but that also face the problem of neutral point control under certain operating conditions similarly to three-level inverters.

[0050] The present invention overcomes the problem of neutral point deviation by operating the multi-level inverter with a standard modulation scheme having three or more levels of modulation patterns, depending on the number of modulation levels of the inverter, when neutral point stability is high, and operating the multi-level inverter with a two-level modulation pattern when neutral point stability is low. The operation of the multi-level inverter may switch between three (or higher) level modulation and two-level modulation patterns depending on one or more operating parameters of the inverter and the load connected to the inverter.

[0051] The load may in particular comprise a multiphase, for instance three phase U, V, W, electrical motor 3 connected to a multiphase, for instance three phase inverter 2 according to embodiments of the invention as schematically illustrated in FIGS. 5 and 6.

[0052] Using the two level modulation pattern when starting a motor without sensor feedback also improves stability and control of the sensorless start.

[0053] Using the two level modulation pattern in a multi-level inverter according to embodiments of the invention also advantageously allows to reduce the size of the DC link capacitors C.sub.1, C.sub.2 compared to conventional multi-level inverters.

[0054] The inverter according to embodiments of the invention is connected to a gate drive unit 6 comprising or connected to a controller 7 that, inter alia, is connected to the inverter transistors Q1-Q4 to control the switching of the transistors for the generation of the modulation patterns, in particular the pulse width modulation (PWM) patterns of the standard multi-level modulation scheme and the two-level modulation scheme.

[0055] The switching states of the transistors Q1, Q2, Q3 and Q4 of three-level inverters of both embodiments of FIGS. 1a and 1b for three-level modulation is illustrated in the table below:

TABLE-US-00005 Voltage between the neutral point Switching state NP and the output V.sub.out-NP Q1 Q2 Q3 Q4 Positive (P)  +V.sub.DC/2 On On Off Off Neutral (0) 0 Off On On Off Negative (N)  −V.sub.DC/2 Off Off On On

[0056] The corresponding three-level PWM signal is illustrated in FIG. 4a whereby the PWM signal has an inverter phase leg output voltage V.sub.Out-G with values +V.sub.DC, +V.sub.DC/2 and 0 for the positive portion of voltage signal, and values 0, −V.sub.DC/2, and −V.sub.DC for the negative portion of voltage signal.

[0057] The switching states of the transistors Q1, Q2, Q3 and Q4 of the three-level inverters of both embodiments of FIGS. 1a and 1b for operation in two-level modulation mode is illustrated in the table below:

TABLE-US-00006 Voltage between the neutral point Switching state NP and the output V.sub.Out-NP Q1 Q2 Q3 Q4 Positive (P) +V.sub.DC/2 On On Off Off Negative (N)  −V.sub.DC/2 Off Off On On

[0058] The corresponding two-level PWM signal is illustrated in FIG. 4b whereby the PWM signal has an inverter phase leg output voltage V.sub.Out-G with values +V.sub.DC, and 0 for the positive portion of voltage signal, and values 0, and −V.sub.DC for the negative portion of voltage signal.

[0059] In both inverter circuit designs of FIGS. 1a and 1b, a two-level inverter mode of operation can easily be achieved by avoiding the switching state “Neutral (0)”. It may be noted that in two-level mode the gate drive unit is configured to drive the transistor pair Q1-Q3 and transistor pair Q2-Q4 always in complementary manner such that they are in an opposite switching states.

[0060] The gate drive unit controller receives measurement signals of the operating parameters from the load and the inverter that are used to determine the operating mode, in particular the level of the PWM modulation pattern level, and to control the switching between standard multi-level modulation, two-level modulation, or no modulation.

[0061] An illustration of these modulation modes or states is schematically illustrated in FIG. 2, whereby the transition between states (no modulation, 3 level modulation, 2 level modulation) in this example is briefly explained in the table below.

TABLE-US-00007 Transition Description 1 Initial and automatic transition 2 Modulation of inverter is requested to switch off. No pulses are generated any more. 3 Modulation of inverter is requested to be switched on. 4 The 2-level modulation strategy is selected depending on operating parameters selected from any one or more of: 1) High neutral point potential deviation 2) Low stator frequency of the motor connected to the inverter 3) Low power factor cos(.sup.ϕ) of the motor connected to the inverter 4) Low phase current magnitude 5) Low PWM frequency 5 The 3-level modulation strategy is selected for all other cases than listed under transition 4. 6, 7, 8 Automatic transitions

[0062] Operating parameters that may be measured or computed and used by the gate drive unit 6 to determine whether to operate the inverter in two-level or multi-level modulation mode, where the electrical load is an electrical motor 3, are presented below:

TABLE-US-00008 Parameter Description Typical operating range of values V.sub.np Neutral point voltage A predetermined value depending on the characteristics of the system (motor and supply) [V] ε.sub.np Deviation of neutral point voltage Threshold value having a value ( | V.sub.DC/2 − V.sub.NP | ) in %; between 0 to 50 [%]; ω Stator frequency 0 to 40% of nominal speed cos(φ) Motor power factor = Real power/ 0 to 1 [—] Apparent power I.sub.ph Motor phase current A predetermined value depending on the characteristics of the motor [A] f.sub.pwm Modulation (PWM) frequency 0 to 100 [kHz]

[0063] According to embodiments of the invention, the threshold values of the above mentioned parameters are set in the following ranges:

TABLE-US-00009 Threshold values for determining Parameter Description transition to two-level modulation ω.sub.min Minimum motor stator frequency 0 to 40% of nominal speed ε.sub.np_max Allowed deviation of neutral 0 to 50 [%] point voltage in % PF.sub.min Motor minimum power factor 0 to 0.7 [—] I.sub.ph_min Motor minimum phase current A predetermined value depending on the characteristics of the motor [A] f.sub.pwm_min Minimum PWM frequency 0 to 50 [kHz]

[0064] In advantageous embodiments, the threshold values may in particular be set in the following ranges:

TABLE-US-00010 Threshold values for determining Parameter Description transition to two-level modulation ω.sub.min Minimum motor stator frequency 5 to 30% of nominal speed ε.sub.np_max Allowed deviation of neutral 5 to 30 [%] point voltage in % PF.sub.min Motor minimum power factor 0.1 to 0.5 [—] I.sub.ph_min Motor minimum phase current 5% to 40% of Nominal current [A] f.sub.pwm_min Minimum PWM frequency 1 to 30 [kHz]

[0065] Preferably, according to advantageous embodiments of the invention, the threshold values may be set in the following ranges:

TABLE-US-00011 Threshold values for determining Parameter Description transition to two-level modulation ω.sub.min Minimum motor stator frequency 5% to 15% of nominal speed ε.sub.np_max Allowed deviation of neutral 10 to 20 [%] point voltage in % PF.sub.min Motor minimum power factor 0.1 to 0.3 [—] I.sub.ph_min Motor minimum phase current 10% to 30% of Nominal current [A] f.sub.pwm_min Minimum PWM frequency 5 to 15 [kHz]

[0066] An example of threshold values of the above mentioned parameters in an advantageous embodiment is illustrated below:

TABLE-US-00012 Threshold values for determining Parameter Description transition to two-level modulation ω.sub.min Minimum motor stator frequency 10% of nominal speed ε.sub.np_max Allowed deviation of neutral 15 [%] point voltage in % PF.sub.min Motor minimum power factor 0.2 [—] I.sub.ph_min Motor minimum phase current 20% of Nominal current [A] f.sub.pwm_min Minimum PWM frequency 8 [kHz]

[0067] A range of values, or a threshold value (e.g. a minimum or maximum value), or a plurality of threshold values (lower bound and upper bound), may be set for any one or more of the above parameters and stored for instance in a lookup table in a memory, preferably in a memory of the gate drive unit. The gate drive unit receives measurement values of said any one or more of the above parameters and compares them with the stored values to determine the control mode of the inverter. For instance, if frequency ω of motor stator coils drops below a threshold value of 40% of the nominal speed (frequency) of the motor in the above example, the gate drive unit transitions operation of the inverter from standard multi-level (three-level in the illustrated embodiments) operation to two-level modulation, and when frequency ω of the motor stator coils increases above a threshold value of 40% of the nominal speed (frequency) the gate drive unit transitions operation of the inverter from two-level modulation back to standard multi-level (three-level in the illustrated embodiments) operation. Thus, when the operating parameter is in a first range on one side of a threshold value, in which the neutral point is stable (either below or above the threshold value depending on the parameter), the inverter operates in standard multi-level modulation mode, and if the operating parameter value crosses the threshold value to the other side constituting a second range in which the neutral point is potentially unstable, the inverter mode of operation switches to the two level modulation mode.

[0068] It may be noted that, in embodiments, the transition threshold values of the parameters used to control operation of the inverter between two-level and multi-level modulation patterns, may be different depending on the direction of the transition to ensure a partial overlap of ranges of values determining the transition. In particular, the transition from two-level to multi-level modulation may have a different threshold value than the threshold value for the transition from multi-level modulation to two-level modulation such that the range of operation in two-level mode overlaps partially the range of operation in three or high level operation mode in order to avoid instability around the transition value. For instance, the threshold value of the stator frequency ω may be 40% of the nominal motor frequency in the direction of decreasing frequency for transition from three to two-level modulation, whereas the threshold value of the stator frequency ω may be 45% of the nominal motor frequency in the direction of increasing frequency for transition from two to three-level modulation. The aforegoing feature may apply to any one or more of the values having a threshold to control the transition from one modulation pattern to the other modulation pattern

[0069] Any parameter or combination of parameters that are indicative of a deviation or an instability of the neutral point voltage beyond desired amplitudes for accurate control of the system (e.g. electrical motor) may be used to set transition values for changing the modulation pattern of the inverter. In embodiments of an electrical motor connected to an inverter, the preferred parameters for determining the modulation pattern may include: neutral point potential deviation V.sub.np, stator frequency ω of the motor, power factor cos(.sup.ϕ) of the motor, phase current magnitude I.sub.ph and PWM frequency f.sub.pwm. All of these preferred parameters may be used to control the operation mode of the inverter between three-level (multi-level) or two-level as illustrated in the flow diagram of FIG. 3. It may however be noted that only one, or only a subset of the preferred parameters may be used to control the operation mode of the inverter between three-level (multi-level) or two-level. Moreover, as mentioned above, other parameters that are indicative of a deviation or an instability of the neutral point voltage beyond desired amplitudes may be employed to control the operation mode of the inverter between multi-level and two-level operation.

[0070] Furthermore, in variants, two or more of the control parameters may also be combined, for instance a ratio or a multiplication of parameters to form a composite value, for instance a ratio of phase current magnitude with respect to PWM frequency Iph/f.sub.pwm or a product of the phase current magnitude and the PWM frequency I.sub.ph×f.sub.pwm Another example would be a weighted sum between phase current magnitude, PWM frequency and stator frequency, the factors k.sub.x are scaling factors k.sub.1*I.sub.ph+k.sub.2*f.sub.pwm+k.sub.3*ω