Hybrid Analog/Digital Phase Locked Loop with Fast Frequency Changes

Abstract

A hybrid Phase Locked Loop, PLL (10, 34A, 34B, 38) employs an analog control loop during a first period of operation, such as steady-state operation, to achieve a simple design, stable operation at very high frequency, and low phase noise. During a second period of operation, such as frequency changes, a digital control loop takes over. Under digital control, charge pump (14) inputs are forced to be at or near 100% duty cycle for maximum loop filter (16) charging and fast, linear frequency change. The digital control loop monitors when the target frequency is reached, and exits the second period of operation with the proper feedback signal phase. The digital control loop can operate in two control modes. In a first mode, the phase of the divided VCO output signal is synchronized with the phase of a periodic reference signal throughout the frequency change. In a second mode, the frequency and phase are controlled in separate steps, by controlling the integer and fractional parts of delta-sigma generated division number. Three embodiments are disclosed. In a first embodiment, a switch substitutes constant charge pump (14) inputs for the outputs of a phase frequency detector, PFD (12) to maximize the loop filter (16) current. In a second embodiment, one pulse of one of the periodic signals is suppressed, forcing the PFD (12) to output charge pump input signals at near 100% duty cycle. In a third embodiment, all the cycles of one of the periodic signals are suppressed, forcing PFD (12) output signals to 100% duty cycle.

Claims

1-27. (canceled)

28. A hybrid Phase Locked Loop (PLL) comprising: a Voltage Controlled Oscillator (VCO) configured to generate a VCO output signal having a frequency determined by a VCO control input signal; a frequency divider circuit configured to divide the frequency of the VCO output signal by a controlled division number; a Phase Frequency Detector (PFD) configured to generate PFD output signals indicative of a difference in edge timing between the divided VCO output signal and a reference periodic signal; a loop filter including a capacitor and configured to generate the VCO control input signal; a charge pump having Charge Up (CU) and Charge Down (CD) inputs and configured to inject a corresponding current into the loop filter; an analog control loop configured to generate the VCO control input signal during a first period of operation; and a digital control loop configured to generate the VCO control input signal during a second period of operation, by digitally controlling the CU and CD inputs to the charge pump.

29. The hybrid PLL of claim 28 further comprising a delta-sigma modulator configured to provide, to the frequency divider circuit, a time series of integer division numbers in response to integer and fractional components of the controlled division number.

30. The hybrid PLL of claim 28 wherein the analog control loop is configured to generate the CU or CD charge pump inputs in response to the PFD output signals; and the digital control loop is configured to force the CU or CD charge pump inputs to be at or near 100% duty cycle.

31. The hybrid PLL of claim 30 wherein the digital control loop is configured to generate the CU or CD charge pump inputs at 100% duty cycle by switching the CU or CD charge pump inputs to predetermined voltage values.

32. The hybrid PLL of claim 30 wherein the digital control loop is configured to generate the CU or CD charge pump inputs near 100% duty cycle by a pulse suppression circuit suppressing at least one pulse in one of the divided VCO output signal and the reference periodic signal, thereby forcing the PFD to output the CU or CD charge pump input near 100% duty cycle in response to the pulse suppression circuit outputs.

33. The hybrid PLL of claim 32 wherein the digital control loop is configured to generate the CU or CD charge pump inputs at 100% duty cycle by the pulse suppression circuit suppressing all pulses in one of the divided VCO output signal and the reference periodic signal, thereby forcing the PFD to output the CU or CD charge pump input at 100% duty cycle in response to the pulse suppression circuit outputs.

34. The hybrid PLL of claim 28 further comprising a current source configured to inject additional current into the loop filter under the control of the digital control loop.

35. The hybrid PLL of claim 28 wherein: the loop filter includes a resistor providing a transmission zero in a frequency response of the loop filter and a switch operative to selectively bypass the resistor; and the digital control loop is further configured to control the switch to bypass the resistor during at least part of the second period of operation.

36. The hybrid PLL of claim 35 wherein: the switch comprises a plurality of independently controllable switch elements; and the digital control loop is further configured to control the switch, at least when ceasing to bypass the resistor, by disabling at least two independently controllable switch elements in different cycles of the reference periodic signal, to thereby reduce transient voltage changes in the VCO control input signal.

37. The hybrid PLL of claim 28 further comprising one or more Time to Digital Conversion (TDC) circuits 32 configured to quantize the length of CU or CD pulses when the digital control loop is active.

38. A method of controlling a hybrid Phase Locked Loop (PLL) comprising a Voltage Controlled Oscillator (VCO) configured to generate a VCO output signal having a frequency determined by a VCO control input signal, a frequency divider circuit configured to divide the frequency of the VCO output signal by a controlled division number, a Phase Frequency Detector (PFD) configured to generate PFD output signals indicative of a difference in edge timing between the divided VCO output signal and a reference periodic signal, a loop filter including a capacitor and configured to generate the VCO control input signal, and a charge pump having Charge Up (CU) and Charge Down (CD) inputs and configured to inject a corresponding current into the loop filter, the method comprising: during a first period of operation, controlling the loop filter to generate the VCO control input signal via an analog control loop; and during a second period of operation, controlling the loop filter to generate the VCO control input signal by controlling the CU and CD inputs to the charge pump, via a digital control loop.

39. The method of claim 38 wherein controlling the loop filter to generate the VCO control input signal via the digital control loop comprises switching the CU and CD inputs to the charge pump to predetermined voltage values having 100% duty cycle.

40. The method of claim 38 wherein controlling the loop filter to generate the VCO control input signal via the digital control loop comprises suppressing at least one pulse in one of the divided VCO output signal and the reference periodic signal, forcing the PFD to output the CU or CD charge pump input near 100% duty cycle.

41. The method of claim 38 wherein controlling the loop filter to generate the VCO control input signal via the digital control loop comprises suppressing all pulses in one of the divided VCO output signal and the reference periodic signal, forcing the PFD to output the CU or CD charge pump input at 100% duty cycle.

42. The method of claim 38 wherein controlling the loop filter to generate the VCO control input signal via the digital control loop further comprises summing the output of the charge pump with additional current prior to injecting the current into the loop filter.

43. The method of claim 38 wherein the hybrid PLL further comprises a delta-sigma modulator configured to provide a division number to the frequency divider circuit; and the digital control loop provides integer and fractional parts of the division number to the delta-sigma modulator during the second period of operation.

44. The method of claim 43 wherein providing integer and fractional parts of the division number to the delta-sigma modulator during the second period of operation comprises controlling the integer and fractional part of the division number, in response to outputs of the PFD, to synchronize the phase of the divided VCO output signal and the reference periodic signal.

45. The method of claim 43 wherein providing integer and fractional parts of the division number to the delta-sigma modulator during the second period of operation comprises: in a frequency control step, controlling the inputs to the charge pump, to change the hybrid PLL output frequency to the desired frequency; and in a phase control step, controlling the integer and fractional parts of the division number, in response to outputs of the PFD, to synchronize the phase of the divided VCO output signal with that of the reference periodic signal.

46. The method of claim 45 wherein, in the phase control step, controlling the fractional part of the division number comprises computing a difference between a desired value of the fractional part and an average of the delta sigma modulator output over a plurality of cycles.

47. The method of claim 45 further comprising disabling the CU and CD inputs to the charge pump during the phase control step.

48. The method of claim 45 wherein, during the frequency control step, controlling the inputs to the charge pump, to change the hybrid PLL output frequency comprises: setting the integer and fractional parts of the division number to correspond to a target frequency; quantizing the pulse length of CU and CD signals derived from the rising edge timing of the periodic reference signal and the VCO output signal; quantizing the pulse length of CU and CD signals derived from the falling edge timing of the periodic reference signal and the VCO output signal; and determining that the desired output frequency is achieved, and the terminating the frequency control step, when the timing between the divided VCO output signal and the reference periodic signal are equal, or differ by less than a predetermined threshold value, for a predetermined number of consecutive edges.

49. The method of claim 48, wherein the resolution of TDCs quantizing the pulse lengths of CU and CD signals derived from rising and falling edges is equal, and wherein the resolution is selected to allow a pulse length timing difference large enough when detecting a frequency control step termination condition to accommodate a desired frequency change ramping rate.

50. The method of claim 38 further comprising bypassing a resistor in the loop filter during at least part of the second period of operation.

51. The method of claim 50 wherein bypassing the resistor comprises removing the bypass by disabling at least two independently controllable switch elements in different cycles of the reference periodic signal.

52. A Radio Frequency transceiver, comprising: receiver circuitry; transmitter circuitry; and one or more hybrid Phase Locked Loops (PLL) each comprising: a Voltage Controlled Oscillator (VCO) configured to generate a VCO output signal having a frequency determined by a VCO control input signal; a frequency divider circuit configured to divide the frequency of the VCO output signal by a controlled division number; a Phase Frequency Detector (PFD) configured to generate PFD output signals indicative of a difference in edge timing between the divided VCO output signal and a reference periodic signal; a loop filter including a capacitor and configured to generate the VCO control input signal; a charge pump having Charge Up (CU) and Charge Down (CD) inputs and configured to inject a corresponding current into the loop filter; an analog control loop configured to generate the VCO control input signal during a first period of operation; and a digital control loop configured to generate the VCO control input signal during a second period of operation, by digitally controlling the CU and CD inputs to the charge pump.

53. A base station operative in a wireless communication network, comprising: processing circuitry; memory operatively connected to the processing circuitry; and a transceiver controlled by the processing circuitry, the transceiver including one or more hybrid Phase Locked Loops (PLL) each comprising: a Voltage Controlled Oscillator (VCO) configured to generate a VCO output signal having a frequency determined by a VCO control input signal; a frequency divider circuit configured to divide the frequency of the VCO output signal by a controlled division number; a Phase Frequency Detector (PFD) configured to generate PFD output signals indicative of a difference in edge timing between the divided VCO output signal and a reference periodic signal; a loop filter including a capacitor and configured to generate the VCO control input signal; a charge pump having Charge Up (CU) and Charge Down (CD) inputs and configured to inject a corresponding current into the loop filter; an analog control loop configured to generate the VCO control input signal during a first period of operation; and a digital control loop configured to generate the VCO control input signal during a second period of operation, by digitally controlling the CU and CD inputs to the charge pump.

54. User Equipment operative in a wireless communication network, comprising: processing circuitry; memory operatively connected to the processing circuitry; and a transceiver controlled by the processing circuitry, the transceiver including one or more hybrid Phase Locked Loops (PLL) each comprising: a Voltage Controlled Oscillator (VCO) configured to generate a VCO output signal having a frequency determined by a VCO control input signal; a frequency divider circuit configured to divide the frequency of the VCO output signal by a controlled division number; a Phase Frequency Detector (PFD) configured to generate PFD output signals indicative of a difference in edge timing between the divided VCO output signal and a reference periodic signal; a loop filter including a capacitor and configured to generate the VCO control input signal; a charge pump having Charge Up (CU) and Charge Down (CD) inputs and configured to inject a corresponding current into the loop filter; an analog control loop configured to generate the VCO control input signal during a first period of operation; and a digital control loop configured to generate the VCO control input signal during a second period of operation, by digitally controlling the CU and CD inputs to the charge pump.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.

[0021] FIG. 1 is a block diagram of a first embodiment of a hybrid PLL.

[0022] FIG. 2A is a timing diagram depicting target frequency detection using rising and falling edges.

[0023] FIG. 2B is a timing diagram depicting target frequency detection using only rising edges.

[0024] FIG. 3 is a timing diagram showing frequency convergence of the hybrid PLL of FIG. 1.

[0025] FIG. 4 is a timing diagram showing phase convergence of the hybrid PLL of FIG. 1.

[0026] FIG. 5 is a simulation result comparing the hybrid PLL of FIG. 1 to the prior art.

[0027] FIG. 6A is a block diagram of a second embodiment of a hybrid PLL operating in a first control mode.

[0028] FIG. 6B is a block diagram of the second embodiment of the hybrid PLL operating in a second control mode.

[0029] FIG. 7 is a timing diagram showing frequency convergence of the hybrid PLL of FIG. 6B.

[0030] FIGS. 8A and 8B are circuit schematics of prior art and inventive PFDs.

[0031] FIG. 9A is a timing diagram showing TDC operation using the full bit width.

[0032] FIG. 9B is a timing diagram showing TDC operation using less than full bit width.

[0033] FIG. 10 is a timing diagram showing phase convergence of the hybrid PLL of FIG. 6B.

[0034] FIG. 11 is a simulation result comparing the hybrid PLL of FIG. 6A, 6B to the prior art.

[0035] FIG. 12A is a simulation result comparing frequency ramping of the hybrid PLLs of FIGS. 1 and 6A, 6B.

[0036] FIG. 13 is a block diagram of a third embodiment of a hybrid PLL.

[0037] FIG. 14 is a timing diagram showing frequency convergence of the hybrid PLL of FIG. 13.

[0038] FIG. 15 is a timing diagram showing suppression of periodic signals to force charge pump inputs inactive during a phase control step.

[0039] FIGS. 16A and 16B are timing diagrams showing phase convergence of the hybrid PLL of FIG. 13.

[0040] FIG. 17 is a simulation result comparing the hybrid PLL of FIG. 13 to the prior art.

[0041] FIG. 18A is a schematic diagram of a prior art loop filter.

[0042] FIG. 18B is a schematic diagram of a loop filter with inventive resistor bypass switch.

[0043] FIG. 19 is a simulation result comparing the loop filters of FIGS. 18A and 18B.

[0044] FIGS. 20A, 20B, and 20C simulation results depicting various loop filter resistor bypass switching times and modes.

[0045] FIG. 21 shows simulation results comparing the loop filters of FIGS. 18A and 18B.

[0046] FIG. 22 is a flow diagram of a method of operating a hybrid PLL.

[0047] FIG. 23 is a block diagram of a base station.

[0048] FIG. 24 is a block diagram of User Equipment.

DETAILED DESCRIPTION

[0049] For simplicity and illustrative purposes, the present invention is described by referring mainly to an exemplary embodiment thereof. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be readily apparent to one of ordinary skill in the art that the present invention may be practiced without limitation to these specific details. In this description, well known methods and structures have not been described in detail so as not to unnecessarily obscure the present invention.

First Embodiment

[0050] FIG. 1 depicts a hybrid PLL 10 according to a first embodiment of the present invention. As used herein, the term “hybrid PLL” refers to a Phase Locked Loop circuit that is a hybrid between analog and digital designs. In particular, the hybrid PLL 10 includes an analog control loop that is configured to control a loop filter 16 to generate a control input signal to a Voltage Controlled Oscillator (VCO) 18 during a first period of operation, such as steady-state operation. Additionally, the hybrid PLL 10 includes a digital control loop configured to control the loop filter (LF) 16 to generate the VCO 18 control input signal during a second period of operation, such as during changes in the output frequency, by controlling the charging of a capacitor in the loop filter in response to timing of outputs of a Phase Frequency Detector (PFD) 12.

[0051] The hybrid PLL is first described with reference to its analog control loop. A VCO 18 is configured to generate a periodic output signal having a frequency determined by a VCO control input signal. A frequency divider circuit (DIV) 20 is configured to divide the frequency of the VCO output signal by a controlled division number, and the divided VCO output signal is provided to the PFD circuit 12. The PFD 12 is configured to output CU′/CD′ signals indicative of a difference in edge timing between the divided VCO output signal and a reference periodic signal, which may for example be generated by a precision source, such as a crystal oscillator. As used herein, CU′-R/CD′-R denote the outputs of a PFD 12 monitoring rising edges of the periodic signals; CU′-F/CD′-F denote the outputs of a falling edge monitoring PFD 12. In embodiments with only one PFD 12 (triggering on either rising or falling edges), the more general notation CU′/CD′ is used. The CU′/CD′ signals are inputs to a charge pump (CP) 14 when an intervening switch 26 is in a “pass-through” state (that is, CU=CU′ and CD=CD′). As known in the art, the CU and CD charge pump inputs are mutually exclusive, and the duration of a pulse in each signal is proportional to a phase error detected by the PFD 12. In response to the CU or CD signal, the charge pump 14 injects positive or negative current, respectfully, into the loop filter 16. (At this point, the current source (CS) 28 is off, and the summing node 30 does not add to the CP current). The CP current charges or discharges, respectfully, a capacitor in the LF 16. The LF 16 converts the charge on this capacitor to a voltage value, which is the control input signal to the VCO 18, and which controls the output frequency of the VCO 18. The LF 16 includes a resistor, which provides a transmission zero in the LF 16 frequency response. In the embodiment depicted, the input to the divider circuit 20 is generated by a delta-sigma (ΔΣ) modulator 22, which in turn is controlled by a digital control circuit 24. During the first period of operation, such as steady-state operation, in which the analog control loop controls the VCO 18 inputs, the digital control circuit 24 simply provides a constant Frequency Control Word to the ΔΣ modulator 22, which responsively outputs a bitstream to the divider 20 implementing an integer, and optionally also a fractional, division number. During the first period of operation, such as during steady-state operation, the analog control loop thus comprises the PFD 12, CP 14, LF 16, VCO 18, and frequency divider circuit 20.

[0052] When the digital control circuit 24 detects a significant change in the commanded Frequency Control Word, indicating a desired change in the output frequency of the hybrid PLL 10, a digital control loop takes control for a second period of operation, such as to effect very fast frequency changes. Depending on the direction of frequency change (up or down), the digital control circuit 24 controls the switch 26 to substitute, for the CU′ and CD′ PFD outputs, one of two sets of mutually exclusive fixed values, whereby one of the signals is tied high, and the other is tied low. In this case, either the CU or CD signal is constantly asserted, and the other is off. This forces the CP 14 to generate the maximum current, in a positive or negative sense, respectively, to the integrating capacitor in the LF 16, for the fastest possible charge or discharge of the capacitor. This, in turn, drives the VCO 18 input at the maximum possible rate, to effect the fastest change in VCO output frequency. In some embodiments, the digital control circuit 24 may also activate an optional current source (CS) 28, which provides yet more current to be summed with the CP 14 output at the summing node 30. The CS 28 may be unidirectional or bidirectional, depending on whether the additional speed in the frequency change is required in only one direction, or in both directions. The digital control circuit 24 also controls a switch in the LF 16, in parallel with the resistor. The control circuit 24 may thus effectively remove the resistor during second period of operation, such as frequency changes, leaving the LF 16 with a purely capacitive response and no transmission zero, which will minimize transients at the ends of the second period of operation. During the digital control loop duration, the tuning voltage presented to the VCO 18 increases or decreases linearly, as the LF 16 capacitor is charged or discharged by a constant current.

[0053] Two aspects are important to consider during the second period of operation, such as fast frequency changes under the digital control loop. The first is that the VCO output signal frequency must be monitored so it does not overshoot or undershoot the target frequency at the end of the charging, which would lead to increased settling time. The second is that, at least toward the end of the frequency change, the phase of the divided VCO output signal should match that of the reference periodic signal as closely as possible; otherwise there will also be a prolonged settling time when returning to the first period of operation, such as steady-state operation under the analog control loop. Both of these aspects are addressed, in a first control mode for the first embodiment, by making the divided VCO output signal phase track that of the reference period signal throughout the frequency transition. This is accomplished by monitoring the phase error output by the PFD 12.

[0054] To enable the digital control circuit 24 to monitor the PFD 12 outputs, a time to digital conversion (TDC) circuit 32 is enabled. The TDC 32 receives the PFD 12 outputs, and provides the digital control circuit 24 with digital values of the widths of the CU′ and CD′ pulses. The digital control circuit 24 monitors the TDC 32 outputs, and controls the division number of the frequency dividers to minimize the detected phase error. During the second period of operation, such as during frequency changes, the digital control loop thus comprises the ΔΣ-modulator 22, frequency divider 20, PFD 12, TDC 32, and digital control circuit 24. In this manner, when the division number (integer and fractional parts) has reached the target, a measurement indicates that the CP 14 charging has reached the target and that it can stop. The LF 16 capacitors then hold the desired charge, the LF 16 outputs the desired VCO control input signal, and the divided VCO output signal is in phase with the reference periodic signal. The hybrid PLL 10 may then return to analog control, with a minimum of settling transient to reach the first period of operation, such as steady-state operation at the new frequency.

[0055] Alternatively, in a second control mode for the first embodiment, the second period of operation, such as a frequency change, is a two-step operation, wherein the frequency and phase are controlled separately. During a frequency control step, the LF 16 is charged until the voltage of the VCO control input signal reaches a value close to that corresponding to the desired frequency. To determine when that condition is met, and the charging should be stopped, the TDC 32 outputs are monitored. The desired frequency is set by the Frequency Control Word, which sets both the integer and fractional part of the frequency division number. Applying this frequency division, when the target frequency is reached, the signals from the PFD 12 will be constant from sample to sample. The TDC 32 outputs are thus monitored for providing minimum (or zero) difference between two or more consecutive samples, after which the frequency ramping step is stopped.

[0056] When applying the frequency division number, the new integer value is set directly in the frequency divider 20. However, since the fractional part is obtained through the ΔΣ-modulator 22, a hop from one value to another cannot be made directly, and the ΔΣ-modulator 22 takes additional time before reaching steady-state and converging to the new desired fractional part. In order to converge the fractional part to the new value faster, the ΔΣ-modulator 22 input can be decreased or increased (based on which value—old or new—is greater) proportionally with the difference between the new value and an average of the ΔΣ-modulator 22 output over multiple cycles. For example, in one embodiment a 63-cycles average is used. This average is obtained as the sum of the values ‘1’ in a 63-bit shift register which samples the ΔΣ-modulator 22 output. It is important that the fractional part converges to the desired value before the end of the frequency control step to obtain good frequency accuracy. This is enabled by configuring both the current in the CS 28 (which changes the frequency ramp rate) and the multiplying factor for the ΔΣ-modulator 22 input change (which changes the ΔΣ-modulator 22 output convergence speed).

[0057] During this step, in one implementation, one TDC 32 is used to monitor the pulse length of the CU′-R or CD′-R signals generated by the PFD 12, which is triggered on the rising edges of the reference periodic signal V.sub.REF and divided VCO output signal V.sub.DIV (TDC-R signal in FIG. 3). Alternatively, in another implementation, the maximum slope of the change in VCO output frequency can be doubled by using a second TDC 32, which monitors the pulse length of the charge up or charge down signals CU′-F or CD′-F generated by a second PFD 12, which is triggered on the falling edges of the reference periodic signal V.sub.REF and divided VCO output signal V.sub.DIV (TDC-F signal in FIG. 3). In the first implementation, the values read from the single TDC 32 must be equal over four consecutive rising edges. In the second implementation, the values read on the two TDCs 32 (having the same resolution) must be equal over four consecutive edges (both rising and falling). Note that for all the simulation results presented in this disclosure, a 6-bit resolution was used for the TDC 32. In the following discussion, the second implementation is described, employing two TDCs 32 and two PFDs 12.

[0058] FIG. 2A depicts the condition where the frequency ramping should stop. The upper curve is the reference periodic signal V.sub.REF (i.e., the frequency target), the frequency of which is constant. The lower curve is the divided VCO output signal V.sub.DIV, the frequency of which is changing (decreasing, in this example) due to a forced continuous “pulse” of CU/CD, and possibly additional current from a CS 28. In the center of the figure, for half-cycle T.sub.0, the frequencies of the two signals are equal, and the ramping step should stop. Because the frequency of the divided VCO output signal V.sub.DIV is higher to the left, and lower to the right of T.sub.0, the zero crossings to the left and right will deviate (in opposite directions) by t.sub.D. FIG. 2A depicts the periodic reference signal V.sub.REF and divided VCO output signals V.sub.DIV—that is, the inputs to the PFDs 12—to explain the frequency ramping and its termination detection. The TDCs 32 receive the CU′-R/CD′-R and CU′-F/CD′-F signals output by the respective PFDs 12, wherein differences in timing between respective edges of the periodic signals is indicated by the lengths of the pulses, which the TDCs 32 convert to digital values. The digital control circuit 24 then calculates the relative edge timings based on these values. If the signal edge timing deviations to depicted in FIG. 2A are less than the resolution of the TDCs 32, they will not be detected. Accordingly, the resolution of the TDCs 32 impacts the maximum frequency ramping rate, or slope, that can be employed for a given design. To ascertain this slope, the following equations 1-5 were developed, assuming the ideal case where the edge timing deviations to precisely correspond to the TDC 32 resolution (i.e., the value of the LSB). N is the (same) number of bits in each TDC 32, and f.sub.ref is the frequency of the reference periodic signal.

[00001]$\begin{array}{cc}{t}_D=\frac{1}{2^N-1}.Math.T_0=\frac{1}{2^N-1}.Math.\frac{1}{2.Math.f_{\mathrm{ref}}}& \left(1\right)\end{array}$$\begin{array}{cc}{T}_1=T_0-t_D=\frac{1}{2.Math.f_{\mathrm{ref}}}.Math.\left(1-\frac{1}{\left(2^N-1\right)}\right)& \left(2\right)\end{array}$$\begin{array}{cc}{T}_2=T_0+t_D=\frac{1}{2.Math.f_{\mathrm{ref}}}.Math.\left(1+\frac{1}{\left(2^N-1\right)}\right)& \left(3\right)\end{array}$$\begin{array}{cc}\Delta f=f_1-f_2=\frac{1}{T_1}-\frac{1}{T_2}=4.Math.f_{\mathrm{ref}}.Math.\frac{2^N-1}{2^N.Math.\left(2^N-2\right)}& \left(4\right)\end{array}$

The slope of the change in VCO output frequency is then estimated as

[00002]$\begin{array}{cc}\frac{\Delta f_{\mathrm{out}}}{\Delta t}\approx \frac{N_{\mathrm{div}}.Math.\Delta f}{3.Math.T_0}=\frac{4}{3}.Math.N_{\mathrm{div}}.Math.\frac{f_{\mathrm{ref}}}{T_0}.Math.\frac{2^N-1}{2^N.Math.\left(2^N-2\right)}& \left(5\right)\end{array}$

where N.sub.div is the integer part in the frequency divider. For example, for N.sub.div=60 and f.sub.ref=40 MHz (yielding an output frequency of f.sub.out=N.sub.div*f.sub.ref=60*40 MHz=2.4 GHz), and N=8 bits, the resulting slope is

[00003]$\frac{\Delta f_{out}}{\Delta t}\approx 1\mathrm{GHz}/\mathrm{usec}.$

This is a very high value, not imposing any practical limitation in this case, as signals yielding a frequency change slope below this value may be reliably detected. Since N.sub.div and f.sub.ref are often fixed for a given application, the maximum frequency change slope, the termination of which can be accurately detected, is determined by N, the resolution of the TDCs 32. Stated differently, any required slope can be achieved by utilizing TDCs 32 having the required number of bits N. If higher resolution TDCs are used, the stopping condition could instead be that the difference between the consecutive samples is less than a threshold number, rather than being equal to zero.

[0059] FIG. 2B depicts the case for the first embodiment, where only one PFD 12—triggered on the rising edges CU′-R/CD′-R of the reference periodic signal V.sub.REF and divided VCO output signal V.sub.DIV—and one TDC 32 are used. The above analysis holds, with the exception that the time difference between two consecutive monitored edges is 2*T.sub.0=1/f.sub.ref. Hence, the resulting slope for the first embodiment is half of that calculated by equation (5) for the second embodiment. Of course, those of skill in the art may readily utilize a single PFD 12 and TDC 32, with the PFD 12 triggering on the falling edges and outputting CU′-F/CD′-F.

[0060] In real-world operating conditions, the ΔΣ-modulator 22 will create additional jitter in the divided VCO output signal, which may result in different values in the TDCs 32, from cycle to cycle. This jitter must be subtracted from to in the calculation above. In case the cycle-to-cycle jitter is very small with respect to t.sub.D, then the stop condition can be based on the monitoring of only four consecutive edges, as depicted in the example of FIG. 2. However, if the cycle-to-cycle jitter is comparable to t.sub.D, the TDC 32 resolution may be maintained as a constant and the signals compared, and the slope calculated, over a longer time period (more than four edges, the slope being proportional to the output frequency distance to the target). Alternatively, a lower resolution may be set in the TDC 32.

[0061] During the phase control step, the ΔΣ-modulator 22 is used to vary the fractional part for phase alignment (fine tuning), whereas the integer part of the division number is changed with ±1 unit, to avoid a range under-/overflow when tuning the fractional part close to the range boundaries. More generally, the integer part may be controlled over a range of more than ±1 units, to achieve even faster convergence.

[0062] During the phase control step, to control the phase through the digital control loop, the CU/CD signals are switched-off from the charge pump. In the first embodiment, this may be accomplished by controlling the switch 26 to select CU=0 and CD=0. This suppresses the CP 14 from providing any charge/discharge current to the LF 16. Rather, all control of the output signal phase is performed by the digital control circuit 24 controlling the integer and fractional parts of the division number, based on the timing of CU′/CD′ signals from the PFD 12, as quantized by the TDCs 32. Alternatively, the charge pump can be disabled by suppressing the CU′ and CD′ signals in the PFD 12, based on the state of the digital control loop (see FIG. 8B, discussed in greater detail below).

[0063] FIG. 3 depicts a simulation of the hybrid PLL 10 of FIG. 1 during the frequency step of the second period of operation, such as a frequency change, according to the second control mode. Values of the digital buses in FIG. 3 are expressed in hexadecimal. Based on a new received Frequency Control Word, a large downwards frequency step is detected. In response, the digital control loop is activated, as indicated by the STATE variable going from state 2, indicating the first period of operation, such as steady-state operation, with analog control loop, to state 0, indicating a downward frequency change (state 1 indicates an upward frequency change). Both the integer part INT and fractional part FRAC of the frequency divider are set. The digital control circuit 24 configures the switch 26 to select the fixed inputs driving the down, or CD signal to 1 (not pictured, but CU=0). This causes the output frequency f.sub.out to begin linearly decreasing. During the second period of operation, such as the frequency change, the ΔΣ-modulator 22 input signal DS-IN is changing based on the difference between the new fractional value FRAC and an average AVG of the ΔΣ-modulator 22 output DS-OUT over multiple cycles. This also increases the rate of ‘1’ values of DS-OUT. The two TDCs 32 monitor the phase difference between the divided VCO output signal V.sub.DIV and reference periodic signal V.sub.REF on the rising (TDC-R) and falling (TDC-F) edges, respectively. Convergence is achieved when the ΔΣ-modulator 22 output average AVG is equal to the fractional part of the divider FRAC, and the rising and falling edges TDC-R, TDC-F are equal over two reference periodic signal periods (four consecutive edges). At this time, STATE goes to 3, which corresponds to the phase control step, during which the charge up/down signals CU, CD are switched-off in the switch 26.

[0064] FIG. 4 depicts a simulation of the hybrid PLL 10 of FIG. 1 during the subsequent phase step of the second period of operation, such as a frequency change, according to the second control mode. During the phase step, the residual phase difference between the divided VCO output signal V.sub.DIV and the reference periodic signal V.sub.REF is minimized, so that when the first period of operation, such as steady-state operation, is resumed (with analog control loop), there will be a minimum transient to lock the phase. This is done by controlling the input of the ΔΣ-modulator 22 (the difference between the fixed FRAC value and AVG, the running average of DS-OUT), which then controls the fractional division number, and as a result also the phase difference. As described above, the CD signal is forced to 0 during the phase control step, so that the digital control loop controls the phase only by manipulation of the fractional division number. Also, the integer division number INT may be controlled to avoid an overflow, or to speed up the phase step. When the phase has been minimized, TDC-R is close to 0. Note that the ΔΣ-modulator 22 input signal DS-IN requires additional time to converge (FIG. 4). After that, the hybrid PLL 10 resumes the first period of operation, such as steady-state operation (with analog control loop), as indicated by the STATE changing to 2.

[0065] FIG. 5 depicts the complete second period of operation, such as a frequency change, for the hybrid PLL 10 of FIG. 1, compared to the operation of a prior art PLL. The prior art PLL is prone to cycle slips, which prolong the locking time. As FIG. 5 indicates, the digitally controlled frequency change procedures of embodiments of the present invention drastically reduce the locking time, avoiding both cycle slips and slow linear settling.

[0066] Referring again to FIG. 1, after the target frequency is reached and phase is locked, the TDCs 32 and CS 28 are disabled; the switch 26 is configured to pass CU′ and CD′ from the PFD 12 directly to the CP 14, and the LF 16 resistor bypass switch is turned off. The signal sent to the ΔΣ modulator 22 and frequency divider 20 is constant—representing the value of the (new) Frequency Control Word—and is no longer controlled by the digital control circuit 24. The hybrid PLL 10 now operates in the first period of operation, such as a steady-state mode, with an analog control loop, as a conventional PLL.

Second Embodiment

[0067] FIG. 6A depicts a hybrid PLL 34A according to a second embodiment. The hybrid PLL 34A operates in a first period of operation, such as steady-state, according to an analog control loop, as described above with respect to hybrid PLL 10. The VCO 18 generates a periodic output signal, the frequency of which is determined by a tuning voltage applied to the VCO 18 input. The frequency divider circuit (DIV) 20 divides the frequency of the VCO output signal by a controlled division factor, and the divided VCO output signal V.sub.DIV is provided to the PFD circuit 12 (the pulse suppression circuit PS 36, described below, acting in “pass through” mode in the analog control loop). The PFD 12 outputs charge pump control signals CU/CD. In response to these signals, the CP 14 injects the appropriate current into the loop filter 16 (the CS 28 is off in the first period of operation, such as during steady-state mode). The LF 16 converts the charge on a capacitor to a voltage value, which is the input to the VCO 18, and which controls the output frequency of the VCO 18. A switch bypassing an LF 16 resistor is off. The ΔΣ modulator 22 controls the divider 20 based on an applied Frequency Control Word.

[0068] The digital control circuit, which controls the hybrid PLL 34A during a second period of operation, such as frequency changes, operates differently to the hybrid PLL 10 embodiment depicted in FIG. 1. In this embodiment, there is no switch interposed between the PFD 12 and CP 14. One benefit of this configuration results from the fact that, during the first period of operation, such as steady-state operation, when there are only minor phase differences between the output signal and the reference periodic signal, the CU/CD pulses are very short. A switch, such as switch 26 in FIG. 1, in the signal path may degrade the quality of such short pulses. Rather, in this embodiment, to force the pulses on CU/CD to approach 100%, a pulse suppression (PS) circuit 36 is added between the divider 20 and the PFD 12. By suppressing one cycle of the reference periodic signal V.sub.REF, the PFD 12 CD output will go from very short pulses, as in the first period of operation, such as steady-state operation, to near-100% CD pulses. To avoid precisely hitting the limit, at 100%, the divided VCO output signal V.sub.DIV should be retarded by momentarily increasing the division number. To accomplish this, an adder 21 is inserted between the ΔΣ-modulator 22 and the frequency divider 20, to add in a value provided by the digital control circuit 24. Similarly, suppressing one cycle of the divided VCO output signal V.sub.DIV and momentarily reducing the division number, will force the CU pulses to near-100% duty cycle.

[0069] As described with respect to the first embodiment of FIG. 1, the additional current source CS 28 can be enabled, and the switch in the LF 16 is preferably enabled to minimize the settling time after the frequency step. The digital control loop will then regulate towards the initial value of the TDC 32, where the pulse length is close to 100%, not towards zero as in the first embodiment. Note that in neither embodiment is any normalization of the TDC 32 response necessary, for instance towards the output period. Apart from controlling towards long CU/CD pulses rather than short, the operation is similar to that of the first embodiment.

[0070] When the target frequency has been reached, a pulse is suppressed on the opposite of the two periodic signals feeding the PFD 12, and the opposite decrease/increase of the division number is performed. The PFD 12 then returns to generating short CU/CD pulses; the PS 36, TDC 32, and CS 28 are disabled; the LF 16 switch is opened; and the hybrid PLL 34A returns to the first period of operation, such as steady-state operation, at the new frequency (under analog loop control) with a minimum of settling time.

[0071] In a first control mode, as described above, the phase of the divided VCO output signal V.sub.DIV is maintained as close as possible to the phase of the reference periodic signal V.sub.REF throughout the second period of operation, such as a frequency change operation. In this mode, the signals CU′ and CD′ sent to the TDC 32 are identical to CU and CD signals sent to the CP 14, so a conventional PFD 12 is used, with a single set of output signals. As also discussed above, if the PFD 12 monitors rising edge timing of the periodic signals V.sub.REF and V.sub.DIV, a second PFD may also be used, to additionally monitor the falling edges (or vice versa).

[0072] In a second control mode, as also described above, the second period of operation, such as a frequency change, is implemented as a two-step operation, wherein the frequency and phase are controlled separately. Due to differences in the circuits required to implement this second control mode, a slightly different hybrid PLL 34B is depicted in FIG. 6B. During a frequency control step, the LF 16 is charged until the voltage of the VCO control input signal reaches a value close to that corresponding to the desired frequency. The desired frequency is given by the Frequency Control Word, which sets both the integer and the fractional part of the division number. The new fractional value is set directly at the start of the frequency control step. In the frequency control step, the only differences with respect to the second control mode of the first embodiment described above is that the CU or CD pulses are close to 100% duration (not completely 100%) and the integer division number is controlled in order to maintain the CU or CD pulses close to 100%, while avoiding an overflow of the PFD1 12, which would result in zero output.

[0073] The phase control step proceeds as described above for the phase control step of the first embodiment, with the fractional and/or the integer part of the division number being controlled to achieve phase convergence. In particular, the ΔΣ-modulator 22 input is decreased or increased proportionally with the difference between the new output and an average of the ΔΣ-modulator 22 output over multiple cycles (such as 63 cycles, e.g., by counting the number of 1 values in a 63-bit shift register). As discussed above, during the phase control step, to control the phase through the digital control loop, the CU/CD signals into the charge pump must be disabled. This may be accomplished by modifying the PFD1 12 to output zero on both outputs when the digital control loop is active, such as by detecting and acting on a particular value of a state machine. FIG. 8 depicts one circuit to accomplish this, for the particular case where STATE [1,0]=11. This circuit was used for the simulations depicted in FIGS. 7 and 9-12. Alternatively, the PS 36 may monitor the state and suppress both periodic signal outputs, which will cause the PFD1 12 to output zero CU/CD signals.

[0074] However, if the CU/CD outputs of the PFD1 12 are suppressed, the digital control loop is unable to monitor the relative timing of the periodic signals V.sub.REF and V.sub.DIV from it. Accordingly, FIG. 6B depicts a hybrid PLL 34B of the second embodiment suited for use where the second control mode (separate frequency and phase adjustments) is employed. In this implementation, the PFD1 12 provides to the CP 14, during the frequency control step, CU/CD pulses that are forced to near 100% duty cycle by the pulse suppression circuit 36, as described. During the phase control step, when the PFD1 12 suppresses CU/CD outputs, a second phase frequency detector PFD2 35 also receives the periodic signals V.sub.REF and V.sub.DIV, and outputs CU′/CD′ signals indicative of their relative edge timings to the TDC 32. In the case that both rising and falling edges are monitored, two PFD2s 35 and TDCs 32 are utilized.

[0075] The phase control step ends when the phase error for, e.g., four consecutive edges (2 positive and 2 negative) are equal to zero, or below a threshold. The fractional part preferably converges to the desired value before the end of the phase control step to obtain good frequency accuracy. This is enabled by configuring both the current in the CS 28 (which changes the frequency change rate and thereby the time available for convergence of the ΔΣ-modulator 22 in the frequency control step) and the multiplying factor for the ΔΣ-modulator 22 input change (which changes the ΔΣ-modulator 22 output convergence rate).

[0076] During the frequency control step, the two TDCs 32 monitor both the rising and the falling edge differences in one of the two directions, based on which signal (CU or CD) is active. Then, for the loop filter charging to stop and the frequency control step to end, the values output by the two TDCs 32 must be equal (or have a variation below a threshold) over, e.g., four consecutive edges. See FIG. 2, equations 1-5, and the accompanying discussion, above. In addition, since the integer part of the division number is used to control the duty cycle of the CU/CD pulses (and they are not fixed, as in the second control mode of the first embodiment), it is also required that the integer part of the division number has reached the desired target value before the frequency ramping is stopped.

[0077] During the phase control step, the ΔΣ-modulator 22 is used to vary the fractional part for phase alignment (fine tuning), whereas the integer part of the division number is changed with ±1 unit, to avoid a range under-/overflow when tuning the fractional part close to the range boundaries.

[0078] FIG. 7 depicts a simulation of the hybrid PLL 34B of FIG. 6B during the frequency step of a second period of operation, such as a frequency change, according to the second control mode. Based on a new received Frequency Control Word, a large downwards frequency step is detected. In response, the digital control loop is activated, as indicated by the STATE variable going from state 2, indicating the first period of operation, such as steady-state operation, with analog control loop, to state 0, indicating a downward frequency change (state 1 indicates an upward frequency change). Both the integer part INT and fractional part FRAC of the frequency divider are set. In this case, one cycle of the reference periodic signal V.sub.REF is suppressed, which causes the PFD1 12 to generate CD pulses at close to (but not reaching) 100% duty cycle. At the same time, there is a momentary change in the integer part INT of the division number, to avoid an overflow. Two TDCs 32—one for the rising edge, and one for the falling edge—monitor for frequency convergence, converting the outputs of two PFD2s 35. Each TDC 32 monitors the active one of the CU and CD signals (depending on the direction of the frequency change), in this case the DC signal. As a result, the CD signal is close to 100% duty cycle, and the output frequency f.sub.out decreases nearly linearly.

[0079] Note that, similar to the first embodiment, during this step the ΔΣ-modulator 22 input DS-IN is changing based on the difference between the new fractional value FRAC and an average of the ΔΣ-modulator 22 output DS-OUT over multiple cycles. This also increases the rate of ‘1’ values at the ΔΣ-modulator 22 output DS-OUT. The two TDCs 32 monitor the phase difference between the divided VCO output signal V.sub.DIV and reference periodic signal V.sub.REF in the given direction on the rising TDC-R and falling TDC-F edges, respectively. Convergence is achieved when both INT division number and average fractional portion of the division number AVG have reached the target value, and the outputs of the two TDCs 32, TDC-R and TDC-F, are equal over, e.g., two clock reference periods (four consecutive edges). At this time, STATE goes to 3, indicating the phase control step has begun, and a pulse of the divided VCO output signal V.sub.DIV is suppressed in order to return to short pulses on CU/CD.

[0080] Note that the resolution of the TDC 32 in the second embodiment of the hybrid PLL 34A, 34B (FIGS. 6A, 6B) is the same as used in the first embodiment (FIG. 1). In a straightforward implementation, for close to 100% duty cycle pulses, a 7-bit TDC 32 would be required to cover the full T.sub.ref=1/f.sub.ref time period. However, this is achieved with a 6-bit TDC 32 covering only T.sub.ref/2. FIG. 9A depicts operation of the TDC 32 during the second period of operation, such as fast frequency changes, for the first embodiment. In this case, 6 bits is sufficient resolution because the duty cycle of the CU′ and CD′ signals is a maximum of 50%. As depicted in FIG. 9B, during the second period of operation, such as fast frequency changes, for the second embodiment, when the pulses are close to 100% duty cycle, the first MSB (corresponding to 50% duty-cycle) is dropped. The TDC 32 then converts only the time period in excess of T.sub.ref/2. This means that now the maximum remainder time period to be converted is less than T.sub.ref/2. This operation is equivalent to a start of the conversion on the falling edge of the divided VCO output signal V.sub.DIV or reference periodic signal V.sub.REF.

[0081] FIG. 10 depicts a simulation of the hybrid PLL 34B of FIG. 6B during the phase control step of a second period of operation, such as a frequency change, according to the second control mode. At the beginning of the phase control step, one cycle must be suppressed from the opposite signal as that suppressed in the frequency control step, in this case, on the divided VCO output signal V.sub.DIV. This returns the PFD2 35 outputs to short pulses, to quickly minimize the residual phase. The minimization of residual phase is done by controlling the input of the ΔΣ-modulator 22, which then controls the fractional part FRAC of the division number, and as a result also the phase difference between the divided VCO output signal V.sub.DIV and the reference periodic signal V.sub.REF As compared to the second control mode for the first embodiment (of FIG. 1), at the beginning of the phase control step, the phase difference is much smaller, making it easier/faster to converge. This is because maintaining close to 100% duty-cycle CU/CD pulses during the frequency control step corresponds to very small phase difference after suppressing the opposite pulse type. Consequently, the PFD2 35 should provide near-zero pulses, especially if the division ratio is also momentarily increased/decreased in addition to the change performed at the beginning of the frequency control step. Therefore, the phase is recovered faster and the input control voltage for the ΔΣ-modulator 22 DS-IN is already close to convergence. Then the hybrid PLL 34B can quickly resume the first period of operation, such as steady-state operation, under an analog control loop (STATE=2).

[0082] FIG. 11 depicts the complete second period of operation, such as a frequency change, for the hybrid PLL 34A of FIG. 6A or hybrid PLL 34B of FIG. 6B, compared to the operation of a prior art PLL. As noted above, the prior art PLL is prone to cycle slips, which prolong the locking time. As FIG. 11 indicates, the digitally controlled frequency change procedures of embodiments of the present invention drastically reduce the locking time, avoiding both cycle slips and slow linear (analog) settling.

[0083] FIG. 12 shows a comparison of the second period of operation, such as a fast frequency change, for the first embodiment (hybrid PLL 10, FIG. 1) and second embodiment (hybrid PLL 34A, 34B, FIGS. 6A, 6B), for the same CP 14 current. The frequency change for the second embodiment is only slightly slower in the frequency ramping phase, due to non-100% duty cycle CD pulses.

Third Embodiment

[0084] FIG. 13 depicts a third embodiment of the present invention, which also utilizes a digital control loop during the second period of operation, such as frequency changes, to achieve very fast frequency hops. This embodiment combines the 100% duty cycle charge pump input feature of the first embodiment, and the pulse suppression technique of the second embodiment, to provide 100% duty cycle on charge pump 14 input signals, while avoiding short pulse switching in the direct path. As described above for the hybrid PLL 34B, an additional PFD2 40 is provided for the digital control loop.

[0085] In the hybrid PLL 38, the PS 36 suppresses all cycles of either the divided VCO output signal V.sub.DIV or the reference periodic signal V.sub.REF This forces the first PFD1 12 to generate a CU or CD signal having 100% duty cycle (i.e., it is continuously on), thus causing the CP 14 to inject the maximum charging or discharging current, respectively, into the LF 16. Note that a second PFD2 40 receives the divided VCO output signal V.sub.DIV and reference periodic signal V.sub.REF directly—without any cycle suppression. The digital control loop operates on this input.

[0086] In the first operating mode, as described above, the phase of the divided VCO output signal is synchronized with the phase of the periodic reference signal throughout the second period of operation, such as a frequency change. The digital control circuit 24 controls the division number (integer and fractional parts) sent to the ΔΣ-modulator 22 in response to the pulse lengths of the CU′/CD′ signals from the TDC 32, to minimize or eliminate the pulses, corresponding to minimizing or eliminating the phase error between the V.sub.DIV and V.sub.REF signals. The target frequency has been reached when the frequency division number has reached the target value.

[0087] Similarly to the first and second embodiments, the third embodiment also operates in a second operating mode, with separate frequency and phase control steps. During the frequency control step, in a downward (upward) frequency hop, the PS 36 will effectively cancel all V.sub.REF (V.sub.DIV) pulses. As a result, the first PFD1 12 will output a constant CD=1 (CU=1) which will cause a linear frequency change, as described above. The CD′/CU′ outputs of the second PFD2 40, which receives both V.sub.REF and V.sub.DIV with no cycle suppression, are quantified by the TDCs 32, and monitored by the digital control circuit 24 to ascertain when the frequency control step should terminate (equal durations between edge transitions over at least two cycles). During a subsequent phase control step, the charge pump inputs are suppressed, and the digital control circuit 24 controls works to minimize the phase error between the V.sub.DIV signal and the V.sub.REF signal by controlling the fractional (and integer) portion of the division number, in response to the CD′/CU′ outputs of the second PFD2 40, as quantified by the TDCs 32.

[0088] Although the use of two PFDs 12, 40 slightly increases silicon area, they do not impact power consumption, as they operate at different times. The first PFD1 12 only dynamically switches during the first period of operation, such as steady-state operation of the hybrid PLL 38 (under analog control loop); during this time the second PFD2 40 is disabled. Conversely, the second PFD2 40 only operates during the second period of operation, such as fast frequency changes (under digital control loop); during this time, the PS 36 suppresses all pulses of one of the two periodic signals, so the first PFD1 12 does not switch, but rather outputs either CD=0 and CU=1, or CD=1 and CU=0 (or, in the phase control step of the second control mode, both CU=0 and CD=0).

[0089] The additional CS 28 is optionally activated only during the frequency change. The LF 14 switch must be activated at the beginning of the frequency change, and deactivated before resuming the first period of operation, such as steady-state operation. In one embodiment, the LF 14 switch is divided in several unitary cells, which are switched off successively toward the end of the phase control step, when the phase difference is small, in order to minimize spikes in the VCO control voltage. Such spikes would otherwise translate to output frequency glitches.

[0090] FIG. 14 depicts a simulation of the hybrid PLL 38 of FIG. 13 during the frequency step of a second period of operation, such as a frequency change, according to the second control mode. The process is similar to that described above with respect to the first embodiment. Convergence is achieved when the average fractional portion of the division number AVG has reached the target value FRAC, and the rising and falling edges are equal over four consecutive edges of the reference periodic signal V.sub.REF See FIG. 2, equations 1-5, and the accompanying discussion, above. At this time STATE=3 which corresponds to the phase control step, and the CU/CD signals are deactivated. As described above, this can be implemented either in the first PFD1 12 or the PS 36. For the simulation results presented in FIGS. 14-17, the PS 36 method to switch off the CU/CD signals was used. As stated above, when STATE=3, this mechanism enables a continuous suppression of all cycles of both the divided VCO output signal V.sub.DIV and reference periodic signal V.sub.REF, in order to generate zero values on the CU and CD signals going to the CP 14, which will no longer provide charge/discharge current to the LF 16.

[0091] However, in a straightforward implementation, if the PFD1 12 is in state CU=0, CD=1 (or CU=1, CD=0) and the mechanism begins to suppress continuously all cycles of both the divided VCO output signal V.sub.DIV and reference periodic signal V.sub.REF, the PFD1 12 will remain in its previous state, and not reset to CU=0, CD=0. As depicted in FIG. 15, in order to enable a correct start-up, immediately after STATE transitions to 3, if the PFD1 12 is in state CU=0, CD=1 (or CU=1, CD=0), then all pulses of V.sub.DIV (or V.sub.REF) are continuously suppressed, but it is necessary to introduce one pulse of V.sub.REF (or V.sub.DIv) before starting to continuously suppress all pulses of V.sub.REF (or V.sub.DIv). Thus, the PFD1 12 will detect a rising edge of V.sub.REF (or V.sub.DIv), which determines a reset of CU and CD outputs. Then, while all pulses of both clock signals are suppressed, the PFD1 12 will not change state, and will output CU=0 and CD=0.

[0092] FIGS. 16A and 16B depict a simulation of the hybrid PLL 38 of FIG. 13 during the phase control step of a second period of operation, such as a frequency change, according to the second control mode. As much of the residual phase as possible is canceled by controlling the input DS-IN of the ΔΣ-modulator 22, which then controls the fractional portion of the division number with average AVG, and as a result also the phase difference between the divided VCO output signal V.sub.DIV and reference periodic signal V.sub.REF When the phase is recovered, TDC-R is close to 0 (i.e., TDC=R=1 at 3.12 μs). Note that the input control signal DS-IN for the ΔΣ-modulator 22 requires time to reach convergence, as indicated in FIG. 16A. This is because the ΔΣ-modulator 22 tracks the phase difference proportionally—that is, the larger the phase difference, the larger the control signal. Once the phase difference is reduced, then the ΔΣ-modulator 22 input control signal DS-IN will also slowly converge, as seen in FIG. 15B, and the hybrid PLL 38 resumes the first period of operation, such as steady-state operation (STATE=2). As noted above, when the phase difference is sufficiently small, the unitary cells comprising the LF 16 switch are turned off successively, to avoid frequency glitches.

[0093] FIG. 17 depicts the complete second period of operation, such as a frequency change, for the hybrid PLL 38 of FIG. 13, compared to the operation of a prior art PLL. As noted above, the prior art PLL is prone to cycle slips, which prolong the locking time. As FIG. 16 indicates, the digitally controlled frequency change procedures of embodiments of the present invention drastically reduce the locking time, avoiding both cycle slips and slow linear (analog) settling.

[0094] Upon returning to the first period of operation, such as steady-state operation (STATE=2), the TDCs 32 are turned off, the PS 36 only acts as clock buffer, and the CS 28 is turned off (the LF 16 switch is already turned off). The signal sent to the ΔΣ modulator 22 and frequency divider 20 is constant, and represents the value of the Frequency Control Word, i.e., it is no longer controlled by the digital control loop.

Loop Filter Resistor Bypass Switching

[0095] In all three embodiments of the hybrid PLL 10, 34, 38 described above, the loop filter 16 includes a resistor, which provides a transmission zero in the LF 16 frequency response during the first period of operation, such as steady-state operation. During the second period of operation, such as a frequency change, it is desired to have the loop filter 16 purely capacitive, so that all current injected into the loop filter 16 goes to (dis)charging the loop filter capacitors. Accordingly, a bypass switch is provided to shunt the loop filter resistor to ground by the digital control loop during the second period of operation, such as frequency changes. At the end of the second period of operation, when returning to the first period of operation, such as steady-state operation, the resistor should be restored. Care must be taken in controlling the bypass switch, to avoid output frequency glitches.

[0096] FIG. 18A depicts a prior art loop filter LF 16, with a resistor R0 that provides a zero in the transfer function to advance the phase. During the second period of operation, such as a frequency change, when the analog control loop is disabled and a digital control loop controls the hybrid PLL 10, 34, 38 operation, the resistor R0 may be bypassed, as shown in FIG. 18B, making the loop filter 16 entirely capacitive. In the circuits of FIGS. 18A and 18B, the capacitors are 50 pF and 5 pF, and the resistor is 32 kΩ, placing a zero at 100 kHz. The pole is then at 1.1 MHz. This is suitable for use in a PLL with a bandwidth of, e.g., 330 kHz. A charging time of 10 μs with 5 pA was used, using the current sources indicated in the schematic. The switch transistor in FIG. 18B is implemented with 40 parallel minimum size transistors in 22 nm FDSOI technology (L=20 nm W=80 nm, MuIt=40). Resistor R1 is very large, and was added for simulation purposes only.

[0097] FIG. 19 depicts the results of simulation. A large overshoot occurs in the circuit of FIG. 18A, with no switch to bypass the resistor. With this loop filter the VCO tuning voltage would reach the target much before the capacitors were fully charged, and the charging would be terminated prematurely. By using the switch in the circuit of FIG. 18B, however, the simulated behavior is very close to ideal, with no overshoot to interfere with control of the VCO tuning voltage. The excellent switch performance results from the use of advanced 22 nm FDSOI technology, and also very good conditions for a switch transistor, with signals close to ground voltage.

[0098] Additionally, the loop filter switch should be turned off during the phase control step, and not at the return to the first period of operation, such as steady-state operation. Turning on/off the LF 16 switch causes small spikes in the VCO tuning voltage, which translate to output frequency glitches. If the LF 16 switch is turned off at the end of the phase control step, it may cause a sudden frequency change, or phase bump, resulting in longer convergence time after the return to the first period of operation, such as steady-state operation. In one embodiment, this is avoided by turning off the LF 16 switch during the phase control step. If the switch is completely turned off during one clock period, there is a sudden frequency glitch as described, but there is still time to recover the output frequency before reaching the end of the phase control step.

[0099] In another embodiment, the LF 16 switch is implemented as several identical smaller switches with the same total effective size. Each of these switches is then turned off during successive clock cycles (or other time periods). In this case, the impact of the frequency glitches is even lower, reducing the time needed to recover the correct target frequency.

[0100] FIGS. 20A, 20B, and 20C depict the differences in output frequency f.sub.out for three different strategies of turning off the LF 16 resistor bypass switch. In FIG. 20C, the switch is turned off at the end of the phase control step, resulting in a negative glitch in the output frequency. In FIG. 20B, the switch is turned off midway through the phase control step. This also produces a glitch, but the digital control loop has time to recover. Finally, FIG. 20A depicts a plurality of switch components being successively turned off over a duration of the phase control step, which eliminates any noticeable glitch in the output frequency.

[0101] FIG. 21 shows the effect of not having a bypass switch at all. When the LF 16 resistor remains in the circuit, a large frequency undershoot results that may cause the frequency control algorithm to fail, as it would stop charging the loop filter too early. In contrast, by removing the resistor with the bypass switch, the frequency change is not only smooth, but completes much sooner.

Method and Wireless Network Apparatus Descriptions

[0102] FIG. 22 depicts a method 100 of controlling a hybrid PLL 10, 34, 38. As described above, the hybrid PLL 10, 34, 38, comprises at least a VCO 18, a frequency divider circuit 20, a PFD 12, a LF 16 including a capacitor, and a CP 14 configured to charge or discharge the LF capacitor in response to the duty cycle of a CU or CD signal output by the PFD 12. During a first period of operation, such as steady-state operation (block 102), the LF 16 is controlled to generate the VCO control input via an analog control loop (block 104). When a change in commanded frequency is detected, a second period of operation, such as a frequency change, is initiated (block 106). Until the new frequency is achieved (with phase synchronization) (block 106), the LF 16 is controlled to generate the VCO control input signal by controlling the charge pump, in response to timing of the PFD 12 outputs, via a digital control loop (block 108). When the new frequency is achieved (block 106) and the output is phase-synchronized to the reference periodic signal, then the first period of operation, such as steady-state operation, is resumed (blocks 102, 104).

[0103] Although the hybrid PLL 10, 34, 38 of embodiments of the present invention may be advantageously used wherever an agile, high-speed, phase-accurate periodic signal generator is required, one application is generating periodic signals, such as a Local Oscillator (LO) signal, for RF communication transceiver circuits, particularly in communication protocols utilizing frequency hopping. In particular, the hybrid PLL 10, 34, 38 is suited for use in nodes in a wireless communication network, such as a base station and/or User Equipment (UE).

[0104] FIG. 23 depicts a base station 50 operative in a wireless communication network. As those of skill in the art are aware, a base station 50 is a network node providing wireless communication services to one or more UEs in a geographic region (known as a cell or sector). The base station 50 in LTE is called an e-NodeB or eNB, and in NR is referred to as a gNB; however the present invention is not limited to these protocols. A base station 50 includes radio circuits, such as a transceiver 52, one or more antennas 54, and the like, to effect wireless communication across an air interface to one or more UEs. The transceiver 52 includes one or more hybrid PLLs 10, 34, 38 according to embodiments of the present invention. As those of skill in the art are aware, and as indicated by the continuation lines in the antenna feed line of FIG. 23, the antenna(s) 54 may be physically located separately from the base station 50, such as mounted on a tower, building, or the like. The base station 50 further includes processing circuitry 56; memory 58, and communication circuits 62 configured to exchange data with other network nodes. Although the memory 58 is depicted as being separate from the processing circuitry 56, those of skill in the art understand that the processing circuitry 56 includes internal memory, such as a cache memory or register files. Those of skill in the art additionally understand that virtualization techniques allow some functions nominally executed by the processing circuitry 56 to actually be executed by other hardware, perhaps remotely located (e.g., in the so-called “cloud”). According to embodiments of the present invention, the memory 58 is configured to store, and the processing circuitry 56 configured to execute, software 60 which when executed is operative to control one or more hybrid PLLs 10, 34, 38. In particular, the software 60 is configured to execute the method 100 described herein. Alternatively, the method 100 may be executed by digital control circuits 24 within the hybrid PLL 10, 32, 34.

[0105] FIG. 24 depicts a UE 70 operative in a wireless communication network. As used herein, a UE 70 is any type of device capable of communicating with a base station 50, another UE 70, or other network node, over radio signals. A UE 70 may therefore refer to a machine-to-machine (M2M) device, a machine-type communications (MTC) device, a Narrowband Internet of Things (NB IoT) device, etc. Despite its name, a UE 70 does not necessarily have a “user” in the sense of an individual person owning and/or operating the device. A UE 70 may also be referred to as a radio device, a radio communication device, a wireless communication device, a wireless terminal, or simply a terminal—unless the context indicates otherwise, the use of any of these terms is intended to include device-to-device UEs or devices, machine-type devices, or devices capable of machine-to-machine communication, sensors equipped with a radio network device, wireless-enabled table computers, mobile terminals, smart phones, laptop-embedded equipped (LEE), laptop-mounted equipment (LME), USB dongles, wireless customer-premises equipment (CPE), etc. In the discussion herein, the terms machine-to-machine (M2M) device, machine-type communication (MTC) device, wireless sensor, and sensor may also be used. It should be understood that these devices may be UEs 70, but may be configured to transmit and/or receive data without direct human interaction.

[0106] A UE 70 as described herein may be, or may be comprised in, a machine or device that performs monitoring or measurements, and transmits the results of such monitoring measurements to another device or a base station 50. Particular examples of such machines are power meters, industrial machinery, or home or personal appliances, e.g. refrigerators, televisions, personal wearables such as watches etc. In other scenarios, a wireless communication device as described herein may be comprised in a vehicle and may perform monitoring and/or reporting of the vehicle's operational status or other functions associated with the vehicle.

[0107] The UE 70 includes radio circuits, such a transceiver 72 one or more antennas 74, and the like, to effect wireless communication across an air interface to one or more base stations 50 or other UEs 70. The transceiver 72 includes one or more hybrid PLLs 10, 34, 38 according to embodiments of the present invention. As indicated by the dashed lines, the antenna(s) 74 may protrude externally from the UE 70, or the antenna(s) 74 may be internal. The UE 70 also includes processing circuitry 76; memory 78; and in some embodiments, the UE 70 includes a user interface 82 (i.e., display, touchscreen, keyboard or keypad, microphone, speaker, and the like). In some embodiments, such as in many M2M, MTC, or NB IoT scenarios, the UE 70 may include only a minimal, or no, user interface 82 (as indicated by the dashed lines of block 82 in FIG. 24). According to embodiments of the present invention, the memory 76 is configured to store, and the processing circuitry 76 configured to execute, software 80 which when executed is operative to control one or more hybrid PLLs 10, 34, 38. In particular, the software 80 is configured to execute the method 100 described herein. Alternatively, the method 100 may be executed by digital control circuits 24 within the hybrid PLL 10, 34, 38.

[0108] In all embodiments described herein, the processing circuitry 56, 76 may comprise any sequential state machine operative to execute machine instructions stored as machine-readable computer programs in the memory, such as one or more hardware-implemented state machines (e.g., in discrete logic, FPGA, ASIC, etc.); programmable logic together with appropriate firmware; one or more stored-program, general-purpose processors, such as a microprocessor or Digital Signal Processor (DSP), together with appropriate software; or any combination of the above.

[0109] In all embodiments described herein, the memory 58, 78 may comprise any non-transitory machine-readable media known in the art or that may be developed, including but not limited to magnetic media (e.g., floppy disc, hard disc drive, etc.), optical media (e.g., CD-ROM, DVD-ROM, etc.), solid state media (e.g., SRAM, DRAM, DDRAM, ROM, PROM, EPROM, Flash memory, solid state disc, etc.), or the like.

[0110] In all embodiments described herein, the radio circuits may comprise one or more transceivers 52, 72 used to communicate with one or more other transceivers 72, 52 via a Radio Access Network according to one or more communication protocols known in the art or that may be developed, such as IEEE 802.xx, CDMA, WCDMA, GSM, LTE, UTRAN, WiMax, Bluetooth, or the like. The transceiver 52, 72 implements transmitter and receiver functionality appropriate to the Radio Access Network links (e.g., frequency allocations and the like). The transmitter and receiver functions may share circuit components and/or software, or alternatively may be implemented separately.

[0111] In all embodiments described herein, the communication circuits 62 may comprise a receiver and transmitter interface used to communicate with one or more other nodes over a communication network according to one or more communication protocols known in the art or that may be developed, such as Ethernet, TCP/IP, SONET, ATM, or the like. The communication circuits 62 implement receiver and transmitter functionality appropriate to the communication network links (e.g., optical, electrical, and the like). The transmitter and receiver functions may share circuit components and/or software, or alternatively may be implemented separately.

Advantages of Embodiments of the Present Invention

[0112] Embodiments of the present invention present numerous advantages over PLLs of the prior art. By operating in an analog control loop in a first period of operation, such as steady-state, the hybrid PLL 10, 34, 38 provides a low complexity architecture with tractable design effort, and which can operate at a high frequency with low power consumption and low phase noise. The time required to change frequency, such as for frequency hopping communications protocols, is dramatically reduced by using a digital control loop for a second period of operation, such as frequency changes. The digital circuitry is not utilized most of the time, and hence adds minimal power consumption and has little or no influence on spectral purity in the first period of operation, such as steady-state operation. Both digital control modes disclosed herein result in a phase synchronized signal at the end of the second period of operation, such as frequency change operation, minimizing transient and settling time upon a return to the second period of operation, such as steady-state operation. By using a small NMOS switch with minimum chip area and parasitic effects in the loop filter, the loop filter resistor is bypassed to maximize the frequency change ramp, while minimizing settling transients.

[0113] As used herein, the term “configured to” means set up, organized, adapted, or arranged to operate in a particular way; the term is synonymous with “designed to.”

[0114] The present invention may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the invention. The present embodiments are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.