DIRECT CURRENT OFFSET CALIBRATION FOR DIGITAL-TO-ANALOG CONVERSION

Abstract

Certain aspects of the present disclosure provide techniques and apparatus for digital-to-analog conversion. An example apparatus generally includes a digital-to-analog converter (DAC), an incremental analog-to-digital converter (IADC) having a first input coupled to a first output of the DAC, and a controller coupled to the DAC and the IADC. The controller is configured to determine a direct current (DC) offset associated with the DAC using the IADC and control a mission-mode digital input signal of the DAC based on the DC offset.

Claims

1. An apparatus for digital-to-analog conversion, comprising: a digital-to-analog converter (DAC); an incremental analog-to-digital converter (IADC) having a first input coupled to a first output of the DAC; and a controller coupled to the DAC and the IADC, wherein the controller is configured to: determine a direct current (DC) offset associated with the DAC using the IADC; and control a mission-mode digital input signal of the DAC based on the DC offset.

2. The apparatus of claim 1, wherein the IADC comprises a switch circuit coupled to the first output of the DAC.

3. The apparatus of claim 2, wherein the switch circuit is configured to: in a non-flip mode, couple the first output of the DAC to the first input of the IADC and a second output of the DAC to a second input of the IADC; and in a flip mode, couple the first output of the DAC to the second input of the IADC and the second output of the DAC to the first input of the IADC.

4. The apparatus of claim 3, wherein: the IADC is configured to: generate a non-flip-mode digital output signal based on a first output current of the DAC while the switch circuit is configured in the non-flip mode; and generate a flip-mode digital output signal based on a second output current of the DAC while the switch circuit is configured in the flip mode; and the controller is configured to determine the DC offset based on the non-flip-mode digital output signal and the flip-mode digital output signal.

5. The apparatus of claim 4, wherein the controller is configured to set a calibration-mode digital input signal of the DAC to a middle code, and wherein the IADC is configured to generate the non-flip-mode digital output signal and the flip-mode digital output signal while the calibration-mode digital input signal of the DAC is set to the middle code.

6. The apparatus of claim 1, wherein the IADC is configured to perform analog-to-digital conversion using delta-sigma modulation.

7. The apparatus of claim 1, wherein: the IADC is configured to be coupled to another DAC after the DC offset associated with the DAC is determined; and the controller is configured to determine another DC offset associated with the other DAC using the IADC after the IADC is coupled to the other DAC.

8. The apparatus of claim 1, further comprising a current source circuit configured to: sink a first current from a first node coupled to the first input of the IADC; and sink a second current from a second node coupled to a second input of the IADC.

9. The apparatus of claim 8, wherein an amount of the first current is the same as an amount of the second current.

10. The apparatus of claim 1, wherein: the controller is configured to set a calibration-mode digital input signal of the DAC to a middle code; the IADC is configured to generate a first digital output signal based on a first output current of the DAC while the calibration-mode digital input signal is set to the middle code; the controller is configured to set the calibration-mode digital input signal of the DAC to the middle code minus one; the IADC is configured to generate a second digital output signal based on a second output current of the DAC while the calibration-mode digital input signal is set to the middle code minus one; and the controller is configured to determine the DC offset based on the first digital output signal and the second digital output signal.

11. A method for digital-to-analog conversion, comprising: generating, via a digital-to-analog converter (DAC), a first output current based on a calibration-mode digital input signal; generating, via an incremental analog-to-digital converter (IADC), a first digital output signal based on the first output current; determining a direct current (DC) offset associated with the DAC based on the first digital output signal; and adjusting a mission-mode digital input signal for the DAC based on the DC offset.

12. The method of claim 11, wherein the IADC comprises a switch circuit coupled to an output of the DAC.

13. The method of claim 12, further comprising: generating, via the IADC, a non-flip-mode digital output signal based on the first output current of the DAC while the switch circuit is configured in a non-flip mode; and generating, via the IADC, a flip-mode digital output signal based on a second output current of the DAC while the switch circuit is configured in a flip mode, wherein the DC offset is determined based on the non-flip-mode digital output signal and the flip-mode digital output signal.

14. The method of claim 13, further comprising: in the non-flip mode, coupling a first output of the DAC to a first input of the IADC and a second output of the DAC to a second input of the IADC using the switch circuit; and in the flip mode, coupling the first output of the DAC to the second input of the IADC and the second output of the DAC to the first input of the IADC using the switch circuit.

15. The method of claim 13, further comprising setting the calibration-mode digital input signal of the DAC to a middle code, wherein the non-flip-mode digital output signal and the flip-mode digital output signal are generated while the calibration-mode digital input signal of the DAC is set to the middle code.

16. The method of claim 11, further comprising: coupling the IADC to another DAC after the DC offset associated with the DAC is determined; and determining another DC offset associated with the other DAC using the IADC after the IADC is coupled to the other DAC.

17. The method of claim 11, further comprising: sinking a first current from a first node coupled to a first input of the IADC; and sinking a second current from a second node coupled to a second input of the IADC, wherein the first digital output signal is generated while the first current and the second current are being sunk from the first input and the second input of the IADC, respectively.

18. The method of claim 17, wherein an amount of the first current is the same as an amount of the second current.

19. The method of claim 11, further comprising: setting the calibration-mode digital input signal of the DAC to a middle code, wherein the first digital output signal is generated based on the first output current of the DAC while the calibration-mode digital input signal is set to the middle code; setting the calibration-mode digital input signal of the DAC to the middle code minus one; and generating a second digital output signal based on a second output current of the DAC while the calibration-mode digital input signal is set to the middle code minus one, wherein the DC offset is determined based on the first digital output signal and the second digital output signal.

20. An apparatus for digital-to-analog conversion, comprising: a digital-to-analog converter (DAC) including a first output and a second output; and an incremental analog-to-digital converter (IADC) including a switch circuit, a first input selectively coupled to the first output of the DAC or the second output of the DAC via the switch circuit, and a second input selectively coupled to the first output of the DAC or the second output of the DAC via the switch circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] So that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description, briefly summarized above, may be had by reference to aspects, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only certain typical aspects of this disclosure and are therefore not to be considered limiting of its scope, for the description may admit to other equally effective aspects.

[0010] FIG. 1 is a diagram of an example wireless communications network, in which aspects of the present disclosure may be practiced.

[0011] FIG. 2 is a block diagram conceptually illustrating a design of an example base station (BS) and user equipment (UE), in which aspects of the present disclosure may be practiced.

[0012] FIG. 3 is a block diagram of an example radio frequency (RF) transceiver, in which aspects of the present disclosure may be practiced.

[0013] FIG. 4 illustrates an example digital-to-analog converter (DAC) and an incremental analog-to-digital converter (IADC) for direct current (DC) offset measurement, in accordance with certain aspects of the present disclosure.

[0014] FIG. 5 is a flow diagram illustrating example operations for DC offset calibration, in accordance with certain aspects of the present disclosure.

[0015] FIG. 6A illustrates an IADC in a non-flip mode, in accordance with certain aspects of the present disclosure.

[0016] FIG. 6B illustrates an IADC in a flip mode, in accordance with certain aspects of the present disclosure.

[0017] FIG. 7 illustrates an example IDAC for DC offset measurement using current sinking, in accordance with certain aspects of the present disclosure.

[0018] FIGS. 8A and 8B illustrate an IADC without a switch circuit, in accordance with certain aspects of the present disclosure.

[0019] FIG. 9 is a flow diagram illustrating example operations for DC offset calibration, in accordance with certain aspects of the present disclosure.

[0020] FIG. 10 is a flow diagram illustrating example operations for digital-to-analog conversion, in accordance with certain aspects of the present disclosure.

[0021] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation.

DETAILED DESCRIPTION

[0022] Certain aspects of the present disclosure are directed towards techniques and apparatus for digital-to-analog conversion. For example, an incremental analog-to-digital converter (IADC) may be used to perform measurements to identify a direct current (DC) offset of a digital-to-analog converter (DAC). Based on the DC offset, a digital signal input to the DAC during mission mode may be adjusted to reduce the effect of the DC offset. In some aspects, the IADC may be implemented with a switch circuit for flipping the coupling between the differential outputs of the DAC and the differential inputs of the IADC. Two separate measurements may be performed by the IADC when the switch circuit is in a flip mode and a non-flip mode. The DC offset for the DAC may be calculated using the two separate measurements, canceling out (or at least reducing) the effect of any offset associated with the IADC on the DC offset measurement for the DAC, as described in more detail herein.

[0023] Various aspects of the disclosure are described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the disclosure disclosed herein, whether implemented independently of or combined with any other aspect of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim.

[0024] The word exemplary is used herein to mean serving as an example, instance, or illustration. Any aspect described herein as exemplary is not necessarily to be construed as preferred or advantageous over other aspects.

[0025] As used herein, the term connected with in the various tenses of the verb connect may mean that element A is directly connected to element B or that other elements may be connected between elements A and B (i.e., that element A is indirectly connected with element B). In the case of electrical components, the term connected with may also be used herein to mean that a wire, trace, or other electrically conductive material is used to electrically connect elements A and B (and any components electrically connected therebetween).

An Example Wireless System

[0026] FIG. 1 illustrates an example wireless communications network 100, in which aspects of the present disclosure may be practiced. For example, the wireless communications network 100 may be a New Radio (NR) system (e.g., a Fifth Generation (5G) NR network), an Evolved Universal Terrestrial Radio Access (E-UTRA) system (e.g., a Fourth Generation (4G) network), a Universal Mobile Telecommunications System (UMTS) (e.g., a Second Generation/Third Generation (2G/3G) network), or a code division multiple access (CDMA) system (e.g., a 2G/3G network), or may be configured for communications according to an IEEE standard such as one or more of the 802.11 standards, etc.

[0027] As illustrated in FIG. 1, the wireless communications network 100 may include a number of base stations (BSs) 110a-z (each also individually referred to herein as BS 110 or collectively as BSs 110) and other network entities. A BS may also be referred to as an access point (AP), an evolved Node B (eNodeB or eNB), a next generation Node B (gNodeB or gNB), or some other terminology.

[0028] A BS 110 may provide communication coverage for a particular geographic area, sometimes referred to as a cell, which may be stationary or may move according to the location of a mobile BS. In some examples, the BSs 110 may be interconnected to one another and/or to one or more other BSs or network nodes (not shown) in wireless communications network 100 through various types of backhaul interfaces (e.g., a direct physical connection, a wireless connection, a virtual network, or the like) using any suitable transport network. In the example shown in FIG. 1, the BSs 110a, 110b, and 110c may be macro BSs for the macro cells 102a, 102b, and 102c, respectively. The BS 110x may be a pico BS for a pico cell 102x. The BSs 110y and 110z may be femto BSs for the femto cells 102y and 102z, respectively. A BS may support one or multiple cells.

[0029] The BSs 110 communicate with one or more user equipment's (UEs) 120a-y (each also individually referred to herein as UE 120 or collectively as UEs 120) in the wireless communications network 100. A UE may be fixed or mobile and may also be referred to as a user terminal (UT), a mobile station (MS), an access terminal, a station (STA), a client, a wireless device, a mobile device, or some other terminology. A user terminal may be a wireless device, such as a cellular phone, a smartphone, a personal digital assistant (PDA), a handheld device, a wearable device, a wireless modem, a laptop computer, a tablet, a personal computer, etc.

[0030] The BSs 110 are considered transmitting entities for the downlink and receiving entities for the uplink. The UEs 120 are considered transmitting entities for the uplink and receiving entities for the downlink. As used herein, a transmitting entity is an independently operated apparatus or device capable of transmitting data via a frequency channel, and a receiving entity is an independently operated apparatus or device capable of receiving data via a frequency channel. In the following description, the subscript dn denotes the downlink, the subscript up denotes the uplink. N.sub.up UEs may be selected for simultaneous transmission on the uplink, N.sub.dn UEs may be selected for simultaneous transmission on the downlink. N.sub.up may or may not be equal to N.sub.dn, and N.sub.up and N.sub.dn may be static values or can change for each scheduling interval. Beam-steering or some other spatial processing technique may be used at the BSs 110 and/or UEs 120.

[0031] The UEs 120 (e.g., 120x, 120y, etc.) may be dispersed throughout the wireless communications network 100, and each UE 120 may be stationary or mobile. The wireless communications network 100 may also include relay stations (e.g., relay station 110r), also referred to as relays or the like, that receive a transmission of data and/or other information from an upstream station (e.g., a BS 110a or a UE 120r) and send a transmission of the data and/or other information to a downstream station (e.g., a UE 120 or a BS 110), or that relays transmissions between UEs 120, to facilitate communication between devices.

[0032] The BSs 110 may communicate with one or more UEs 120 at any given moment on the downlink and uplink. The downlink (i.e., forward link) is the communication link from the BSs 110 to the UEs 120, and the uplink (i.e., reverse link) is the communication link from the UEs 120 to the BSs 110. A UE 120 may also communicate peer-to-peer with another UE 120.

[0033] The wireless communications network 100 may use multiple transmit and multiple receive antennas for data transmission on the downlink and uplink. BSs 110 may be equipped with a number N.sub.ap of antennas to achieve transmit diversity for downlink transmissions and/or receive diversity for uplink transmissions. A set N.sub.u of UEs 120 may receive downlink transmissions and transmit uplink transmissions. Each UE 120 may transmit user-specific data to and/or receive user-specific data from the BSs 110. In general, each UE 120 may be equipped with one or multiple antennas. The N.sub.u UEs 120 can have the same or different numbers of antennas.

[0034] The wireless communications network 100 may be a time division duplex (TDD) system or a frequency division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. The wireless communications network 100 may also utilize a single carrier or multiple carriers for transmission. Each UE 120 may be equipped with a single antenna (e.g., to keep costs down) or multiple antennas (e.g., where the additional cost can be supported).

[0035] A network controller 130 (also sometimes referred to as a system controller) may be in communication with a set of BSs 110 and provide coordination and control for these BSs 110 (e.g., via a backhaul). In certain cases (e.g., in a 5G NR system), the network controller 130 may include a centralized unit (CU) and/or a distributed unit (DU). In certain aspects, the network controller 130 may be in communication with a core network 132 (e.g., a 5G Core Network (5GC)), which provides various network functions such as Access and Mobility Management, Session Management, User Plane Function, Policy Control Function, Authentication Server Function, Unified Data Management, Application Function, Network Exposure Function, Network Repository Function, Network Slice Selection Function, etc.

[0036] In certain aspects of the present disclosure, the BSs 110 and/or the UEs 120 may include a digital-to-analog converter (DAC) and an incremental analog-to-digital converter (IADC) used to make measurements to identify a direct current (DC) offset associated with the DAC, as described in more detail herein.

[0037] FIG. 2 illustrates example components of BS 110a and UE 120a (e.g., from the wireless communications network 100 of FIG. 1), in which aspects of the present disclosure may be implemented.

[0038] On the downlink, at the BS 110a, a transmit processor 220 may receive data from a data source 212, control information from a controller/processor 240, and/or possibly other data (e.g., from a scheduler 244). The various types of data may be sent on different transport channels. For example, the control information may be designated for the physical broadcast channel (PBCH), physical control format indicator channel (PCFICH), physical hybrid automatic repeat request (HARQ) indicator channel (PHICH), physical downlink control channel (PDCCH), group common PDCCH (GC PDCCH), etc. The data may be designated for the physical downlink shared channel (PDSCH), etc. A medium access control (MAC)-control element (MAC-CE) is a MAC layer communication structure that may be used for control command exchange between wireless nodes. The MAC-CE may be carried in a shared channel such as a PDSCH, a physical uplink shared channel (PUSCH), or a physical sidelink shared channel (PSSCH).

[0039] The processor 220 may process (e.g., encode and symbol map) the data and control information to obtain data symbols and control symbols, respectively. The transmit processor 220 may also generate reference symbols, such as for the primary synchronization signal (PSS), secondary synchronization signal (SSS), PBCH demodulation reference signal (DMRS), and channel state information reference signal (CSI-RS).

[0040] A transmit (TX) multiple-input, multiple-output (MIMO) processor 230 may perform spatial processing (e.g., precoding) on the data symbols, the control symbols, and/or the reference symbols, if applicable, and may provide output symbol streams to the modulators (MODs) in transceivers 232a-232t. Each modulator in transceivers 232a-232t may process a respective output symbol stream (e.g., for orthogonal frequency division multiplexing (OFDM), etc.) to obtain an output sample stream. Each of the transceivers 232a-232t may further process (e.g., convert to analog, amplify, filter, and upconvert) the output sample stream to obtain a downlink signal. Downlink signals from the transceivers 232a-232t may be transmitted via the antennas 234a-234t, respectively.

[0041] At the UE 120a, the antennas 252a-252r may receive the downlink signals from the BS 110a and may provide received signals to the transceivers 254a-254r, respectively. The transceivers 254a-254r may condition (e.g., filter, amplify, downconvert, and digitize) a respective received signal to obtain input samples. Each demodulator (DEMOD) in the transceivers 232a-232t may further process the input samples (e.g., for OFDM, etc.) to obtain received symbols. A MIMO detector 256 may obtain received symbols from all the demodulators in transceivers 254a-254r, perform MIMO detection on the received symbols if applicable, and provide detected symbols. A receive processor 258 may process (e.g., demodulate, deinterleave, and decode) the detected symbols, provide decoded data for the UE 120a to a data sink 260, and provide decoded control information to a controller/processor 280.

[0042] On the uplink, at UE 120a, a transmit processor 264 may receive and process data (e.g., for the physical uplink shared channel (PUSCH)) from a data source 262 and control information (e.g., for the physical uplink control channel (PUCCH)) from the controller/processor 280. The transmit processor 264 may also generate reference symbols for a reference signal (e.g., the sounding reference signal (SRS)). The symbols from the transmit processor 264 may be precoded by a TX MIMO processor 266 if applicable, further processed by the modulators (MODs) in transceivers 254a-254r (e.g., for single-carrier frequency division multiplexing (SC-FDM), etc.), and transmitted to the BS 110a. At the BS 110a, the uplink signals from the UE 120a may be received by the antennas 234, processed by the demodulators in transceivers 232a-232t, detected by a MIMO detector 236 if applicable, and further processed by a receive processor 238 to obtain decoded data and control information sent by the UE 120a. The receive processor 238 may provide the decoded data to a data sink 239 and the decoded control information to the controller/processor 240.

[0043] The memories 242 and 282 may store data and program codes for BS 110a and UE 120a, respectively. The memories 242 and 282 may also interface with the controllers/processors 240 and 280, respectively. A scheduler 244 may schedule UEs for data transmission on the downlink and/or uplink.

[0044] In certain aspects of the present disclosure, the transceivers 232 and/or the transceivers 254 may include a DAC and an IADC used to make measurements to identify a DC offset associated with the DAC, as described in more detail herein.

[0045] NR may utilize orthogonal frequency division multiplexing (OFDM) with a cyclic prefix (CP) on the uplink and downlink. NR may support half-duplex operation using time division duplexing (TDD). OFDM and single-carrier frequency division multiplexing (SC-FDM) partition the system bandwidth into multiple orthogonal subcarriers, which are also commonly referred to as tones, bins, etc. Each subcarrier may be modulated with data. Modulation symbols may be sent in the frequency domain with OFDM and in the time domain with SC-FDM. The spacing between adjacent subcarriers may be fixed, and the total number of subcarriers may be dependent on the system bandwidth. The system bandwidth may also be partitioned into subbands. For example, a subband may cover multiple resource blocks (RBs).

Example RF Transceiver

[0046] FIG. 3 is a block diagram of an example radio frequency (RF) transceiver circuit 300, in accordance with certain aspects of the present disclosure. The RF transceiver circuit 300 includes at least one transmit (TX) path 302 (also known as a transmit chain) for transmitting signals via one or more antennas 306 and at least one receive (RX) path 304 (also known as a receive chain) for receiving signals via the antennas 306. When the TX path 302 and the RX path 304 share an antenna 306, the paths may be connected with the antenna via an interface 308, which may include any of various suitable RF devices, such as a switch, a duplexer, a diplexer, a multiplexer, and the like.

[0047] Receiving in-phase (I) and/or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 310, the TX path 302 may include a baseband filter (BBF) 312, a mixer 314, a driver amplifier (DA) 316, and a power amplifier (PA) 318. The BBF 312, the mixer 314, the DA 316, and the PA 318 may be included in a radio frequency integrated circuit (RFIC). For certain aspects, the PA 318 may be external to the RFIC. In some aspects, an IADC may be used to make measurements to identify a DC offset associated with the DAC 310, as described in more detail herein.

[0048] The BBF 312 filters the baseband signals received from the DAC 310, and the mixer 314 mixes the filtered baseband signals with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., upconvert from baseband to a radio frequency). This frequency-conversion process produces the sum and difference frequencies between the LO frequency and the frequencies of the baseband signal of interest. The sum and difference frequencies are referred to as the beat frequencies. The beat frequencies are typically in the RF range, such that the signals output by the mixer 314 are typically RF signals, which may be amplified by the DA 316 and/or by the PA 318 before transmission by the antenna(s) 306. While one mixer 314 is illustrated, several mixers may be used to upconvert the filtered baseband signals to one or more intermediate frequencies and to thereafter upconvert the intermediate frequency (IF) signals to a frequency for transmission.

[0049] The RX path 304 may include a low noise amplifier (LNA) 324, a mixer 326, and a baseband filter (BBF) 328. The LNA 324, the mixer 326, and the BBF 328 may be included in one or more RFICs, which may or may not be the same RFIC that includes the TX path components. RF signals received via the antenna(s) 306 may be amplified by the LNA 324, and the mixer 326 mixes the amplified RF signals with a receive local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (e.g., downconvert). The baseband signals output by the mixer 326 may be filtered by the BBF 328 before being converted by an analog-to-digital converter (ADC) 330 to digital I and/or Q signals for digital signal processing.

[0050] Certain transceivers may employ frequency synthesizers with a variable-frequency oscillator (e.g., a voltage-controlled oscillator (VCO) or a digitally controlled oscillator (DCO)) to generate a stable, tunable LO with a particular tuning range. Thus, the transmit LO may be produced by a TX frequency synthesizer 320, which may be buffered or amplified by amplifier 322 before being mixed with the baseband signals in the mixer 314. Similarly, the receive LO may be produced by an RX frequency synthesizer 332, which may be buffered or amplified by amplifier 334 before being mixed with the RF signals in the mixer 326. For certain aspects, a single frequency synthesizer may be used for both the TX path 302 and the RX path 304.

[0051] A controller 336 (e.g., controller/processor 280 in FIG. 2) may direct the operation of the RF transceiver circuit 300A, such as transmitting signals via the TX path 302 and/or receiving signals via the RX path 304. The controller 336 may be a processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. A memory 338 (e.g., memory 282 in FIG. 2) may store data and/or program codes for operating the RF transceiver circuit 300. The controller 336 and/or the memory 338 may include control logic (e.g., complementary metal-oxide-semiconductor (CMOS) logic).

[0052] While FIGS. 1-3 provide wireless communications as an example application in which certain aspects of the present disclosure may be implemented to facilitate understanding, certain aspects described herein may be used for any of various other suitable systems.

Example Techniques for Digital-to-Analog Conversion

[0053] A current-steering digital-to-analog converter (DAC) is commonly used as the DAC structure for a transmit chain because such a DAC operates efficiently at a high conversion speed. The DAC output is in the form of a differential current in this case. The direct current (DC) offset of the DAC affects certain performance specifications, such as carrier suppression (CARSUP) and local oscillator (LO) leakage. The CARSUP specification is becoming more stringent; thus, reducing the DC offset of the DAC may help meet this specification. One way of reducing the DC offset is to increase the transistor and resistor sizes associated with the DAC. However, this manner of reducing DC offset would cause the DAC area to increase significantly.

[0054] Some implementations use repeated most-significant bit (MSB) current cell calibration to detect the DC offset and calibrate the DAC. However, using repeated MSB current cell calibration may be insufficient to meet CARSUP specifications. Moreover, performing multiple calibrations increases test time and cost. Certain aspects of the present disclosure are directed toward techniques for performing calibration to reduce the effect of a DC offset of a DAC in a manner that has little to no impact on the mission mode of the DAC.

[0055] FIG. 4 illustrates an example DAC 402 (e.g., a DAC for a transmit chain labeled TXDAC, such as the DAC 310 described with respect to FIG. 3) and an incremental analog-to-digital converter (IADC) 450 for DC offset measurement, in accordance with certain aspects of the present disclosure. The outputs (e.g., differential outputs) of the DAC 402 may be coupled to respective differential inputs of the IADC 450. The IADC 450 may be implemented using a delta-sigma modulator (e.g., perform analog-to-digital conversion using delta-sigma modulation). For example, the IADC 450 may include an integrator 416 having differential inputs coupled to respective differential inputs 464, 466 of the IADC 450. The integrator 416 may include an operational amplifier with a first capacitive element (labeled C.sub.int) coupled between a negative input and a positive output of the operational amplifier, and a second capacitive element (labeled C.sub.int) coupled between a positive input and a negative output of the operational amplifier. As shown, reset switches (labeled RST) may be coupled in parallel with the first and second capacitive elements. The reset switches may be closed to discharge the first and second capacitive elements and reset the integrator 416.

[0056] A one-bit ADC 412 (labeled 1b ADC) (e.g., a comparator) may be coupled between a counter 414 (labeled CNT) and the differential outputs of the integrator 416. The counter 414 generates a digital output (D.sub.OUT) for the IADC. A one-bit DAC 408 (labeled 1b DAC) may be coupled between the output of the ADC 412 and inputs of the integrator 416, as shown. The 1b DAC 408 may be implemented using a current-steering cell 409. As shown, the current-steering cell 409 may include a current source (labeled I.sub.DAC) that selectively sinks current from inputs of the integrator using switches controlled by a digital signal (labeled D) and a complementary digital signal (labeled Db), respectively. The digital signal (D) and the complementary digital signal (Db) are generated by the 1b ADC 412.

[0057] The IADC 450 may be used to measure an offset current (e.g., I.sub.DAC,offset) associated with the DAC 402. The offset current may be represented by current source 406 in FIG. 4. In other words, when the data input signal (labeled D.sub.IN) for the DAC 402 is set to be equal to a middle code (mid code) (e.g., D.sub.IN is set to 100 . . . 000), a difference between a positive output current (I.sub.DAC,p) and a negative output current (I.sub.DAC,n) of the DAC 402 should be (e.g., ideally) equal to a resolution (a current (I.sub.LSB) representing a least-significant bit (LSB)) of the DAC 402. However, due to the DC offset of the DAC 402, the difference between I.sub.DAC,p and I.sub.DAC,n may not be equal to the resolution of the DAC 402 by an amount equal to I.sub.DAC,offset represented in FIG. 4 by the current source 406.

[0058] In some aspects, the IADC 450 may include a switch circuit 404. The switch circuit 404 may selectively couple the positive output 460 of the DAC 402 (e.g., providing I.sub.DAC,p) to either the negative input 466 or the positive input 464 of the IADC 450, and selectively couple the negative output 462 of the DAC 402 (e.g., providing I.sub.DAC,n) to either the negative input 466 or the positive input 464 of the IADC 450. During a non-flip mode, the switch circuit 404 couples the positive output 460 of the DAC 402 to the positive input 464 of the IADC 450 and couples the negative output 462 of the DAC 402 to the negative input 466 of the IADC 450. During a flip mode, the switch circuit 404 couples the negative output 462 of the DAC 402 to the positive input 464 of the IADC 450 and couples the positive output 460 of the DAC 402 to the negative input 466 of the IADC 450.

[0059] As shown, the integrator 416 may receive a positive input current (I.sub.p) at a first input of the integrator 416 from the input 464 and receive a negative input current I.sub.n at a second input of the integrator 416 from input 466. When in the non-flip mode, I.sub.p may be equal to I.sub.DAC,p+I.sub.DAC,offset, and I.sub.n may be equal to I.sub.DAC,n. The differential input signal to the integrator 416 (I.sub.pI.sub.n).sub.NFLIP in non-flip mode may be equal to I.sub.DAC,offset+I.sub.LSB, where I.sub.LSB is the resolution (a current representing a LSB) of the DAC 402. When in flip-mode, I.sub.p may be equal to I.sub.DAC,n, and I.sub.n may be equal to I.sub.DAC,p+I.sub.DAC,offset. The differential input signal to the integrator (I.sub.pI.sub.n).sub.FLIP in flip mode may be equal to I.sub.DAC,offsetI.sub.LSB.

[0060] FIG. 5 is a flow diagram illustrating example operations 500 for DC offset calibration, in accordance with certain aspects of the present disclosure. The operations 500 may be performed using a controller, such as the controller 240 or controller 280 of FIG. 2.

[0061] At block 502, the controller sets the data input signal (labeled D.sub.IN in FIG. 4) for the DAC 402 to be equal to a middle code (mid code). For example, the D.sub.IN may be set to 100 . . . 000. With the data input signal being set to the mid code, the difference between the differential output currents (I.sub.DAC,p and I.sub.DAC,n) of the DAC 402 should be equal to the resolution of the DAC without any DC offset, as described.

[0062] At block 504, the controller calculates (e.g., finds) I.sub.DAC,offset using measurements from the IADC 450. The calculation of the I.sub.DAC,offset may be performed using measurements made during non-flip and flip modes of the switch circuit 404.

[0063] FIG. 6A illustrates the IADC 450 in a non-flip mode, in accordance with certain aspects of the present disclosure. The switch circuit 404 may be configured in the non-flip mode to perform a non-flip operation. During the non-flip mode, the switch circuit 404 couples the positive output 460 of the DAC 402 to the positive input 464 of the IADC 450 and couples the negative output 462 of the DAC 402 to the negative input 466 of the IADC 450, as shown. During the non-flip operation, the differential output current of the DAC 402 is provided as input to the IADC 450 for conversion to a digital output (D.sub.NFLIP,OUT). The switch circuit 404 may then be configured in a flip mode to perform a flip operation.

[0064] FIG. 6B illustrates the IADC 450 in a flip mode, in accordance with certain aspects of the present disclosure. During the flip mode, the switch circuit 404 couples the negative output 462 of the DAC 402 to the positive input 464 of the IADC 450 and couples the positive output 460 of the DAC 402 to the negative input 466 of the IADC 450. During the flip operation, the differential output current of the DAC is inverted and used as the input to the IADC 450. For example, I.sub.DAC,p may be provided to the negative input 466, and I.sub.DAC,n may be provided to the positive input 464. As shown, the IADC 450 then converts the inverted differential output to a digital signal (D.sub.FLIP,OUT).

[0065] The DAC offset current I.sub.DAC,offset may be calculated based on the following equation:

[00001]$\left[{\left(I_p-I_n\right)}_{\mathrm{NFLIP}}-{\left(I_p-I_n\right)}_{\mathrm{FLIP}}\right]/2-I_{\mathrm{LSB}}=I_{\mathrm{DAC},\mathrm{offset}}$

Referring back to FIG. 5, at block 506, the controller generates a digital DAC offset signal (D.sub.DAC,offset) per the following equation:

[00002]$D_{\mathrm{DAC},\mathrm{offset}}=\frac{\left(D_{\mathrm{NFLIP},\mathrm{OUT}}-D_{\mathrm{FLIP},\mathrm{OUT}}\right)/4-1}{2}$

[0066] At block 508, the controller modifies DI for the DAC 402 during mission mode based on D.sub.DAC,offset to compensate for (or at least reduce) the effect of the DAC offset. For example, if D.sub.DAC,offset is equal to 3, the controller may subtract 3 from D.sub.IN for every digital input code during mission mode. For example, if the digital input signal before calibration (D.sub.IN,before_calibration) is equal to 100 . . . 000, then the digital input signal after calibration (D.sub.IN,after_calibration) may be equal to 011 . . . 101, given a D.sub.DAC,offset of 3. Performing the DC offset measurements with flip and non-flip modes as described herein effectively cancels out (e.g., or at least reduces) the impact of any DC offset associated with the IADC 450 itself on the DC offset measurement for the DAC 402, providing a more accurate measurement of the DC offset for the DAC 402.

[0067] Using the differential current outputs (I.sub.DAC,p and I.sub.DAC,n) of the DAC 402 to perform the DC offset measurement may involve using capacitive elements (C.sub.int) for the integrator 416, a large current source (I.sub.DAC) for the current-steering cell 409, and may result in a long measurement process (e.g., the IADC measurement process may take 22.sup.TXDAC,b cycles, where TXDAC,b represents the resolution of the DAC 402). For example, if the DAC 402 is a 10-bit DAC, the IADC 450 may use 22.sup.10 cycles for each DC offset measurement. Certain aspects are directed to techniques for reducing the size of the integrator capacitive elements (C.sub.int), reducing the size of the current source (I.sub.DAC) for the current-steering cell 409, and reducing the duration of the measurement process, as described in more detail with respect to FIG. 7.

[0068] FIG. 7 illustrates an IADC 450 for DC offset measurement using current sinking, in accordance with certain aspects of the present disclosure. The IADC 450 may include a current source circuit 701. The current source circuit 701 may include current sources 702, 704 that sink currents from respective positive output 460 and negative output 462. The current sources 702, 704 may sink the same current I.sub.sub, in some aspects. Thus, an equal amount of current I.sub.sub may be subtracted from both the differential current outputs of the DAC 402. I.sub.sub may be equal to (I.sub.FSI.sub.LSB)/2 to reduce the current sent to IADC 450 to I.sub.LSB, I.sub.FS being the full-scale current of the DAC 402 (e.g., I.sub.DAC,p+I.sub.DAC,n). may be set to be equal to 2.sup.N, where N is a positive integer less than TXDAC,b. For example, if TXDAC,b is 10 for a 10-bit DAC 402, then N may be set to be equal to an integer less than 10 (e.g., 7). In this manner, the size of the integrator capacitive elements (C.sub.int), the size of the current source (I.sub.DAC) of the current-steering cell 409, and the processing time of IADC 450 for DC offset measurements may be reduced by 2.sup.(TXDAC,bN). With the implementation described with respect to FIG. 7, the overall operation/calculation to obtain the DAC DC offset remains the same as described with respect to FIG. 5.

[0069] Any noise associated with the DAC 402 and IADC 450 may be canceled over time and may not impact the DC offset measurements. As shown, the IADC 450 is separate from the DAC 402 and may have little to no impact on the operation of the DAC 402 during mission mode. No modification to the DAC 402 may be performed for the DC offset measurement techniques described herein. Having the IADC separate from the DAC 402 allows for evaluating the DC offset both using automated test equipment (ATE) and in the factory.

[0070] The IADC 450 may be shared to calibrate the DC offset for multiple DACs, such as a DAC for an in-phase (I) path, a DAC for a quadrature (Q) path, a DAC for a 45 offset in-phase (I45) path, and a DAC for a 45 offset quadrature (Q45) path of a transmitter. For instance, as shown in FIG. 4, the DAC 402 may represent N DAC(s), N being a positive integer. The DACs may be selectively coupled to the IADC 450 for DC offset calibration.

[0071] FIGS. 8A and 8B illustrate the IADC 450 without the switch circuit 404 and receiving two different values for D.sub.IN, in accordance with certain aspects of the present disclosure. In this case, instead of flipping the differential outputs of DAC 402 (e.g., in flip and non-flip modes), the DC offset may be measured using two different values for D.sub.IN, as described in more detail with respect to FIG. 9.

[0072] FIG. 9 is a flow diagram illustrating example operations 900 for DC offset calibration without a switch circuit, in accordance with certain aspects of the present disclosure. The operations 900 may be performed by a controller, such as the controller 240 or controller 280 of FIG. 2.

[0073] At block 902, D.sub.IN may be set to the mid-code (e.g., 100 . . . 000), and at block 904, the IADC 450 may evaluate (e.g., perform analog-to-digital conversion) to generate a digital output signal D.sub.OUT,100 . . . 000, as shown in FIG. 8A. The controller may obtain the digital output signal D.sub.OUT,100 . . . 000. At block 906, D.sub.IN may be set to the mid-code minus one (011 . . . 111), and at block 908, the IADC 450 may evaluate (e.g., performing analog-to-digital conversion) to generate a digital output signal D.sub.OUT,011 . . . 111, as shown in FIG. 8B. The digital output signal D.sub.OUT,011 . . . 111 may be obtained by the controller. The D.sub.IN value of 100 . . . 000 should provide a DAC differential current [I.sub.DAC,PI.sub.DAC,N] representing +I.sub.LSB/2 and the D.sub.IN value of 011 . . . 111 should provide a differential current [I.sub.DAC,PI.sub.DAC,N] representing I.sub.LSB/2, the addition of which should be zero without any DC offset (e.g., assuming an ideal DAC 402).

[0074] When D.sub.IN is set to 100 . . . 000, the positive output current of DAC 402 may be equal to I.sub.DAC,p,100 . . . 000 and I.sub.p may be equal to I.sub.DAC,p,100 . . . 000+I.sub.DAC,offset. When D.sub.IN is set to 100 . . . 000, the negative output current of DAC 402 may be equal to I.sub.DAC,n,100 . . . 000 and I.sub.n may be equal to I.sub.DAC,n,100 . . . 000. Thus, the different input current (I.sub.pI.sub.n).sub.100 . . . 000 of the IADC 450 may be equal to I.sub.DAC,offset+I.sub.LSB. When D.sub.IN is set to 011 . . . 111, the positive output current of DAC 402 may be equal to I.sub.DAC,p,011 . . . 111, and I.sub.p may be equal to I.sub.DAC,p,011 . . . 111+I.sub.DAC,offset. When D.sub.IN is set to 011 . . . 111, the negative output current of DAC 402 may be equal to I.sub.DAC,n,011 . . . 111, and I.sub.n may be equal to I.sub.DAC,n,011 . . . 111. Thus, the different input current (I.sub.pI.sub.n).sub.011 . . . 111 of the IADC 450 may be equal to I.sub.DAC, offsetI.sub.LSB. Thus, I.sub.DAC,offset may be calculated based on the following equation:

[00003]$I_{\mathrm{DAC},\mathrm{offset}}=\left[{\left(I_p-I_n\right)}_{100\mathrm{.Math.000}}+{\left(I_p-I_n\right)}_{011\mathrm{.Math.111}}\right]/2$

[0075] To calculate the DC offset associated with DAC 402 at block 910, the controller may add the two digital output signals (D.sub.OUT,100 . . . 000 and D.sub.OUT,011 . . . 111) to obtain a DAC offset digital signal (D.sub.DAC,offset) per the following equation:

[00004]$D_{\mathrm{DAC},\mathrm{offset}}=\frac{D_{\mathrm{OUT},100\mathrm{.Math.000}}+D_{\mathrm{OUT},011\mathrm{.Math.111}}}{8}$

At block 912, the controller modifies D.sub.IN for the DAC 402 during mission mode based on D.sub.DAC,offset to compensate for (or at least reduce) the effect of the DAC offset (e.g., similar to block 508 of FIG. 5).

[0076] The DC offset calibration techniques described herein may correct (or at least reduce) the DC offset to a range of 0.5 I.sub.LSB. The hardware to implement the IADC 450 may be shared among different DACs for calibration.

[0077] FIG. 10 is a flow diagram illustrating example operations 1000 for digital-to-analog conversion, in accordance with certain aspects of the present disclosure. The operations 1000 may be performed, for example, by a conversion circuit, such as the DAC 402, the IADC 450, and a controller (e.g., controller 240 or 280 of FIG. 2).

[0078] At block 1002, the conversion circuit may generate, via a DAC (e.g., DAC 402), a first output current (e.g., I.sub.DAC,p) based on a calibration-mode digital input signal (e.g., D.sub.IN during a calibration mode). At block 1004, the conversion circuit may generate, via an IADC (e.g. IADC 450), a first digital output signal (e.g., D.sub.OUT) based on the first output current.

[0079] At block 1006, the conversion circuit may determine a DC offset associated with the DAC based on the first digital output signal. At block 1008, the conversion circuit may adjust a mission-mode digital input signal (e.g., D.sub.IN during mission mode) for the DAC based on the DC offset.

[0080] In some aspects, the IADC may include a switch circuit (e.g., switch circuit 404 of FIG. 4) coupled to an output of the DAC. The conversion circuit may generate, via the IADC, a non-flip-mode digital output signal (e.g., D.sub.NFLIP,OUT) based on the first output current of the DAC while the switch circuit is configured in non-flip mode. The conversion circuit may also generate, via the IADC, a flip-mode digital output signal (e.g., D.sub.FLIP,OUT) based on a second output current of the DAC while the switch circuit is configured in flip mode. The DC offset may be determined based on the non-flip-mode digital output signal and the flip-mode digital output signal.

[0081] In some aspects, the conversion circuit may, in the non-flip mode, couple a first output (e.g., output 460 of FIG. 4) of the DAC to a first input (e.g., input 464) of the IADC and a second output (e.g., output 462) of the DAC to a second input (e.g., input 466) of the IADC using the switch circuit. The conversion circuit may, in the flip mode, couple the first output of the DAC to the second input of the IADC and the second output of the DAC to the first input of the IADC using the switch circuit. In some aspects, the conversion circuit may set the calibration-mode digital input signal of the DAC to a middle code. The non-flip-mode digital output signal and the flip-mode digital output signal may be generated while the calibration-mode digital input signal of the DAC is set to the middle code.

[0082] In some aspects, the conversion circuit may couple the IADC to another DAC after the DC offset associated with the DAC is determined. The conversion circuit may determine another DC offset associated with the other DAC using the IADC after the IADC is coupled to the other DAC.

[0083] In some aspects, the conversion circuit may sink a first current (e.g., via current source 702) from a first node coupled to a first input (e.g., input 464) of the IADC. The conversion circuit may also sink a second current (e.g., via current source 704) from a second node coupled to a second input (e.g., input 466) of the IADC. The first digital output signal may be generated while the first current and the second current are being sunk from the first input and the second input of the IADC, respectively. An amount of the first current (e.g., I.sub.sub) may be the same as an amount of the second current (e.g., I.sub.sub).

[0084] In some aspects, the conversion circuit may set the calibration-mode digital input signal of the DAC to a middle code. The first digital output signal (D.sub.OUT,100 . . . 000) may be generated based on the first output current of the DAC while the digital input signal is set to the middle code. The conversion circuit may set the digital input signal of the DAC to the middle code minus one, and generate a second digital output signal (D.sub.OUT,011 . . . 111) based on a second output current of the DAC while the digital input signal is set to the middle code minus one. The DC offset may be determined based on the first digital output signal and the second digital output signal.

Example Aspects

[0085] In addition to the various aspects described above, specific combinations of aspects are within the scope of the present disclosure, some of which are detailed below:

[0086] Aspect 1: An apparatus for digital-to-analog conversion, comprising: a digital-to-analog converter (DAC); an incremental analog-to-digital converter (IADC) having a first input coupled to a first output of the DAC; and a controller coupled to the DAC and the IADC, wherein the controller is configured to: determine a direct current (DC) offset associated with the DAC using the IADC; and control a mission-mode digital input signal of the DAC based on the DC offset.

[0087] Aspect 2: The apparatus of Aspect 1, wherein the IADC comprises a switch circuit coupled to the first output of the DAC.

[0088] Aspect 3: The apparatus of Aspect 2, wherein the switch circuit is configured to: in a non-flip mode, couple the first output of the DAC to the first input of the IADC and a second output of the DAC to a second input of the IADC; and in a flip mode, couple the first output of the DAC to the second input of the IADC and the second output of the DAC to the first input of the IADC.

[0089] Aspect 4: The apparatus of Aspect 3, wherein: the IADC is configured to: generate a non-flip-mode digital output signal based on a first output current of the DAC while the switch circuit is configured in the non-flip mode; and generate a flip-mode digital output signal based on a second output current of the DAC while the switch circuit is configured in the flip mode; and the controller is configured to determine the DC offset based on the non-flip-mode digital output signal and the flip-mode digital output signal.

[0090] Aspect 5: The apparatus of Aspect 4, wherein the controller is configured to set a calibration-mode digital input signal of the DAC to a middle code, and wherein the IADC is configured to generate the non-flip-mode digital output signal and the flip-mode digital output signal while the calibration-mode digital input signal of the DAC is set to the middle code.

[0091] Aspect 6: The apparatus according to any of Aspects 1-5, wherein the IADC is configured to perform analog-to-digital conversion using delta-sigma modulation.

[0092] Aspect 7: The apparatus according to any of Aspects 1-6, wherein: the IADC is configured to be coupled to another DAC after the DC offset associated with the DAC is determined; and the controller is configured to determine another DC offset associated with the other DAC using the IADC after the IADC is coupled to the other DAC.

[0093] Aspect 8: The apparatus according to any of Aspects 1-7, further comprising a current source circuit configured to: sink a first current from a first node coupled to the first input of the IADC; and sink a second current from a second node coupled to a second input of the IADC.

[0094] Aspect 9: The apparatus of Aspect 8, wherein an amount of the first current is the same as an amount of the second current.

[0095] Aspect 10: The apparatus according to any of Aspects 1-9, wherein: the controller is configured to set a calibration-mode digital input signal of the DAC to a middle code; the IADC is configured to generate a first digital output signal based on a first output current of the DAC while the calibration-mode digital input signal is set to the middle code; the controller is configured to set the calibration-mode digital input signal of the DAC to the middle code minus one; the IADC is configured to generate a second digital output signal based on a second output current of the DAC while the calibration-mode digital input signal is set to the middle code minus one; and the controller is configured to determine the DC offset based on the first digital output signal and the second digital output signal.

[0096] Aspect 11: A method for digital-to-analog conversion, comprising: generating, via a digital-to-analog converter (DAC), a first output current based on a calibration-mode digital input signal; generating, via an incremental analog-to-digital converter (IADC), a first digital output signal based on the first output current; determining a direct current (DC) offset associated with the DAC based on the first digital output signal; and adjusting a mission-mode digital input signal for the DAC based on the DC offset.

[0097] Aspect 12: The method of Aspect 11, wherein the IADC comprises a switch circuit coupled to an output of the DAC.

[0098] Aspect 13: The method of Aspect 12, further comprising: generating, via the IADC, a non-flip-mode digital output signal based on the first output current of the DAC while the switch circuit is configured in a non-flip mode; and generating, via the IADC, a flip-mode digital output signal based on a second output current of the DAC while the switch circuit is configured in a flip mode, wherein the DC offset is determined based on the non-flip-mode digital output signal and the flip-mode digital output signal.

[0099] Aspect 14: The method of Aspect 13, further comprising: in the non-flip mode, coupling a first output of the DAC to a first input of the IADC and a second output of the DAC to a second input of the IADC using the switch circuit; and in the flip mode, coupling the first output of the DAC to the second input of the IADC and the second output of the DAC to the first input of the IADC using the switch circuit.

[0100] Aspect 15: The method of Aspect 13 or 14, further comprising setting the calibration-mode digital input signal of the DAC to a middle code, wherein the non-flip-mode digital output signal and the flip-mode digital output signal are generated while the calibration-mode digital input signal of the DAC is set to the middle code.

[0101] Aspect 16: The method according to any of Aspects 11-15, further comprising: coupling the IADC to another DAC after the DC offset associated with the DAC is determined; and determining another DC offset associated with the other DAC using the IADC after the IADC is coupled to the other DAC.

[0102] Aspect 17: The method according to any of Aspects 11-16, further comprising: sinking a first current from a first node coupled to a first input of the IADC; and sinking a second current from a second node coupled to a second input of the IADC, wherein the first digital output signal is generated while the first current and the second current are being sunk from the first input and the second input of the IADC, respectively.

[0103] Aspect 18: The method of Aspect 17, wherein an amount of the first current is the same as an amount of the second current.

[0104] Aspect 19: The method according to any of Aspects 11-18, further comprising: setting the calibration-mode digital input signal of the DAC to a middle code, wherein the first digital output signal is generated based on the first output current of the DAC while the calibration-mode digital input signal is set to the middle code; setting the calibration-mode digital input signal of the DAC to the middle code minus one; and generating a second digital output signal based on a second output current of the DAC while the calibration-mode digital input signal is set to the middle code minus one, wherein the DC offset is determined based on the first digital output signal and the second digital output signal.

[0105] Aspect 20: An apparatus for digital-to-analog conversion, comprising: a digital-to-analog converter (DAC) including a first output and a second output; and an incremental analog-to-digital converter (IADC) including a switch circuit, a first input selectively coupled to the first output of the DAC or the second output of the DAC via the switch circuit, and a second input selectively coupled to the first output of the DAC or the second output of the DAC via the switch circuit.

[0106] The above description provides examples, and is not limiting of the scope, applicability, or examples set forth in the claims. Changes may be made in the function and arrangement of elements discussed without departing from the scope of the disclosure. Various examples may omit, substitute, or add various procedures or components as appropriate. For instance, the methods described may be performed in an order different from that described, and various steps may be added, omitted, or combined. Also, features described with respect to some examples may be combined in some other examples. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to, or other than, the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim.

[0107] The various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component(s) and/or module(s), including, but not limited to a circuit, an application-specific integrated circuit (ASIC), or processor. Generally, where there are operations illustrated in figures, those operations may have corresponding counterpart means-plus-function components.

[0108] As used herein, a phrase referring to at least one of a list of items refers to any combination of those items, including single members. As an example, at least one of: a, b, or c is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c).

[0109] The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.

[0110] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes, and variations may be made in the arrangement, operation, and details of the methods and apparatus described above without departing from the scope of the claims.