Method for Producing a Nanoscale Channel Structure

Abstract

A method for producing a nanoscale channel structure disclosed. The method includes depositing and structuring a first sacrificial layer on a substrate, depositing a second sacrificial layer on the substrate and on the first sacrificial layer, depositing an etching masking layer on the second sacrificial layer, partly removing the etching masking layer and the second sacrificial layer, removing the first sacrificial layer and additionally partly removing the second sacrificial layer, depositing a wall layer on the etching masking layer and on the substrate, structuring access openings to the second sacrificial layer, and removing the remaining second sacrificial layer.

Claims

1. A method for producing a nanoscale channel structure, comprising: a) depositing and structuring a first sacrificial layer on a substrate, b) depositing a second sacrificial layer on the substrate and on the first sacrificial layer, c) depositing an etch masking layer on the second sacrificial layer, d) partially removing the etch masking layer and the second sacrificial layer, e) removing the first sacrificial layer and further partially removing the second sacrificial layer, f) depositing a wall layer on the etch masking layer and on the substrate, g) structuring access openings to the second sacrificial layer, and h) removing the remaining second sacrificial layer.

2. The method as claimed in claim 1, wherein the second sacrificial layer is deposited with a thickness of less than 100 nm.

3. The method as claimed in claim 1, wherein the first sacrificial layer and the second sacrificial layer are deposited from the same material.

4. The method as claimed in claim 1, wherein the etch masking layer is deposited with a smaller thickness than the first sacrificial layer.

5. The method as claimed in claim 1, wherein the partial removal of the etch masking layer and of the second sacrificial layer and also the removal of the first sacrificial layer and the further partial removal of the second sacrificial layer are effected by way of anisotropic etching.

6. The method as claimed in claim 1, wherein the wall layer is deposited from the same material as the etch masking layer.

7. The method as claimed in claim 1, wherein the removal of the remaining second sacrificial layer is effected by way of isotropic etching.

8. A computer program configured to carry out each step of the method as claimed in claim 1.

9. A machine-readable storage medium on which a computer program as claimed in claim 8 is stored.

10. An electronic control unit configured to produce a nanoscale channel structure by way of a method as claimed in claim 1.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] An exemplary embodiment of the invention is illustrated in the drawings and will be explained in more detail in the following description.

[0019] FIG. 1 shows a cross-sectional view of a substrate, on which a first sacrificial layer has been deposited and structured.

[0020] FIG. 2 shows a cross-sectional view of the substrate according to FIG. 1, after a second sacrificial layer has been deposited on the substrate and the first sacrificial layer.

[0021] FIG. 3 shows a cross-sectional view of the substrate according to FIG. 2, after an etch masking layer has been deposited on the second sacrificial layer.

[0022] FIG. 4 shows a cross-sectional view of the substrate according to FIG. 3, after the etch masking layer and the second sacrificial layer have been partially removed.

[0023] FIG. 5 shows a cross-sectional view of a substrate according to FIG. 4, after the first sacrificial layer has been removed.

[0024] FIG. 6 shows a cross-sectional view of the substrate according to FIG. 5, after a wall layer has been deposited on the etch masking layer and on the substrate.

[0025] FIG. 7 shows a cross-sectional view of the substrate according to FIG. 6 after removal of the second sacrificial layer.

EXEMPLARY EMBODIMENTS OF THE INVENTION

[0026] In one exemplary embodiment of the invention, a first sacrificial layer 2 of polysilicon with a thickness of 150 nm is deposited on a substrate 1. Said layer is structured such that the substrate 1 is partially exposed again. This is illustrated in FIG. 1.

[0027] A second sacrificial layer 3, likewise consisting of polysilicon, is then deposited by means of LPCVD such that it covers, with a thickness of 5 nm, the exposed surface of the substrate 1, the surface of the first sacrificial layer 2 and the lateral faces of the first sacrificial layer 2.

[0028] Since the first sacrificial layer 2 and the second sacrificial layer 3 consist of the same material, they merge with one another, as illustrated in FIG. 2.

[0029] As illustrated in FIG. 3, an oxide layer is subsequently deposited, for example by means of PECVD, as an etch masking layer 4 such that it covers, with a thickness of 10 nm, the surface and lateral faces of the 5 nm-thick second sacrificial layer 3.

[0030] Anisotropic RIE etching is subsequently effected as etchback until the substrate 1 is partially exposed again. This means that in the regions that are not covered by the first sacrificial layer 2, the etch masking layer 4 and the underlying second sacrificial layer 3 are completely removed. The layer structure consisting of the second sacrificial layer 3 and the etch masking layer 4 that is applied on top of the first sacrificial layer 2 is also removed. The parts of the etch masking layer 4 which cover the sides of the first sacrificial layer 2 are not removed, since the anisotropic etching is only effected from top to bottom. These remaining parts of the etch masking layer 4 can therefore protect the underlying part of the second sacrificial layer 3 from etchback. The parts of the second sacrificial layer 3 that are arranged between the first sacrificial layer 2 and the etch masking layer 4 are not removed either. This is illustrated in FIG. 4.

[0031] The parameters of the RIE etching are then changed such that, in the remainder of the etching process, it is only the first sacrificial layer 2 and the second sacrificial layer 3 that are attacked, but no longer the etch masking layer 4. This completely removes the first sacrificial layer 2, with the residues of the etch masking layer 4 and the residues of the second sacrificial layer 3 protected by the latter, as shown in FIG. 5, remaining on the substrate 1.

[0032] A wall layer 5, composed of an oxide for example, is then deposited by means of PECVD in a thickness of 200 nm. As illustrated in FIG. 6, this wall layer 5 merges with the residues of the etch masking layer 4, since these two layers consist of the same material. This results in projections on the wall layer 5 above the residues of the etch masking layer 4. FIG. 6 illustrates the layer structure that arises when these projections have already been partially smoothed by way of structuring, with the result that only an indication remains on the upper side of the wall layer 5 as to where the residues of the second sacrificial layer 3 are located and where the nanoscale channels will therefore run in the finished channel structure.

[0033] Access openings to the residues of the second sacrificial layer 3 are then structured and XeF.sub.2 is introduced through said access openings until the residues of the second sacrificial layer 3 are completely removed by way of isotropic etching. As a result, nanoscale channels 6 are left at the location at which the residues of the second sacrificial layer 3 were previously located. Said nanoscale channels are accessible through the access openings. The width of the nanoscale channels corresponds to the former thickness of the etch masking layer 4, and thus 10 nm. The height of the nanoscale channels corresponds to the former thickness of the second sacrificial layer, and thus 5 nm. The nanoscale channel structure obtained in this way can for example be used for a DNA sequencer or for a gas sensor.