PROGRAM TIME IMPROVEMENT FOR NAND DIE WITH COARSE BITSCAN DURING PROGRAM-VERIFY
20250391484 ยท 2025-12-25
Assignee
Inventors
- Ancha Harihara Sravan (Bangalore, IN)
- Yosuke Kato (Yokohama, JP)
- Henry Chin (Fremont, CA, US)
- Erika Penzo (San Jose, CA, US)
Cpc classification
G11C16/3481
PHYSICS
G11C16/3459
PHYSICS
International classification
Abstract
A memory apparatus is provided and includes memory cells configured to retain a threshold voltage corresponding to data states. The memory cells are disposed in memory holes each connected to bit lines. Each of the bit lines is coupled to one of a plurality of sense amplifiers arranged in tiers. A control means is configured to program the memory cells in each of a plurality of program iterations of a program operation. The control means counts a failure quantity of a group of the memory cells having the threshold voltage below one of a plurality of verify voltages associated with one of the data states targeted for the memory cells in each of a plurality of verify iterations of a program operation. The count is a coarse count not separately counting the memory cells coupled with ones of the plurality of sense amplifiers of one or more of the tiers.
Claims
1. A memory apparatus, comprising: memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states, the memory cells disposed in memory holes each connected to one of a plurality of bit lines, each of the plurality of bit lines coupled to one of a plurality of sense amplifiers arranged in tiers; and a control means configured to: program the memory cells in each of a plurality of program iterations of a program operation, and count a failure quantity of a group of the memory cells having the threshold voltage below one of a plurality of verify voltages associated with one of the plurality of data states targeted for the memory cells in each of a plurality of verify iterations of the program operation, the count being a coarse count not separately counting the memory cells coupled with ones of the plurality of sense amplifiers of one or more of the tiers.
2. The memory apparatus as set forth in claim 1, wherein the tiers include odd numbered tiers of the plurality of sense amplifiers and even numbered tiers of the plurality of sense amplifiers arranged in an alternating fashion vertically in a sense amplifier stack and the control means is further configured to: logically or data of the plurality of sense amplifiers of at least one of the odd numbered tiers with data of the plurality of sense amplifiers of at least one of the even numbered tiers to determine logical or results; store the logical or results; and count the failure quantity based on the logical or results for all of the odd numbered tiers of the plurality of sense amplifiers of all of the even numbered tiers.
3. The memory apparatus as set forth in claim 2, wherein: one of the odd numbered tiers of the plurality of sense amplifiers and one of the even numbered tiers of the plurality of sense amplifiers are coupled together by a data bus; the memory apparatus further includes a supply switch and an operation control switch connected in series between a supply level and an even sense node of the one of the even numbered tiers of the plurality of sense amplifiers, a supply switch gate of the supply switch connected to the data bus; and the control means is coupled to the operation control switch and further configured to control the operation control switch to determine and re-latch the logical or results.
4. The memory apparatus as set forth in claim 3, wherein: the one of the even numbered tiers of the plurality of sense amplifiers includes an even transfer switch connecting the even sense node to an even local data bus and an even strobe switch and an even sense controlled switch connected in series between the even sense node and a reference level, an even sense controlled switch gate of the even sense controlled switch connected to the even sense node; the one of the even numbered tiers of the plurality of sense amplifiers includes an even local switch and an even local bus controlled switch connected in series between the even sense node and the reference level, an even local bus controlled switch gate of the even local bus controlled switch connected to the even local data bus; the one of the even numbered tiers of the plurality of sense amplifiers includes an even pre-charge switch connected between the supply level and the even local data bus and an even data bus connection switch connected between the data bus and the even local data bus; the one of the odd numbered tiers of the plurality of sense amplifiers includes an odd transfer switch connecting an odd sense node to an odd local data bus and an odd strobe switch and an odd sense controlled switch connected in series between the odd sense node and the reference level, an odd sense controlled switch gate of the odd sense controlled switch connected to the odd sense node; the one of the odd numbered tiers of the plurality of sense amplifiers includes an odd local switch and an odd local bus controlled switch connected in series between the odd sense node and the reference level, an odd local bus controlled switch gate of the odd local bus controlled switch connected to the odd local data bus; and the one of the odd numbered tiers of the plurality of sense amplifiers includes an odd pre-charge switch connected between the supply level and the odd local data bus and an odd data bus connection switch connected between the data bus and the odd local data bus.
5. The memory apparatus as set forth in claim 2, wherein: a first one of the odd numbered tiers of the plurality of sense amplifiers and a first one of the even numbered tiers of the plurality of sense amplifiers are coupled together by a first data bus; a second one of the odd numbered tiers of the plurality of sense amplifiers and a second one of the even numbered tiers of the plurality of sense amplifiers are coupled together by a second data bus; the memory apparatus further includes a first supply switch and a first operation control switch connected in series between a supply level and a first even sense node of the first one of the even numbered tiers of the plurality of sense amplifiers, a first supply switch gate of the first supply switch connected to the first data bus; the memory apparatus further includes a second supply switch and a second operation control switch connected in series between the supply level and a second even sense node of the second one of the even numbered tiers of the plurality of sense amplifiers, a second supply switch gate of the second supply switch connected to the second data bus; the memory apparatus further includes a pass operation control switch connected between the first data bus and the second data bus; and the control means is coupled to the first operation control switch and the second operation control switch and the pass operation control switch and further configured to control the first operation control switch and the second operation control switch and the pass operation control switch to determine and re-latch the logical or results.
6. The memory apparatus as set forth in claim 5, wherein: the first one of the even numbered tiers of the plurality of sense amplifiers includes a first even transfer switch connecting the first even sense node to a first even local data bus and a first even strobe switch and a first even sense controlled switch connected in series between the first even transfer switch and a reference level, a first even sense controlled switch gate of the first even sense controlled switch connected to the first even sense node; the first one of the even numbered tiers of the plurality of sense amplifiers includes a first even local switch and a first even local bus controlled switch connected in series between the first even sense node and the reference level, a first even local bus controlled switch gate of the first even local bus controlled switch connected to the first even local data bus; the first one of the even numbered tiers of the plurality of sense amplifiers includes a first even pre-charge switch connected between the supply level and the first even local data bus and a first even data bus connection switch connected between the first data bus and the first even local data bus; the first one of the odd numbered tiers of the plurality of sense amplifiers includes a first odd transfer switch connecting a first odd sense node to a first odd local data bus and a first odd strobe switch and an odd sense controlled switch connected in series between the first odd transfer switch and the reference level, a first odd sense controlled switch gate of the first odd sense controlled switch connected to the first odd sense node; the first one of the odd numbered tiers of the plurality of sense amplifiers includes a first odd local switch and a first odd local bus controlled switch connected in series between the first odd sense node and the reference level, a first odd local bus controlled switch gate of the first odd local bus controlled switch connected to the first odd local data bus; the first one of the odd numbered tiers of the plurality of sense amplifiers includes a first odd pre-charge switch connected between the supply level and the first odd local data bus and a first odd data bus connection switch connected between the first data bus and the first odd local data bus; the second one of the even numbered tiers of the plurality of sense amplifiers includes a second even transfer switch connecting the second even sense node to a second even local data bus and a second even strobe switch and a second even sense controlled switch connected in series between the second even sense node and a reference level, a second even sense controlled switch gate of the second even sense controlled switch connected to the second even sense node; the second one of the even numbered tiers of the plurality of sense amplifiers includes a second even local switch and a second even local bus controlled switch connected in series between the second even sense node and the reference level, a second even local bus controlled switch gate of the second even local bus controlled switch connected to the second even local data bus; the second one of the even numbered tiers of the plurality of sense amplifiers includes a second even pre-charge switch connected between the supply level and the second even local data bus and a second even data bus connection switch connected between the second data bus and the second even local data bus; the second one of the odd numbered tiers of the plurality of sense amplifiers includes a second odd transfer switch connecting a second odd sense node to a second odd local data bus and a second odd strobe switch and an odd sense controlled switch connected in series between the second odd transfer switch and the reference level, a second odd sense controlled switch gate of the second odd sense controlled switch connected to the second odd sense node; the second one of the odd numbered tiers of the plurality of sense amplifiers includes a second odd local switch and a second odd local bus controlled switch connected in series between the second odd sense node and the reference level, a second odd local bus controlled switch gate of the second odd local bus controlled switch connected to the second odd local data bus; and the second one of the odd numbered tiers of the plurality of sense amplifiers includes a second odd pre-charge switch connected between the supply level and the second odd local data bus and a second odd data bus connection switch connected between the second data bus and the second odd local data bus.
7. The memory apparatus as set forth in claim 1, wherein the control means is further configured to: coarse count the failure quantity of the group of the memory cells to determine a coarse count failure quantity; determine whether the failure quantity is less than a predetermined failure quantity threshold; and count an actual failure quantity including separately counting the memory cells coupled with ones of the plurality of sense amplifiers of all of the tiers in response to the failure quantity being less than the predetermined failure quantity threshold.
8. A controller in communication with a memory apparatus including memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states, the memory cells disposed in memory holes each connected to one of a plurality of bit lines, each of the plurality of bit lines coupled to one of a plurality of sense amplifiers arranged in tiers, the controller configured to: instruct the memory apparatus to program the memory cells in each of a plurality of program iterations of a program operation; instruct the memory apparatus to count a failure quantity of a group of the memory cells having the threshold voltage below one of a plurality of verify voltages associated with one of the plurality of data states targeted for the memory cells in each of a plurality of verify iterations of the program operation, the count being a coarse count not separately counting the memory cells coupled with ones of the plurality of sense amplifiers of one or more of the tiers.
9. The controller as set forth in claim 8, wherein the tiers include odd numbered tiers of the plurality of sense amplifiers and even numbered tiers of the plurality of sense amplifiers arranged in an alternating fashion vertically in a sense amplifier stack and the controller is further configured to: instruct the memory apparatus to logically or data of the plurality of sense amplifiers of at least one of the odd numbered tiers with data of the plurality of sense amplifiers of at least one of the even numbered tiers to determine logical or results; instruct the memory apparatus to store the logical or results; and instruct the memory apparatus to count the failure quantity based on the logical or results for all of the odd numbered tiers of the plurality of sense amplifiers of all of the even numbered tiers.
10. The controller as set forth in claim 9, wherein: one of the odd numbered tiers of the plurality of sense amplifiers and one of the even numbered tiers of the plurality of sense amplifiers are coupled together by a data bus; the memory apparatus further includes a supply switch and an operation control switch connected in series between a supply level and an even sense node of the one of the even numbered tiers of the plurality of sense amplifiers, a supply switch gate of the supply switch connected to the data bus; and the controller is in communication with the operation control switch and further configured to instruct the memory apparatus control the operation control switch to determine and re-latch the logical or results.
11. The controller as set forth in claim 10, wherein: the one of the even numbered tiers of the plurality of sense amplifiers includes an even transfer switch connecting the even sense node to an even local data bus and an even strobe switch and an even sense controlled switch connected in series between the even sense node and a reference level, an even sense controlled switch gate of the even sense controlled switch connected to the even sense node; the one of the even numbered tiers of the plurality of sense amplifiers includes an even local switch and an even local bus controlled switch connected in series between the even sense node and the reference level, an even local bus controlled switch gate of the even local bus controlled switch connected to the even local data bus; the one of the even numbered tiers of the plurality of sense amplifiers includes an even pre-charge switch connected between the supply level and the even local data bus and an even data bus connection switch connected between the data bus and the even local data bus; the one of the odd numbered tiers of the plurality of sense amplifiers includes an odd transfer switch connecting an odd sense node to an odd local data bus and an odd strobe switch and an odd sense controlled switch connected in series between the odd sense node and the reference level, an odd sense controlled switch gate of the odd sense controlled switch connected to the odd sense node; the one of the odd numbered tiers of the plurality of sense amplifiers includes an odd local switch and an odd local bus controlled switch connected in series between the odd sense node and the reference level, an odd local bus controlled switch gate of the odd local bus controlled switch connected to the odd local data bus; and the one of the odd numbered tiers of the plurality of sense amplifiers includes an odd pre-charge switch connected between the supply level and the odd local data bus and an odd data bus connection switch connected between the data bus and the odd local data bus.
12. The controller as set forth in claim 10, wherein: a first one of the odd numbered tiers of the plurality of sense amplifiers and a first one of the even numbered tiers of the plurality of sense amplifiers are coupled together by a first data bus; a second one of the odd numbered tiers of the plurality of sense amplifiers and a second one of the even numbered tiers of the plurality of sense amplifiers are coupled together by a second data bus; the memory apparatus further includes a first supply switch and a first operation control switch connected in series between a supply level and a first even sense node of the first one of the even numbered tiers of the plurality of sense amplifiers, a first supply switch gate of the first supply switch connected to the first data bus; the memory apparatus further includes a second supply switch and a second operation control switch connected in series between the supply level and a second even sense node of the second one of the even numbered tiers of the plurality of sense amplifiers, a second supply switch gate of the second supply switch connected to the second data bus; the memory apparatus further includes a pass operation control switch connected between the first data bus and the second data bus; and the controller is in communication with to the first operation control switch and the second operation control switch and the pass operation control switch and further configured to instruct the memory apparatus to control the first operation control switch and the second operation control switch and the pass operation control switch to determine and re-latch the logical or results.
13. The controller as set forth in claim 12, wherein: the first one of the even numbered tiers of the plurality of sense amplifiers includes a first even transfer switch connecting the first even sense node to a first even local data bus and a first even strobe switch and a first even sense controlled switch connected in series between the first even transfer switch and a reference level, a first even sense controlled switch gate of the first even sense controlled switch connected to the first even sense node; the first one of the even numbered tiers of the plurality of sense amplifiers includes a first even local switch and a first even local bus controlled switch connected in series between the first even sense node and the reference level, a first even local bus controlled switch gate of the first even local bus controlled switch connected to the first even local data bus; the first one of the even numbered tiers of the plurality of sense amplifiers includes a first even pre-charge switch connected between the supply level and the first even local data bus and a first even data bus connection switch connected between the first data bus and the first even local data bus; the first one of the odd numbered tiers of the plurality of sense amplifiers includes a first odd transfer switch connecting a first odd sense node to a first odd local data bus and a first odd strobe switch and an odd sense controlled switch connected in series between the first odd transfer switch and the reference level, a first odd sense controlled switch gate of the first odd sense controlled switch connected to the first odd sense node; the first one of the odd numbered tiers of the plurality of sense amplifiers includes a first odd local switch and a first odd local bus controlled switch connected in series between the first odd sense node and the reference level, a first odd local bus controlled switch gate of the first odd local bus controlled switch connected to the first odd local data bus; the first one of the odd numbered tiers of the plurality of sense amplifiers includes a first odd pre-charge switch connected between the supply level and the first odd local data bus and a first odd data bus connection switch connected between the first data bus and the first odd local data bus; the second one of the even numbered tiers of the plurality of sense amplifiers includes a second even transfer switch connecting the second even sense node to a second even local data bus and a second even strobe switch and a second even sense controlled switch connected in series between the second even sense node and a reference level, a second even sense controlled switch gate of the second even sense controlled switch connected to the second even sense node; the second one of the even numbered tiers of the plurality of sense amplifiers includes a second even local switch and a second even local bus controlled switch connected in series between the second even sense node and the reference level, a second even local bus controlled switch gate of the second even local bus controlled switch connected to the second even local data bus; the second one of the even numbered tiers of the plurality of sense amplifiers includes a second even pre-charge switch connected between the supply level and the second even local data bus and a second even data bus connection switch connected between the second data bus and the second even local data bus; the second one of the odd numbered tiers of the plurality of sense amplifiers includes a second odd transfer switch connecting a second odd sense node to a second odd local data bus and a second odd strobe switch and an odd sense controlled switch connected in series between the second odd transfer switch and the reference level, a second odd sense controlled switch gate of the second odd sense controlled switch connected to the second odd sense node; the second one of the odd numbered tiers of the plurality of sense amplifiers includes a second odd local switch and a second odd local bus controlled switch connected in series between the second odd sense node and the reference level, a second odd local bus controlled switch gate of the second odd local bus controlled switch connected to the second odd local data bus; and the second one of the odd numbered tiers of the plurality of sense amplifiers includes a second odd pre-charge switch connected between the supply level and the second odd local data bus and a second odd data bus connection switch connected between the second data bus and the second odd local data bus.
14. A method of operating a memory apparatus including memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states, the memory cells disposed in memory holes each connected to one of a plurality of bit lines, each of the plurality of bit lines coupled to one of a plurality of sense amplifiers arranged in tiers, the method comprising the steps of: programing the memory cells in each of a plurality of program iterations of a program operation; and counting a failure quantity of a group of the memory cells having the threshold voltage below one of a plurality of verify voltages associated with one of the plurality of data states targeted for the memory cells in each of a plurality of verify iterations of the program operation, the count being a coarse count not separately counting the memory cells coupled with ones of the plurality of sense amplifiers of one or more of the tiers.
15. The method as set forth in claim 14, wherein the tiers include odd numbered tiers of the plurality of sense amplifiers and even numbered tiers of the plurality of sense amplifiers arranged in an alternating fashion vertically in a sense amplifier stack and the method further includes the steps of: logically oring data of the plurality of sense amplifiers of at least one of the odd numbered tiers with data of the plurality of sense amplifiers of at least one of the even numbered tiers to determine logical or results; storing the logical or results; and counting the failure quantity based on the logical or results for all of the odd numbered tiers of the plurality of sense amplifiers of all of the even numbered tiers.
16. The method as set forth in claim 15, wherein: one of the odd numbered tiers of the plurality of sense amplifiers and one of the even numbered tiers of the plurality of sense amplifiers are coupled together by a data bus; the memory apparatus further includes a supply switch and an operation control switch connected in series between a supply level and an even sense node of the one of the even numbered tiers of the plurality of sense amplifiers, a supply switch gate of the supply switch connected to the data bus; and the method further includes the step of controlling the operation control switch to determine and re-latch the logical or results.
17. The method as set forth in claim 16, wherein: the one of the even numbered tiers of the plurality of sense amplifiers includes an even transfer switch connecting the even sense node to an even local data bus and an even strobe switch and an even sense controlled switch connected in series between the even sense node and a reference level, an even sense controlled switch gate of the even sense controlled switch connected to the even sense node; the one of the even numbered tiers of the plurality of sense amplifiers includes an even local switch and an even local bus controlled switch connected in series between the even sense node and the reference level, an even local bus controlled switch gate of the even local bus controlled switch connected to the even local data bus; the one of the even numbered tiers of the plurality of sense amplifiers includes an even pre-charge switch connected between the supply level and the even local data bus and an even data bus connection switch connected between the data bus and the even local data bus; the one of the odd numbered tiers of the plurality of sense amplifiers includes an odd transfer switch connecting an odd sense node to an odd local data bus and an odd strobe switch and an odd sense controlled switch connected in series between the odd sense node and the reference level, an odd sense controlled switch gate of the odd sense controlled switch connected to the odd sense node; the one of the odd numbered tiers of the plurality of sense amplifiers includes an odd local switch and an odd local bus controlled switch connected in series between the odd sense node and the reference level, an odd local bus controlled switch gate of the odd local bus controlled switch connected to the odd local data bus; and the one of the odd numbered tiers of the plurality of sense amplifiers includes an odd pre-charge switch connected between the supply level and the odd local data bus and an odd data bus connection switch connected between the data bus and the odd local data bus.
18. The method as set forth in claim 15, wherein: a first one of the odd numbered tiers of the plurality of sense amplifiers and a first one of the even numbered tiers of the plurality of sense amplifiers are coupled together by a first data bus; a second one of the odd numbered tiers of the plurality of sense amplifiers and a second one of the even numbered tiers of the plurality of sense amplifiers are coupled together by a second data bus; the memory apparatus further includes a first supply switch and a first operation control switch connected in series between a supply level and a first even sense node of the first one of the even numbered tiers of the plurality of sense amplifiers, a first supply switch gate of the first supply switch connected to the first data bus; the memory apparatus further includes a second supply switch and a second operation control switch connected in series between the supply level and a second even sense node of the second one of the even numbered tiers of the plurality of sense amplifiers, a second supply switch gate of the second supply switch connected to the second data bus; the memory apparatus further includes a pass operation control switch connected between the first data bus and the second data bus; and the method further includes the step of controlling the first operation control switch and the second operation control switch and the pass operation control switch to determine and re-latch the logical or results.
19. The method as set forth in claim 18, wherein: the first one of the even numbered tiers of the plurality of sense amplifiers includes a first even transfer switch connecting the first even sense node to a first even local data bus and a first even strobe switch and a first even sense controlled switch connected in series between the first even transfer switch and a reference level, a first even sense controlled switch gate of the first even sense controlled switch connected to the first even sense node; the first one of the even numbered tiers of the plurality of sense amplifiers includes a first even local switch and a first even local bus controlled switch connected in series between the first even sense node and the reference level, a first even local bus controlled switch gate of the first even local bus controlled switch connected to the first even local data bus; the first one of the even numbered tiers of the plurality of sense amplifiers includes a first even pre-charge switch connected between the supply level and the first even local data bus and a first even data bus connection switch connected between the first data bus and the first even local data bus; the first one of the odd numbered tiers of the plurality of sense amplifiers includes a first odd transfer switch connecting a first odd sense node to a first odd local data bus and a first odd strobe switch and an odd sense controlled switch connected in series between the first odd transfer switch and the reference level, a first odd sense controlled switch gate of the first odd sense controlled switch connected to the first odd sense node; the first one of the odd numbered tiers of the plurality of sense amplifiers includes a first odd local switch and a first odd local bus controlled switch connected in series between the first odd sense node and the reference level, a first odd local bus controlled switch gate of the first odd local bus controlled switch connected to the first odd local data bus; the first one of the odd numbered tiers of the plurality of sense amplifiers includes a first odd pre-charge switch connected between the supply level and the first odd local data bus and a first odd data bus connection switch connected between the first data bus and the first odd local data bus; the second one of the even numbered tiers of the plurality of sense amplifiers includes a second even transfer switch connecting the second even sense node to a second even local data bus and a second even strobe switch and a second even sense controlled switch connected in series between the second even sense node and a reference level, a second even sense controlled switch gate of the second even sense controlled switch connected to the second even sense node; the second one of the even numbered tiers of the plurality of sense amplifiers includes a second even local switch and a second even local bus controlled switch connected in series between the second even sense node and the reference level, a second even local bus controlled switch gate of the second even local bus controlled switch connected to the second even local data bus; the second one of the even numbered tiers of the plurality of sense amplifiers includes a second even pre-charge switch connected between the supply level and the second even local data bus and a second even data bus connection switch connected between the second data bus and the second even local data bus; the second one of the odd numbered tiers of the plurality of sense amplifiers includes a second odd transfer switch connecting a second odd sense node to a second odd local data bus and a second odd strobe switch and an odd sense controlled switch connected in series between the second odd transfer switch and the reference level, a second odd sense controlled switch gate of the second odd sense controlled switch connected to the second odd sense node; the second one of the odd numbered tiers of the plurality of sense amplifiers includes a second odd local switch and a second odd local bus controlled switch connected in series between the second odd sense node and the reference level, a second odd local bus controlled switch gate of the second odd local bus controlled switch connected to the second odd local data bus; and the second one of the odd numbered tiers of the plurality of sense amplifiers includes a second odd pre-charge switch connected between the supply level and the second odd local data bus and a second odd data bus connection switch connected between the second data bus and the second odd local data bus.
20. The method as set forth in claim 14, further including the steps of: coarse counting the failure quantity of the group of the memory cells to determine a coarse count failure quantity; determining whether the failure quantity is less than a predetermined failure quantity threshold; and counting an actual failure quantity including separately counting the memory cells coupled with ones of the plurality of sense amplifiers of all of the tiers in response to the failure quantity being less than the predetermined failure quantity threshold.
Description
DRAWINGS
[0010] The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present disclosure.
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[0050] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.
DETAILED DESCRIPTION
[0051] In the following description, details are set forth to provide an understanding of the present disclosure. In some instances, certain circuits, structures and techniques have not been described or shown in detail in order not to obscure the disclosure.
[0052] In general, the present disclosure relates to non-volatile memory apparatuses of the type well-suited for use in many applications. The non-volatile memory apparatus and associated methods of operation of this disclosure will be described in conjunction with one or more example embodiments. However, the specific example embodiments disclosed are merely provided to describe the inventive concepts, features, advantages and objectives with sufficient clarity to permit those skilled in this art to understand and practice the disclosure. Specifically, the example embodiments are provided so that this disclosure will be thorough, and will fully convey the scope to those who are skilled in the art. Numerous specific details are set forth such as examples of specific components, devices, and methods, to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that specific details need not be employed, that example embodiments may be embodied in many different forms and that neither should be construed to limit the scope of the disclosure. In some example embodiments, well-known processes, well-known device structures, and well-known technologies are not described in detail.
[0053] Non-volatile memory cells are programmed by applying a programming signal as a series of programming voltage pulses (or other doses of programming) to selected memory cells and verifying the memory cells between programming voltage pulses. For memory devices storing data in a multi-level memory cell, or MLC, format, the memory device will typically perform multiple sensing operations as part of the verify process, both to distinguish between the different target data states and also as part of a coarse/fine (or quick pass write) programming process that uses a two-step verification for the same target data state. Consequently, the speed of a program operation is dependent upon how quickly the inter-pulse verify operations can be performed.
[0054] One way to perform sensing for a verity operation on a selected memory cell is to pre-charge a sensing node within a sense amplifier, discharge the sensing node for a sensing interval through the selected memory cell at a rate dependent the conductivity of the memory cell, and then determine whether the memory cell verifies based on the resultant amount of charge on the sense amplifier's sensing node. To determine whether the memory cell verifies as written to a target data state, the result of the sensing operation can be compared to values for the target data stored in latches of the sense amplifier structure by performing a series of logical operations between the sensed data and the values for the target data. A count of the memory cells that fail program-verily is typically done to determine whether another program pulse for the same data state is needed, however, such a count can be very time consuming.
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[0057] In one embodiment, there are a plurality of memory packages 104. Each memory package 104 may contain one or more memory dies. In one embodiment, each memory die in the memory package 104 utilizes NAND flash memory (including two dimensional NAND flash memory and/or three dimensional NAND flash memory). In other embodiments, the memory package 104 can include other types of memory; for example, the memory package can include Phase Change Memory (PCM) memory.
[0058] In one embodiment, memory controller 102 communicates with host system 120 using an interface 130 that implements NVM Express (NVMe) over PCI Express (PCIe). For working with storage system 100, host system 120 includes a host processor 122, host memory 124, and a PCIe interface 126, which communicate over bus 128. Host memory 124 is the host's physical memory, and can be DRAM, SRAM, non-volatile memory or another type of storage. Host system 120 is external to and separate from storage system 100. In one embodiment, storage system 100 is embedded in host system 120. In other embodiments, the controller 102 may communicate with host 120 via other types of communication buses and/or links, including for example, over an NVMe over Fabrics architecture, or a cache/memory coherence architecture based on Cache Coherent Interconnect for Accelerators (CCIX), Compute Express Link (CXL), Open Coherent Accelerator Processor Interface (OpenCAPI), Gen-Z and the like. For simplicity, the example embodiments below will be described with respect to a PCIe example.
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[0061] The ECC engines 226/256 are used to perform error correction, as known in the art. Herein, the ECC engines 226/256 may be referred to as controller ECC engines. The XOR engines 224/254 are used to XOR the data so that data can be combined and stored in a manner that can be recovered in case there is a programming error. In an embodiment, the XOR engines 224/254 are able to recover data that cannot be decoded using ECC engine 226/256.
[0062] Data path controller 222 is connected to a memory interface 228 for communicating via four channels with integrated memory assemblies. Thus, the top NOC 202 is associated with memory interface 228 for four channels for communicating with integrated memory assemblies and the bottom NOC 204 is associated with memory interface 258 for four additional channels for communicating with integrated memory assemblies. In one embodiment, each memory interface 228/258 includes four Toggle Mode interfaces (TM Interface), four buffers and four schedulers. There is one scheduler, buffer and TM Interface for each of the channels. The processor can be any standard processor known in the art. The data path controllers 222/252 can be a processor, FPGA, microprocessor or other type of controller. The XOR engines 224/254 and ECC engines 226/256 are dedicated hardware circuits, known as hardware accelerators. In other embodiments, the XOR engines 224/254, ECC engines 226/256 can be implemented in software. The scheduler, buffer, and TM Interfaces are hardware circuits. In other embodiments, the memory interface (an electrical circuit for communicating with memory dies) can be a different structure than depicted in
[0063]
[0064]
[0065] System control logic 360 receives data and commands from a host and provides output data and status to the host. In other embodiments, system control logic 360 receives data and commands from a separate controller circuit and provides output data to that controller circuit, with the controller circuit communicating with the host. In some embodiments, the system control logic 360 can include a state machine 362 that provides die-level control of memory operations. In one embodiment, the state machine 362 is programmable by software. In other embodiments, the state machine 362 does not use software and is completely implemented in hardware (e.g., electrical circuits). In another embodiment, the state machine 362 is replaced by a micro-controller or microprocessor, either on or off the memory chip. The system control logic 360 can also include a power control module 364 controls the power and voltages supplied to the rows and columns of the memory 302 during memory operations and may include charge pumps and regulator circuit for creating regulating voltages. System control logic 360 includes storage 366, which may be used to store parameters for operating the memory array 302.
[0066] Commands and data are transferred between the controller 102 and the memory die 300 via memory controller interface 368 (also referred to as a communication interface). Memory controller interface 368 is an electrical interface for communicating with memory controller 102. Examples of memory controller interface 368 include a Toggle Mode Interface and an Open NAND Flash Interface (ONFI). Other I/O interfaces can also be used. For example, memory controller interface 368 may implement a Toggle Mode Interface that connects to the Toggle Mode interfaces of memory interface 228/258 for memory controller 102. In one embodiment, memory controller interface 368 includes a set of input and/or output (I/O) pins that connect to the controller 102.
[0067] In some embodiments, all of the elements of memory die 300, including the system control logic 360, can be formed as part of a single die. In other embodiments, some or all of the system control logic 360 can be formed on a different die.
[0068] For purposes of this document, the phrase one or more control circuits can include a controller, a state machine, a micro-controller, micro-processor, and/or other control circuitry as represented by the system control logic 360, or other analogous circuits that are used to control non-volatile memory.
[0069] In one embodiment, memory structure 302 comprises a three dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory that are monolithically formed in one or more physical levels of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping.
[0070] In another embodiment, memory structure 302 comprises a two dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR-type flash memory) can also be used.
[0071] The exact type of memory array architecture or memory cell included in memory structure 302 is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure 302. No particular non-volatile memory technology is required for purposes of the new claimed embodiments proposed herein. Other examples of suitable technologies for memory cells of the memory structure 302 include ReRAM memories (resistive random access memories), magnetoresistive memory (e.g., MRAM, Spin Transfer Torque MRAM, Spin Orbit Torque MRAM), FeRAM, phase change memory (e.g., PCM), and the like. Examples of suitable technologies for memory cell architectures of the memory structure 302 include two dimensional arrays, three dimensional arrays, cross-point arrays, stacked two dimensional arrays, vertical bit line arrays, and the like.
[0072] One example of a ReRAM cross-point memory includes reversible resistance-switching elements arranged in cross-point arrays accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state change element based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases causing the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory element may have a wide range of programming thresholds over temperature.
[0073] Another example is magnetoresistive random access memory (MRAM) that stores data by magnetic storage elements. The elements are formed from two ferromagnetic layers, each of which can hold a magnetization, separated by a thin insulating layer. One of the two layers is a permanent magnet set to a particular polarity; the other layer's magnetization can be changed to match that of an external field to store memory. A memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through them, an induced magnetic field is created. MRAM based memory embodiments will be discussed in more detail below.
[0074] Phase change memory (PCM) exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTeSb2Te3 super lattice to achieve non-thermal phase changes by simply changing the co-ordination state of the Germanium atoms with a laser pulse (or light pulse from another source). Therefore, the doses of programming are laser pulses. The memory cells can be inhibited by blocking the memory cells from receiving the light. In other PCM embodiments, the memory cells are programmed by current pulses. Note that the use of pulse in this document does not require a square pulse but includes a (continuous or non-continuous) vibration or burst of sound, current, voltage light, or other wave. These memory elements within the individual selectable memory cells, or bits, may include a further series element that is a selector, such as an ovonic threshold switch or metal insulator substrate.
[0075] A person of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, memory construction or material composition, but covers many relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of ordinary skill in the art.
[0076] The elements of
[0077] Another area in which the memory structure 302 and the peripheral circuitry are often at odds is in the processing involved in forming these regions, since these regions often involve differing processing technologies and the trade-off in having differing technologies on a single die. For example, when the memory structure 302 is NAND flash, this is an NMOS structure, while the peripheral circuitry is often CMOS based. For example, elements such sense amplifier circuits, charge pumps, logic elements in a state machine, and other peripheral circuitry in system control logic 360 often employ PMOS devices. Processing operations for manufacturing a CMOS die will differ in many aspects from the processing operations optimized for an NMOS flash NAND memory or other memory cell technologies.
[0078] To improve upon these limitations, embodiments described below can separate the elements of
[0079]
[0080]
[0081] System control logic 360, row control circuitry 320, and column control circuitry 310 may be formed by a common process (e.g., CMOS process), so that adding elements and functionalities, such as ECC, more typically found on a memory controller 102 may require few or no additional process steps (i.e., the same process steps used to fabricate controller 102 may also be used to fabricate system control logic 360, row control circuitry 320, and column control circuitry 310). Thus, while moving such circuits from a die such as memory structure die 301 may reduce the number of steps needed to fabricate such a die, adding such circuits to a die such as control die 311 may not require any additional process steps. The control die 311 could also be referred to as a CMOS die, due to the use of CMOS technology to implement some or all of control circuitry 360, 310, 320.
[0082]
[0083] For purposes of this document, the phrase one or more control circuits can include one or more of controller 102, system control logic 360, column control circuitry 310, row control circuitry 320, a micro-controller, a state machine, and/or other control circuitry, or other analogous circuits that are used to control non-volatile memory. The one or more control circuits can include hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is one example of a control circuit. A control circuit can include a processor, FGA, ASIC, integrated circuit, or other type of circuit.
[0084]
[0085] Sense module 450 comprises sense circuitry 460 that determines whether a conduction current in a connected bit line is above or below a predetermined level or, in voltage based sensing, whether a voltage level in a connected bit line is above or below a predetermined level. The sense circuitry 460 is to receive control signals from the state machine via input lines 471. In some embodiments, sense module 450 includes a circuit commonly referred to as a sense amplifier. Sense module 450 also includes a bit line latch 468 that is used to set a voltage condition on the connected bit line. For example, a predetermined state latched in bit line latch 468 will result in the connected bit line being pulled to a state designating program inhibit (e.g., Vdd).
[0086] Common portion 480 comprises a processor 468, a set of data latches 484 and an I/O Interface 488 coupled between the set of data latches 484 and data bus 318. Processor 468 performs computations. For example, one of its functions is to determine the data stored in the sensed memory cell and store the determined data in the set of data latches. The set of data latches 484 is used to store data bits determined by processor 468 during a read operation. It is also used to store data bits imported from the data bus 318 during a program operation. The imported data bits represent write data meant to be programmed into the memory. V/O interface 488 provides an interface between data latches 484 and the data bus 318.
[0087] During read or sensing, the operation of the system is under the control of state machine 362 that controls (using power control 364) the supply of different control gate or other bias voltages to the addressed memory cell(s). As it steps through the various predefined control gate voltages corresponding to the various memory states supported by the memory, the sense module 450 may trip at one of these voltages and an output will be provided from sense module 450 to processor 468 via bus 454. At that point, processor 468 determines the resultant memory state by consideration of the tripping event(s) of the sense module and the information about the applied control gate voltage from the state machine via input lines 490. It then computes a binary encoding for the memory state and stores the resultant data bits into data latches 484. In another embodiment of the core portion, bit line latch 468 serves double duty, both as a latch for latching the output of the sense module 450 and also as a bit line latch as described above.
[0088] Data latch stack 484 contains a stack of data latches corresponding to the sense module. In one embodiment, there are three, four or another number of data latches per sense module 450. In one embodiment, the latches are each one bit. In this document, the latches in one embodiment of data latch stack 484 will be referred to as SDL, XDL, ADL, BDL, and CDL. In the embodiments discussed here, the latch XDL is a transfer latch used to exchange data with the I/O interface 488. In addition to a first sense amp data latch SDL, the additional latches ADL, BDL and CDL can be used to hold multi-state data, where the number of such latches typically reflects the number of bits stored in a memory cell. For example, in 3-bit per cell multi-level cell (MLC) memory format, the three sets of latches ADL, BDL, CDL can be used for upper, middle, lower page data. In 2-bit per cell embodiment, only ADL and BDL might be used, while a 4-bit per cell MLC embodiment might include a further set of DDL latches. In other embodiments, the XDL latches can be used to hold additional pages of data, such as a 4-bit per cell MLC embodiment the uses the XDL latches in addition to the three sets of latches ADL, BDL, CDL for four pages of data. The following discussion will mainly focus on a 3-bit per cell embodiment, as this can illustrate the main features but not get overly complicated, but the discussion can also be applied to embodiments with more or fewer bit per cell formals. Some embodiments many also include additional latches for particular functions, such as represented by the TDL latch where, for example, this could be used in quick pass write operations where it is used in program operations for when a memory cell is approaching its target state and is partially inhibited to slow its programming rate. In embodiments discussed below, the latches ADL, BDL, . . . can transfer data between themselves and the bit line latch 468 and with the transfer latch XDL, but not directly with the I/O interface 488, so that a transfer from these latches to the I/O interface is transferred by way of the XDL latches.
[0089] For example, in some embodiments data read from a memory cell or data to be programmed into a memory cell will first be stored in XDL. In case the data is to be programmed into a memory cell, the system can program the data into the memory cell from XDL. In one embodiment, the data is programmed into the memory cell entirely from XDL before the next operation proceeds. In other embodiments, as the system begins to program a memory cell through XDL, the system also transfers the data stored in XDL into ADL in order to reset XDL. Before data is transferred from XDL into ADL, the data kept in ADL is transferred to BDL, flushing out whatever data (if any) is being kept in BDL, and similarly for BDL and CDL. Once data has been transferred from XDL into ADL, the system continues (if necessary) to program the memory cell through ADL, while simultaneously loading the data to be programmed into a memory cell on the next word line into XDL, which has been reset. By performing the data load and programming operations simultaneously, the system can save time and thus perform a sequence of such operations faster.
[0090] During program or verify, the data to be programmed is stored in the set of data latches 484 from the data bus 318. During the verify process, Processor 468 monitors the verified memory state relative to the desired memory state. When the two are in agreement, processor 468 sets the bit line latch 468 so as to cause the bit line to be pulled to a state designating program inhibit. This inhibits the memory cell coupled to the bit line from further programming even if it is subjected to programming pulses on its control gate. In other embodiments the processor initially loads the bit line latch 468 and the sense circuitry sets it to an inhibit value during the verify process.
[0091] In some implementations (but not required), the data latches are implemented as a shift register so that the parallel data stored therein is converted to serial data for data bus 318, and vice versa. In one preferred embodiment, all the data latches corresponding to the read/write block of m memory cells can be linked together to form a block shift register so that a block of data can be input or output by serial transfer. In particular, the bank of read/write modules is adapted so that each of its set of data latches will shift data in to or out of the data bus in sequence as if they are part of a shift register for the entire read/write block.
[0092]
[0093] In some embodiments, there is more than one control die 311 and more than one memory structure die 301 in an integrated memory assembly 307. In some embodiments, the integrated memory assembly 307 includes a stack of multiple control die 311 and multiple memory structure die 301.
[0094] Each control die 311 is affixed (e.g., bonded) to at least one of the memory structure dies 301. Some of the bond pads 570, 574, are depicted. There may be many more bond pads. A space between two dies 301, 311 that are bonded together is filled with a solid layer 548, which may be formed from epoxy or other resin or polymer. This solid layer 548 protects the electrical connections between the dies 301, 311, and further secures the dies together. Various materials may be used as solid layer 548, but in embodiments, it may be Hysol epoxy resin from Henkel Corp., having offices in California, USA.
[0095] The integrated memory assembly 307 may for example be stacked with a stepped offset, leaving the bond pads at each level uncovered and accessible from above. Wire bonds 506 connected to the bond pads connect the control die 311 to the substrate 502. A number of such wire bonds may be formed across the width of each control die 311 (i.e., into the page of
[0096] A memory structure die through silicon via (TSV) 512 may be used to route signals through a memory structure die 301. A control die through silicon via (TSV) 514 may be used to route signals through a control die 311. The TSVs 512, 514 may be formed before, during or after formation of the integrated circuits in the semiconductor dies 301, 311. The TSVs may be formed by etching holes through the wafers. The holes may then be lined with a barrier against metal diffusion. The barrier layer may in turn be lined with a seed layer, and the seed layer may be plated with an electrical conductor such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof may be used.
[0097] Solder balls 508 may optionally be affixed to contact pads 510 on a lower surface of substrate 502. The solder balls 508 may be used to electrically and mechanically couple the integrated memory assembly 307 to a host device such as a printed circuit board. Solder balls 508 may be omitted where the integrated memory assembly 307 is to be used as an LGA package. The solder balls 508 may form a part of the interface between the integrated memory assembly 307 and the memory controller 102.
[0098]
[0099] Some of the bond pads 570, 574 are depicted. There may be many more bond pads. A space between two dies 301, 311 that are bonded together is filled with a solid layer 548, which may be formed from epoxy or other resin or polymer. In contrast to the example in
[0100] Solder balls 508 may optionally be affixed to contact pads 510 on a lower surface of substrate 502. The solder balls 508 may be used to electrically and mechanically couple the integrated memory assembly 307 to a host device such as a printed circuit board. Solder balls 508 may be omitted where the integrated memory assembly 307 is to be used as an LGA package.
[0101] As has been briefly discussed above, the control die 311 and the memory structure die 301 may be bonded together. Bond pads on each die 301, 311 may be used to bond the two dies together. In some embodiments, the bond pads are bonded directly to each other, without solder or other added material, in a so-called Cu-to-Cu bonding process. In a Cu-to-Cu bonding process, the bond pads are controlled to be highly planar and formed in a highly controlled environment largely devoid of ambient particulates that might otherwise settle on a bond pad and prevent a close bond. Under such properly controlled conditions, the bond pads are aligned and pressed against each other to form a mutual bond based on surface tension. Such bonds may be formed at room temperature, though heat may also be applied. In embodiments using Cu-to-Cu bonding, the bond pads may be about 5 m square and spaced from each other with a pitch of 5 m to 5 m. While this process is referred to herein as Cu-to-Cu bonding, this term may also apply even where the bond pads are formed of materials other than Cu.
[0102] When the area of bond pads is small, it may be difficult to bond the semiconductor dies together. The size of, and pitch between, bond pads may be further reduced by providing a film layer on the surfaces of the semiconductor dies including the bond pads. The film layer is provided around the bond pads. When the dies are brought together, the bond pads may bond to each other, and the film layers on the respective dies may bond to each other. Such a bonding technique may be referred to as hybrid bonding. In embodiments using hybrid bonding, the bond pads may be about 5 m square and spaced from each other with a pitch of 1 m to 5 m. Bonding techniques may be used providing bond pads with even smaller sizes and pitches.
[0103] Some embodiments may include a film on surface of the dies 301, 311. Where no such film is initially provided, a space between the dies may be under filled with an epoxy or other resin or polymer. The under-fill material may be applied as a liquid which then hardens into a solid layer. This under-fill step protects the electrical connections between the dies 301, 311, and further secures the dies together. Various materials may be used as under-fill material, but in embodiments, it may be Hysol epoxy resin from Henkel Corp., having offices in California, USA.
[0104]
[0105]
[0106]
[0107]
[0108]
[0109] The block depicted in
[0110] Although
[0111]
[0112]
[0113] For ease of reference, drain side select layers SGD0, SGD1, SGD2 and SGD3; source side select layers SGS0, SGS1, SGS2 and SGS3; dummy word line layers DD0, DD1, DS0 and DS1; and word line layers WLL0-WLL47 collectively are referred to as the conductive layers. In one embodiment, the conductive layers are made from a combination of TIN and tungsten. In other embodiments, other materials can be used to form the conductive layers, such as doped polysilicon, metal such as tungsten or metal silicide. In some embodiments, different conductive layers can be formed from different materials. Between conductive layers are dielectric layers DL0-DL59. For example, dielectric layers DL49 is above word line layer WLL43 and below word line layer WLL44. In one embodiment, the dielectric layers are made from SiO.sub.2. In other embodiments, other dielectric materials can be used to form the dielectric layers.
[0114] The non-volatile memory cells are formed along vertical columns which extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings. The word line layer WLL0-WLL47 connect to memory cells (also called data memory cells). Dummy word line layers DD0, DD1, DS0 and DS1 connect to dummy memory cells. A dummy memory cell does not store user data, while a data memory cell is eligible to store user data. Drain side select layers SGD0, SGD1, SGD2 and SGD3 are used to electrically connect and disconnect NAND strings from bit lines. Source side select layers SGS0, SGS1, SGS2 and SGS3 are used to electrically connect and disconnect NAND strings from the source line SL.
[0115] In some embodiments, the word lines are read sequentially, which means that the word lines are read either from low to high (e.g., WLL0 to WLL47) or from high to low (e.g., WLL47 to WLL0). It is not required to read the entire set of word lines when reading sequentially. Techniques are disclosed herein for providing compensation for interference caused by adjacent memory cells on target memory cells during a sequential read.
[0116] In some embodiments, the read of an individual word line is broken down into separate reads of sub-blocks. Referring again to
[0117]
[0118]
[0119] Note that the charge trapping layer 673 may extend from one end of the NAND string to the other, and hence may be referred to herein as a continuous charge trapping layer. When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer 673 which is associated with the memory cell. These electrons are drawn into the charge trapping layer 673 from the channel 671, through the tunneling dielectric 672, in response to an appropriate voltage on word line region 676. The Vt of a memory cell is increased in proportion to the amount of stored charge. In one embodiment, the programming is achieved through Fowler-Nordheim tunneling of the electrons into the charge trapping layer. During an erase operation, the electrons return to the channel or holes are injected into the charge trapping layer to recombine with electrons. In one embodiment, erasing is achieved using hole injection into the charge trapping layer via a physical mechanism such as gate induced drain leakage (GIDL).
[0120]
[0121] Although the example memory system of
[0122] The memory systems discussed above can be erased, programmed and read. At the end of a successful programming process (with verification), the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate.
[0123]
[0124]
[0125]
[0126]
[0127] In one embodiment, known as full sequence programming, memory cells can be programmed from the erased data state S0 directly to any of the programmed data states S1-S7. For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state S0. Then, a programming process is used to program memory cells directly into data states S1, S2, S3, S4, S5, S6, and/or S7. For example, while some memory cells are being programmed from data state S0 to data state S1, other memory cells are being programmed from data state S0 to data state S2 and/or from data state S0 to data state S3, and so on. The arrows of
[0128] Each threshold voltage distribution (data state) of
[0129]
[0130] In general, during verify operations and read operations, the selected word line is connected to a voltage (one example of a reference signal), a level of which is specified for each read operation (e.g., see read reference voltages Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7, of
[0131] There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured by the rate it discharges or charges a dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or fails to allow) the NAND string that includes the memory cell to discharge a corresponding bit line. The voltage on the bit line is measured after a period of time to see whether it has been discharged or not. Note that the technology described herein can be used with different methods known in the art for verifying/reading. Other read and verify techniques known in the art can also be used.
[0132]
[0133] Typically, a programming signal Vpgm is applied to the control gates (via a selected word line) during a program operation as a series of programming voltage pulses, as depicted in
[0134] In step 874, the appropriate memory cells are verified using the appropriate set of verify reference voltages to perform one or more verify operations. In one embodiment, the verification process is performed by testing whether the threshold voltages of the memory cells selected for programming have reached the appropriate verity reference voltage.
[0135] In step 876, it is determined whether all the memory cells have reached their target threshold voltages (pass). If so, the programming process is complete and successful because all selected memory cells were programmed and verified to their target states. A status of PASS (or success) is reported in step 878. If, in 876, it is determined that not all of the memory cells have reached their target threshold voltages (fail), then the programming process continues to step 880.
[0136] In step 880, the system counts the number of memory cells that have not yet reached their respective target threshold voltage distribution. That is, the system counts the number of memory cells that have, so far, failed the verify process. This counting can be done by the state machine 362, the controller 102, or other logic. In one implementation, each of the sense blocks will store the status (pass/fail) of their respective memory cells. In one embodiment, there is one total count, which reflects the total number of memory cells currently being programmed that have failed the last verify step. In another embodiment, separate counts are kept for each data state.
[0137] In step 882, it is determined whether the count from step 880 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is a number of bits that can be corrected by error correction codes (ECC) during a read process for the page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, then the programming process can stop and a status of PASS is reported in step 878. In this situation, enough memory cells programmed correctly such that the few remaining memory cells that have not been completely programmed can be corrected using ECC during the read process. In some embodiments, step 880 will count the number of failed cells for each sector, each target data state or other unit, and those counts will individually or collectively be compared to one or more thresholds in step 882.
[0138] In one embodiment, the predetermined limit can be less than the total number of bits that can be corrected by ECC during a read process to allow for future errors. When programming less than all of the memory cells for a page, or comparing a count for only one data state (or less than all states), than the predetermined limit can be a portion (pro-rata or not pro-rata) of the number of bits that can be corrected by ECC during a read process for the page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors already counted for the page, the number of program-erase cycles performed or other criteria.
[0139] If number of failed memory cells is not less than the predetermined limit, than the programming process continues at step 884 and the program counter PC is checked against the program limit value (PL). Examples of program limit values include 6, 20 and 30; however, other values can be used. If the program counter PC is not less than the program limit value PL, then the program process is considered to have failed and a status of FAIL is reported in step 888. If the program counter PC is less than the program limit value PL, then the process continues at step 886 during which time the Program Counter PC is incremented by 1 and the program voltage Vpgm is stepped up to the next magnitude. For example, the next pulse will have a magnitude greater than the previous pulse by a step size (e.g., a step size of 0.1-0.4 volts). After step 886, the process loops back to step 872 and another program pulse is applied to the selected word line so that another iteration (steps 872-886) of the programming process of
[0140] Because it is possible that errors can occur when programming or reading, and errors can occur while storing data (e.g., due to electrons drifting, data retention issues or other phenomenon), error correction is used with the programming of data. Memory systems often use Error Correction Codes (ECC) to protect data from corruption. Many ECC coding schemes are well known in the art. These conventional error correction codes are especially useful in large scale memories, including flash (and other non-volatile) memories, because of the substantial impact on manufacturing yield and device reliability that such coding schemes can provide, rendering devices that have a few non-programmable or defective cells as useable. Of course, a tradeoff exists between the yield savings and the cost of providing additional memory cells to store the code bits (i.e., the code rate). As such, some ECC codes are better suited for flash memory devices than others. Generally, ECC codes for flash memory devices tend to have higher code rates (i.e., a lower ratio of code bits to data bits) than the codes used in data communications applications (which may have code rates as low as ). Examples of well-known ECC codes commonly used in connection with flash memory storage include Reed-Solomon codes, other BCH codes, Hamming codes, and the like. Sometimes, the error correction codes used in connection with flash memory storage are systematic, in that the data portion of the eventual code word is unchanged from the actual data being encoded, with the code or parity bits appended to the data bits to form the complete code word.
[0141] The particular parameters for a given error correction code include the type of code, the size of the block of actual data from which the code word is derived, and the overall length of the code word after encoding. For example, a typical BCH code applied to a sector of 512 bytes (4096 bits) of data can correct up to four error bits, if at least 60 ECC or parity bits are used. Reed-Solomon codes are a subset of BCH codes, and are also commonly used for error correction. For example, a typical Reed-Solomon code can correct up to four errors in a 512 byte sector of data, using about 72 ECC bits. In the flash memory context, error correction coding provides substantial improvement in manufacturing yield, as well as in the reliability of the flash memory over time.
[0142] In some embodiments, controller 102 receives host data (also referred to as user data or data from an entity external to the memory system), also referred to as information bits, that is to be stored non-volatile memory structure 302. The informational bits are represented by the matrix i=[1 0] (note that two bits are used for example purposes only, and many embodiments have code words longer than two bits). An error correction coding process (such as any of the processes mentioned above or below) is implemented by ECC engine 226/256 of controller 102 in which parity bits are added to the informational bits to provide data represented by the matrix or code word v=[1 0 1 0], indicating that two parity bits have been appended to the data bits. Other techniques can be used that map input data to output data in more complex manners. For example, low density parity check (LDPC) codes, also referred to as Gallager codes, can be used. More details about LDPC codes can be found in R. G. Gallager, Low-density parity-check codes, IRE Trans. Inform. Theory, vol. IT-8, pp. 21 28, January 1962; and D. Mackay, Information Theory, Inference and Learning Algorithms, Cambridge University Press 2003, chapter 47. In practice, such LDPC codes are typically applied (e.g., by ECC engine 226/256) to multiple pages encoded across a number of storage elements, but they do not need to be applied across multiple pages. The data bits can be mapped to a logical page and stored in memory structure 302 by programming one or more memory cells to one or more programming states, which corresponds to v.
[0143] In one embodiment, programming serves to raise the threshold voltage of the memory cells to one of the programmed data states S1-S7. Erasing serves to lower the threshold voltage of the memory cells to the Erase data state S0.
[0144] One technique to erase memory cells in some memory devices is to bias a p-well (or other types of) substrate to a high voltage to charge up a NAND channel. An erase enable voltage is applied to control gates of memory cells while the NAND channel is at a high voltage to erase the non-volatile storage elements (memory cells). Another approach to erasing memory cells is to generate gate induced drain leakage (GIDL) current to charge up the NAND string channel. An erase enable voltage is applied to control gates of the memory cells, while maintaining the string channel potential to erase the memory cells.
[0145] In one embodiment, the GIDL current is generated by causing a drain-to-gate voltage at a select transistor. A transistor drain-to-gate voltage that generates a GIDL current is referred to herein as a GIDL voltage. The GIDL current may result when the select transistor drain voltage is significantly higher than the select transistor control gate voltage. GIDL current is a result of carrier generation, i.e., electron-hole pair generation due to band-to-band tunneling and/or trap-assisted generation. In one embodiment, GIDL current may result in one type of carriers, e.g., holes, predominantly moving into NAND channel, thereby raising potential of the channel. The other type of carriers, e.g., electrons, are extracted from the channel, in the direction of a bit line or in the direction of a source line, by an electric field. During erase, the holes may tunnel from the channel to a charge storage region of memory cells and recombine with electrons there, to lower the threshold voltage of the memory cells.
[0146] The GIDL current may be generated at either end of the NAND string. A first GIDL voltage may be created between two terminals of a select transistor (e.g., drain side select transistor) that is connected to a bit line to generate a first GIDL current. A second GIDL voltage may be created between two terminals of a select transistor (e.g., source side select transistor) that is connected to a source line to generate a second GIDL current. Erasing based on GIDL current al only one end of the NAND string is referred to as a one-sided GIDL erase. Erasing based on GIDL current at both ends of the NAND string is referred to as a two-sided GIDL erase.
[0147] As discussed above,
[0148]
[0149]
[0150] In step 962, the system performs verification for data state S2. For example, the system tests whether memory cells being programmed to data state S2 have threshold voltages greater than Vv2 (e.g., applying verify voltage pulse v2 of
[0151] In step 964, the system performs verification for data state S3. For example, the system tests whether memory cells being programmed to data state S3 have threshold voltages greater than Vv3 (e.g., applying verify voltage pulse v3 of
[0152] In step 966, the system performs verification for data state S4. For example, the system tests whether memory cells being programmed to data state S4 have threshold voltages greater than Vv4 (e.g., applying verify voltage pulses v4 of
[0153] In step 968, the system performs verification for data state S5. For example, the system tests whether memory cells being programmed to data state S5 have threshold voltages greater than Vv5 (e.g., applying verify voltage pulses v5 of
[0154] In step 970, the system performs verification for data state S6. For example, the system tests whether memory cells being programmed to data state S6 have threshold voltages greater than Vv6 (e.g., applying verify voltage pulse v6 of
[0155] In step 972, the system performs verification for data state S7. For example, the system tests whether memory cells being programmed to data state S7 have threshold voltages greater than Vv7 (e.g., applying verify voltage pulse v7 of
[0156] The flow of
[0157] An important aspect of the performance of a non-volatile memory device is the speed with which sensing operations, both for reads and program verifies, can be performed. Considering the case of a program verify, as described above with respect to
[0158]
[0159] In a sense operation, a selected memory cell is biased by setting its corresponding selected word line to a read voltage level as described above. In a NAND array implementation, the selected gates and the non-selected word lines of the selected word line's NAND string are also biased to be on. Once the array is biased, the selected memory cell will conduct a level based on the relation of applied read voltage to the memory cell's threshold voltage. The capacitor 1325 can be used to store charge on the SEN node 1305, where, during pre-charging, the level CLK (and lower plate of capacitor 1325) can be set to a low voltage (e.g., ground or VSS) so that the voltage on the SEN node 1305 is referenced to this low voltage. The pre-charged SEN node 1305 of a selected memory is connected to the corresponding bit line 1309 by way XXL 1319 and BLS 1327 to the selected bit lines and allowed to discharge for a sensing interval to a level dependent on the threshold voltage of the memory cell relative to the voltage level applied to the control gate of the selected memory cell. At the end of the sensing interval, XXL 1319 can be turned off to trap the resultant charge on SEN 1305. At this point, the CLK level can be raised somewhat, similarly raising the voltage on SEN 1305, to account for voltage drops across intervening elements (such as XXL 1319) in the discharge path. Consequently, the voltage level on SEN 1305 that controls the degree to which the transistor 1317 is on will reflect to the data state of the selected memory cell relative the applied read voltage. The local data LBUS 1301 is also pre-charged, so that when the strobe transistor STB 1315 is turned on for a strobing interval, LBUS will discharge to the CLK node as determined by the voltage level on SEN 1305. At the end of the strobe interval, STB 1315 is turned off to set the sensed value on LBUS and the result can be latched into one of the latches along LBUS 1301 or DBUS as illustrated in
[0160] Before a subsequent seeing operation can be performed using the sense amplifier, the node SEN 1305 needs to be available for pre-charging for the subsequent operation. To verify whether a memory cell has been programmed to its target data state, read data from the sensing operation is compared to the target data as stored in the latches associated with the local data bus LBUS 1301, where the latches can each store a value for the pages as described with respect to
[0161] As discussed above with respect to the embodiment of
[0162]
[0163]
[0164] The latch XDL 1551 of
[0165] Concerning the use of the various latches associated with a given sense amplifier, the data latch SDL 1401 can be used to store a bit to determine whether the bit line should be program enabled or program inhibited. If the embodiment is a quick pass write embodiment, the TDL latch can be used to determine whether the bit line should be partially inhibited to allow programming, but at a slower rate, and the XDL, ADL, BDL, ands CDL latches can be used to store to the bits of the target state of the upper, upper-middle, lower-middle, and lower page value of a 4-bit per memory cell embodiment. In a sensing operation for performing a verify phase of a program loop, the target data is loaded into the XDL, ADL, BDL, and CDL latches and the resultant level on the SEN or LBUS nodes is checked against the stored target data by forming various logical combinations of the latched XDL, ADL, BDL, and CDL target data values to determine whether the memory cell is programmed. For example, to set the value of the SDL latch to determine whether, at the next programming pulse, a selected memory cell should be program enable or programmed inhibited, values such as S=.sup.X & A & B & .sup.C, S=.sup.X & A & .sup.B & C, or S=.sup.X & A & .sup.B & .sup.C are determined, where (X, A, B, C) denote the values latched in (XDL, ADL, BDL, CDL), denotes NOT, & denotes AND, and (as used further below) | denotes OR. As illustrated by the latch structures of
[0166] To compute these logical combinations of values of the sensed value and the latched target values stored in the XDL, ADL, BDL, CDL nodes, the SEN node itself can be used to compute these values. Considering a particular example of S=.sup.X & A & .sup.B & .sup.C, this can be formed by the following steps or OPCODE sequence, beginning by initializing the SEN node:
TABLE-US-00001 SEN=1 SEN=.sup.~X SEN=A & SEN SEN=.sup.~B & SEN SEN=.sup.~C & SEN S=0 S=SEN|S
[0167] In these steps, the SEN node 1305 is used to form and temporally store the intermediate logical combinations that are part of the sensing operation, with the result stored in the SDL latch. As long as the SEN node 1305 is being used for forming these logical combinations, the SEN node 1305 cannot be pre-charged as part of a subsequent sensing operation.
[0168] In some embodiments, within the column structure sensing of all of the tiers can be done at the same time to increase parallelism. Although this increases parallelism, this can lead to spikes in current consumption, since all of the SEN nodes would be pre-charged concurrently. To reduce these spikes, the tiers can be split into sub-sets with their operations interleaved. For example, the tiers can be split into even and odd tiers, corresponding to even and odd bit lines and sequence of operations in the preceding paragraph (beginning with SEN=1 and following on to S=SEN|S) can be interleaved between even and odd tiers. However, for both the odd tiers and the even tiers, until the logical combinations using the SEN node of one sensing operation is complete, the SEN node cannot be pre-charged to begin the next sensing operation on a bit line, limiting the degree of parallelism and resultant memory performance.
[0169] To be able to free up the SEN node 1305 sooner so that it can be pre-charged for the following sensing operation, the embodiment of
[0170] As discussed above, a count of the memory cells that fail program-verity is typically done to determine whether another program pulse for the same data state is needed, however, such a count can be very time consuming. In more detail, it is desirable to have a faster program time tPROG time for memory die, however, program time tPROG is partly limited by a BITSCAN time during the program-verify operation. Such a BITSCAN operation is to count a number of failures during program-verify to determine if next program pulse for same data state is required. The program time tPROG time increases due to increases the number of SA (sense-amplifier) tiers being scanned. Some part of the BITSCAN time is hidden, but overflow increases with increase in tier count involved in the BITSCAN.
[0171]
[0172] Consequently, described herein is a memory apparatus (e.g., storage system 100 of
[0173] As shown in
[0174] Once there is a pass using the coarse count, a normal bitscan can be done for actual NF value (i.e., the tolerable failure count or predetermined failure quantity threshold). Thus, according to another aspect of the disclosure, the control means is further configured to coarse count the failure quantity of the group of the memory cells to determine a coarse count failure quantity. In addition, the control means is configured to determine whether the failure quantity is less than a predetermined failure quantity threshold. The control means is also configured to count an actual failure quantity including separately counting the memory cells coupled with ones of the plurality of sense amplifiers of all of the tiers in response to the failure quantity being less than the predetermined failure quantity threshold.
[0175] If two tiers are grouped together during bitscan, then there is a chance the errors may be uncounted if the same bit line on the two tiers both have errors. There are three possibilities. Assuming the true bit-error is p: 1) both tiers have an error, p{circumflex over ()}2, 2) only one tier has an error, 2p(1p), and 3) neither tier has an error, (1p){circumflex over ()}2. When counting failures of every tier, the first possibility (#1) is counted as one error. The second possibility (#2) is counted as one error. For the memory apparatus and method disclosed herein using the coarse counting, both errors are counted as a single error. This undercounts the error, so a condition that should have barely failed bit-scan now is interpreted as a pass. The overall inaccuracy can be quantified by comparing the true bit-error with what the coarse counting result would be. Again if the true error is p, the coarse counting results in (1probability of #3)/(# of groupings), so, (1(1p){circumflex over ()}2)/2.
[0176] In more detail, the true error of interest is the BSPF and tier-scan option chosen. Ultimately, it is desirable to know if a condition that barely fails bitscan may instead be mistaken for a pass. As an example, if p is the true error rate, p equals BSPF/[(# of Tiers)(S/A per tier)], which equals BSPF/[(# of Tiers)(9168)]. Then, if m is a measured error rate, m equals (1probability of #3)/(# of groupings), which equals (1(1p){circumflex over ()}2)/2. So the looser the BSPF setting, the higher the allowed error-rate. This in turns leads to potentially more inaccuracy. In an example memory apparatus, the loosest BSPF is for G-complete equals=240b using 2-tier. So, p equals 240/(29168)=0.01309 and m equals (1(10.01309){circumflex over ()}2)/2=0.01300 In terms of percentage inaccuracy, 1p/m=0.65%. Out of a BSPF of 240 b, this is only 1 or 2 bits. In other words, there may be a situation where there are 242 fail-bits which should technically be a fail, but the proposed coarse counting scheme interprets this as 240 fail-bits and calls this a pass. Under most circumstances, this level of inaccuracy is acceptable.
[0177]
[0178]
[0179] In more detail and according to additional aspects, the one of the even numbered tiers of the plurality of sense amplifiers 2202 includes an even transfer switch BLQ 2214 connecting the even sense node 2210 to an even local data bus LBUS 2216 and an even strobe switch STB 2218 and an even sense controlled switch 2220 connected in series between the even sense node 2210 and a reference level VLOP. An even sense controlled switch gate 2222 of the even sense controlled switch 2220 is connected to the even sense node 2210. The one of the even numbered tiers of the plurality of sense amplifiers 2202 includes an even local switch LSL 2224 and an even local bus controlled switch 2226 connected in series between the even sense node 2210 and the reference level VLOP. An even local bus controlled switch gate 2228 of the even local bus controlled switch 2226 is connected to the even local data bus LBUS 2216. In addition, the one of the even numbered tiers of the plurality of sense amplifiers 2202 includes an even pre-charge switch 2230 connected between the supply level VHLB and the even local data bus 2216 and an even data bus connection switch 2232 connected between the data bus DBUS 2204 and the even local data bus 2216. The one of the odd numbered tiers of the plurality of sense amplifiers 2200 additionally includes an odd transfer switch BLQ 2234 connecting an odd sense node 2236 to an odd local data bus LBUS 2238 and an odd strobe switch STB 2240 and an odd sense controlled switch 2242 connected in series between the odd sense node 2236 and the reference level VLOP. An odd sense controlled switch gate 2244 of the odd sense controlled switch 2242 is connected to the odd sense node 2236. Additionally, the one of the odd numbered tiers of the plurality of sense amplifiers 2200 includes an odd local switch LSL 2246 and an odd local bus controlled switch 2248 connected in series between the odd sense node 2236 and the reference level VLOP. An odd local bus controlled switch gate 2250 of the odd local bus controlled switch 2248 is connected to the odd local data bus LBUS 2238. The one of the odd numbered tiers of the plurality of sense amplifiers 2200 also includes an odd pre-charge switch 2252 connected between the supply level VHLB and the odd local data bus 2238 and an odd data bus connection switch 2254 connected between the data bus DBUS 2204 and the odd local data bus 2238. Thus, the new SA structure of
[0180]
[0181] More specifically and according to further aspects, the first one of the even numbered tiers of the plurality of sense amplifiers 2302 includes a first even transfer switch BLQ 2330 connecting the first even sense node 2316 to a first even local data bus LBUS 2332 and a first even strobe switch STB 2334 and a first even sense controlled switch 2336 connected in series between the first even transfer switch BLQ 2330 and a reference level VLOP. A first even sense controlled switch gate 2338 of the first even sense controlled switch 2336 is connected to the first even sense node 2316. The first one of the even numbered tiers of the plurality of sense amplifiers 2302 additionally includes a first even local switch LSL 2340 and a first even local bus controlled switch 2342 connected in series between the first even sense node 2316 and the reference level VLOP. A first even local bus controlled switch gate 2344 of the first even local bus controlled switch 2342 is connected to the first even local data bus LBUS 2332. Furthermore, the first one of the even numbered tiers of the plurality of sense amplifiers 2302 includes a first even pre-charge switch 2346 connected between the supply level VHLB and the first even local data bus 2332 and a first even data bus connection switch 2348 connected between the first data bus 2304 and the first even local data bus 2332.
[0182] In addition, the first one of the odd numbered tiers of the plurality of sense amplifiers 2300 includes a first odd transfer switch BLQ 2350 connecting a first odd sense node 2352 to a first odd local data bus LBUS 2354 and a first odd strobe switch STB 2356 and an odd sense controlled switch 2358 connected in series between the first odd transfer switch BLQ 2350 and the reference level VLOP. A first odd sense controlled switch gate 2360 of the first odd sense controlled switch 2358 is connected to the first odd sense node 2352. The first one of the odd numbered tiers of the plurality of sense amplifiers 2300 further includes a first odd local switch LSL 2362 and a first odd local bus controlled switch 2364 connected in series between the first odd sense node 2352 and the reference level VLOP. A first odd local bus controlled switch gate 2366 of the first odd local bus controlled switch 2364 is connected to the first odd local data bus LBUS 2354. Additionally, the first one of the odd numbered tiers of the plurality of sense amplifiers 2300 includes a first odd pre-charge switch 2368 connected between the supply level VHLB and the first odd local data bus 2354 and a first odd data bus connection switch 2370 connected between the first data bus 2304 and the first odd local data bus 2354.
[0183] The second one of the even numbered tiers of the plurality of sense amplifiers 2308 includes a second even transfer switch BLQ 2372 connecting the second even sense node 2324 to a second even local data bus LBUS 2374 and a second even strobe switch STB 2376 and a second even sense controlled switch 2378 connected in series between the second even sense node 2324 and a reference level VLOP. A second even sense controlled switch gate 2380 of the second even sense controlled switch 2378 connected to the second even sense node 2324. Also, the second one of the even numbered tiers of the plurality of sense amplifiers 2308 includes a second even local switch LSL 2382 and a second even local bus controlled switch 2384 connected in series between the second even sense node 2324 and the reference level VLOP. A second even local bus controlled switch gate 2386 of the second even local bus controlled switch 2384 is connected to the second even local data bus LBUS 2374. In addition, the second one of the even numbered tiers of the plurality of sense amplifiers 2308 includes a second even pre-charge switch 2388 connected between the supply level VHLB and the second even local data bus 2374 and a second even data bus connection switch 2390 connected between the second data bus 2310 and the second even local data bus 2374.
[0184] The second one of the odd numbered tiers of the plurality of sense amplifiers 2306 includes a second odd transfer switch BLQ 2392 connecting a second odd sense node 2394 to a second odd local data bus LBUS 2396 and a second odd strobe switch STB 2398 and an odd sense controlled switch 2400 connected in series between the second odd transfer switch BLQ 2392 and the reference level VLOP. A second odd sense controlled switch gate 2402 of the second odd sense controlled switch 2400 is connected to the second odd sense node 2394. Additionally, the second one of the odd numbered tiers of the plurality of sense amplifiers 2306 includes a second odd local switch LSL 2404 and a second odd local bus controlled switch 2406 connected in series between the second odd sense node 2394 and the reference level VLOP. A second odd local bus controlled switch gate 2408 of the second odd local bus controlled switch 2406 is connected to the second odd local data bus LBUS 2396. The second one of the odd numbered tiers of the plurality of sense amplifiers 2306 also includes a second odd pre-charge switch 2410 connected between the supply level VHLB and the second odd local data bus 2396 and a second odd data bus connection switch 2412 connected between the second data bus 2310 and the second odd local data bus 2396.
[0185] As an alternative to making changes to the structure of sense amplifiers described above and if any data latch is free to store the logical or result, the sense node SEN stores original TAG data. A new OPCODE can then be inserted to do the logical or operation of consecutive sense amplifiers, as follows: TDL=0.fwdarw.TDL=TDL|SEN.fwdarw.SENe (sense node of even sense amplifier)=SENo (sense node of odd sense amplifier).fwdarw.TDL=TDL|SEN.fwdarw.TAG=TDL (only for even sense amplifier tier). While this OPCODE performs a 2:1 logical or, the opcode sequence can be repeated twice to get a 4:1 logical or operation.
[0186]
[0187]
[0188]
[0189] Referring back to
[0190] Again, once there is a pass using the coarse count, a normal bitscan can be done for actual NF value (i.e., the tolerable failure count or predetermined failure quantity threshold). So, according to another aspect of the disclosure, the method further includes the step of coarse counting the failure quantity of the group of the memory cells to determine a coarse count failure quantity. Additionally, the method also includes the step of determining whether the failure quantity is less than a predetermined failure quantity threshold. The next step of the method is counting an actual failure quantity including separately counting the memory cells coupled with ones of the plurality of sense amplifiers of all of the tiers in response to the failure quantity being less than the predetermined failure quantity threshold.
[0191] As discussed above and referring back to
[0192] Again, in more detail and according to additional aspects, the one of the even numbered tiers of the plurality of sense amplifiers 2202 includes an even transfer switch BLQ 2214 connecting the even sense node 2210 to an even local data bus LBUS 2216 and an even strobe switch STB 2218 and an even sense controlled switch 2220 connected in series between the even sense node 2210 and a reference level VLOP. An even sense controlled switch gate 2222 of the even sense controlled switch 2220 is connected to the even sense node 2210. The one of the even numbered tiers of the plurality of sense amplifiers 2202 includes an even local switch LSL 2224 and an even local bus controlled switch 2226 connected in series between the even sense node 2210 and the reference level VLOP. An even local bus controlled switch gate 2228 of the even local bus controlled switch 2226 is connected to the even local data bus LBUS 2216. Additionally, the one of the even numbered tiers of the plurality of sense amplifiers 2202 includes an even pre-charge switch 2230 connected between the supply level VHLB and the even local data bus 2216 and an even data bus connection switch 2232 connected between the data bus DBUS 2204 and the even local data bus 2216. The one of the odd numbered tiers of the plurality of sense amplifiers 2200 additionally includes an odd transfer switch BLQ 2234 connecting an odd sense node 2236 to an odd local data bus LBUS 2238 and an odd strobe switch STB 2240 and an odd sense controlled switch 2242 connected in series between the odd sense node 2236 and the reference level VLOP. An odd sense controlled switch gate 2244 of the odd sense controlled switch 2242 is connected to the odd sense node 2236. Additionally, the one of the odd numbered tiers of the plurality of sense amplifiers 2200 includes an odd local switch LSL 2246 and an odd local bus controlled switch 2248 connected in series between the odd sense node 2236 and the reference level VLOP. The odd local bus controlled switch gate 2250 of the odd local bus controlled switch 2248 connected to the odd local data bus LBUS 2238. The one of the odd numbered tiers of the plurality of sense amplifiers 2200 also includes an odd pre-charge switch 2252 connected between the supply level VHLB and the odd local data bus 2238 and an odd data bus connection switch 2254 connected between the data bus DBUS 2204 and the odd local data bus 2238.
[0193] Referring back to
[0194] In more detail and according to further aspects, the first one of the even numbered tiers of the plurality of sense amplifiers 2302 includes a first even transfer switch BLQ 2330 connecting the first even sense node 2316 to a first even local data bus LBUS 2332 and a first even strobe switch STB 2334 and a first even sense controlled switch 2336 connected in series between the first even transfer switch BLQ 2330 and a reference level VLOP. A first even sense controlled switch gate 2338 of the first even sense controlled switch 2336 is connected to the first even sense node 2316. The first one of the even numbered tiers of the plurality of sense amplifiers 2302 additionally includes a first even local switch LSL 2340 and a first even local bus controlled switch 2342 connected in series between the first even sense node 2316 and the reference level VLOP. A first even local bus controlled switch gate 2344 of the first even local bus controlled switch 2342 is connected to the first even local data bus LBUS 2332. Moreover, the first one of the even numbered tiers of the plurality of sense amplifiers 2302 includes a first even pre-charge switch 2346 connected between the supply level VHLB and the first even local data bus 2332 and a first even data bus connection switch 2348 connected between the first data bus 2304 and the first even local data bus 2332.
[0195] Further, the first one of the odd numbered tiers of the plurality of sense amplifiers 2300 includes a first odd transfer switch BLQ 2350 connecting a first odd sense node 2352 to a first odd local data bus LBUS 2354 and a first odd strobe switch STB 2356 and an odd sense controlled switch 2358 connected in series between the first odd transfer switch BLQ 2350 and the reference level VLOP. A first odd sense controlled switch gate 2360 of the first odd sense controlled switch 2358 is connected to the first odd sense node 2352. The first one of the odd numbered tiers of the plurality of sense amplifiers 2300 further includes a first odd local switch LSL 2362 and a first odd local bus controlled switch 2364 connected in series between the first odd sense node 2352 and the reference level VLOP. A first odd local bus controlled switch gate 2366 of the first odd local bus controlled switch 2364 is connected to the first odd local data bus LBUS 2354. Additionally, the first one of the odd numbered tiers of the plurality of sense amplifiers 2300 includes a first odd pre-charge switch 2368 connected between the supply level VHLB and the first odd local data bus 2354 and a first odd data bus connection switch 2370 connected between the first data bus 2304 and the first odd local data bus 2354.
[0196] The second one of the even numbered tiers of the plurality of sense amplifiers 2308 includes a second even transfer switch BLQ 2372 connecting the second even sense node 2324 to a second even local data bus LBUS 2374 and a second even strobe switch STB 2376 and a second even sense controlled switch 2378 connected in series between the second even sense node 2324 and a reference level VLOP. A second even sense controlled switch gate 2380 of the second even sense controlled switch 2378 is connected to the second even sense node 2324. Also, the second one of the even numbered tiers of the plurality of sense amplifiers 2308 includes a second even local switch LSL 2382 and a second even local bus controlled switch 2384 connected in series between the second even sense node 2324 and the reference level VLOP. A second even local bus controlled switch gate 2386 of the second even local bus controlled switch 2384 is connected to the second even local data bus LBUS 2374. In addition, the second one of the even numbered tiers of the plurality of sense amplifiers 2308 includes a second even pre-charge switch 2388 connected between the supply level VHLB and the second even local data bus 2374 and a second even data bus connection switch 2390 connected between the second data bus 2310 and the second even local data bus 2374.
[0197] The second one of the odd numbered tiers of the plurality of sense amplifiers 2306 includes a second odd transfer switch BLQ 2392 connecting a second odd sense node 2394 to a second odd local data bus LBUS 2396 and a second odd strobe switch STB 2398 and an odd sense controlled switch 2400 connected in series between the second odd transfer switch BLQ 2392 and the reference level VLOP. A second odd sense controlled switch gate 2402 of the second odd sense controlled switch 2400 is connected to the second odd sense node 2394. Additionally, the second one of the odd numbered tiers of the plurality of sense amplifiers 2306 includes a second odd local switch LSL 2404 and a second odd local bus controlled switch 2406 connected in series between the second odd sense node 2394 and the reference level VLOP. A second odd local bus controlled switch gate 2408 of the second odd local bus controlled switch 2406 is connected to the second odd local data bus LBUS 2396. The second one of the odd numbered tiers of the plurality of sense amplifiers 2306 also includes a second odd pre-charge switch 2410 connected between the supply level VHLB and the second odd local data bus 2396 and a second odd data bus connection switch 2412 connected between the second data bus 2310 and the second odd local data bus 2396.
[0198] Referring back to
[0199] Clearly, changes may be made to what is described and illustrated herein without, however, departing from the scope defined in the accompanying claims. The foregoing description of the embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and can be used in a selected embodiment, even if not specifically shown or described. The same may also be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.