Module comprising a switchable bypass device

Abstract

A module (100) is specified, the module (100) comprising a first module connection (108), a second module connection (109), an energy store (105), a first electrical switch (101) and a second electrical switch (102), wherein a switchable bypass device (1) is arranged between the first module connection (108) and the second module connection (109) and wherein the switchable bypass device (1) is configured to remain in a bidirectional current conducting state in response to a single trigger pulse.

Claims

1. A module comprising a first module connection and a second module connection, an energy store, and a first electrical switch and a second electrical switch, wherein a switchable bypass device is arranged between the first module connection and the second module connection, wherein the switchable bypass device is configured to remain in a bidirectional current conducting state in response to a single trigger pulse, the switchable bypass device in the bidirectional current conducting state forms an electrical bypass between the first module connection and the second module connection bypassing the energy store, the first electrical switch and the second electrical switch, the switchable bypass device comprises a semiconductor body extending between a first main surface and a second main surface, wherein the switchable bypass device comprises a first main electrode arranged on the first main surface, and a second main electrode arranged on the second main surface, the semiconductor body comprises a first base layer of a first conductivity type, a second base layer of the first conductivity type, and a third base layer of a second conductivity type different than the first conductivity type arranged between the first base layer and the second base layer, the first main electrode acts as a cathode for a first thyristor functional element and as an anode for a second thyristor functional element of the switchable bypass device, the semiconductor body is configured with respect to a charge carrier recombination lifetime such that the switchable bypass device does not turn off in response to a voltage commutation, and a turn-off of the switchable bypass device occurs if the switchable bypass device is brought below its holding current.

2. The module according to claim 1, wherein the first main electrode adjoins at least one first emitter region of the second conductivity type and at least one first emitter short region of the first conductivity type, and the first main electrode acts as the cathode for the first thyristor functional element via the first emitter region and as the anode for the second thyristor functional element via the first emitter short region.

3. The module according to claim 1, wherein each of the first thyristor functional element and the second thyristor functional element uses an entire area of a p-n junction formed between the first base layer and the third base layer.

4. The module according to of claim 2, wherein the second main electrode adjoins at least one second emitter region of the second conductivity type and at least one second emitter short region of the first conductivity type.

5. The module according to claim 4, wherein at least one first emitter region overlaps with a second emitter short region when seen onto the first main surface.

6. The module according to claim 4, wherein an arrangement of first emitter regions and first emitter short regions on the first main surface differs from an arrangement of second emitter regions and second emitter short regions on the second main surface.

7. The module according to claim 1, wherein the switchable bypass device comprises a first gate electrode on the first main surface, and wherein the first main electrode comprises a plurality of first segments that are spaced apart from one another, wherein at least some of the first segments are completely surrounded by the first gate electrode in a view onto the first main surface.

8. The module according to claim 7, wherein the switchable bypass device comprises a second gate electrode on the second main surface and the second main electrode comprises a plurality of second segments that are spaced apart from one another, wherein at least some of the second segments are completely surrounded by the second gate electrode in a view onto the second main surface.

9. The module according to claim 1, wherein the module is configured as a half-bridge arrangement or as a full-bridge arrangement.

10. The module according to claim 1, wherein the module is configured for a modular multi-level converter.

11. The module according to claim 1, wherein the module comprises a further switchable bypass device connected in parallel to the switchable bypass device.

12. The module according to claim 1, wherein the module is configured to be triggered electrically or optically.

13. The module according to claim 1, wherein the switchable bypass device is configured to be triggered in the event of a fault within the module or of an external fault causing a voltage applied to the module that exceeds a predetermined value.

Description

(1) In the figures:

(2) FIG. 1 shows an exemplary embodiment of a module;

(3) FIG. 2 shows a further exemplary embodiment of a module;

(4) FIG. 3 shows an exemplary embodiment of a switchable bypass device;

(5) FIG. 4A shows measurements of current and voltage as a function of time for an exemplary embodiment of a switchable bypass device;

(6) FIGS. 4B, 4C, and 4D show schematic illustrations of the charge carrier distribution within the switchable bypass device at three different stages of FIG. 4A;

(7) FIG. 5A shows a detail of an exemplary embodiment of a switchable bypass device in top view;

(8) FIG. 5B shows a cross-sectional view of the switchable bypass device of FIG. 5A;

(9) FIG. 6 shows a detail of a further exemplary embodiment of a switchable bypass device in cross-sectional view.

(10) The elements illustrated in the figures and their size relationships among one another are not necessarily true to scale. Rather, individual elements or layer thicknesses may be represented with an exaggerated size for the sake of better representability and/or for the sake of better understanding.

(11) An exemplary embodiment of a module 100 is illustrated in FIG. 1.

(12) The module 100 is configured as a half bridge cell of an MMC for instance. The module 100 comprises an energy store 105, a first switch 101 and a second switch 102. The module 100 further comprises a first module connection 108 and a second module connection 109.

(13) At least one of the first and second switches may comprise an IGBT (insulated gate bipolar transistor) for instance.

(14) The module 100 further comprises a switchable bypass device 1 arranged between the first module connection 108 and the second module connection 109. During regular operation of the module 100 the switchable bypass device 1 is in a non-conducting OFF state so that there is no current flow through the switchable bypass device 1. The voltage between the first module connection 108 and the second module connection 109 depends on the state of the first switch 101 and the second switch 102. If the first switch 101 is open and the second switch 102 is closed, the voltage difference between the first module connection 108 and the second module connection 109 corresponds to the voltage of the energy store 105. If the first switch 101 is closed and the second switch 102 is open there is no, or at least no significant, voltage difference between the first module connection 108 and the second module connection 109.

(15) In the case of a fault the switchable bypass device 1 may be switched into the ON state so that there is an electrical bypass between the first module connection 108 and the second module connection 109 circumventing the energy store 105 and the first and second switches 101, 102.

(16) For example, the switchable bypass device 1 includes a first thyristor functional element 11 and a second thyristor functional element 12 arranged in anti-parallel and integrated into a common semiconductor body. Exemplary embodiments of the switchable bypass device 1 are described in more detail in connection with FIGS. 3 through 6.

(17) The module 100 may further comprise a further bypass 10 which may be, for example, a mechanical switch. A mechanical switch can be used to release the switchable bypass device 1 from too heavy loading, for instance during a too long fault event. For example, the switchable bypass device 1 and the further bypass device 10 may be triggered simultaneously. A mechanical switch can be also used for protection under the condition of zero supply voltage of the MMC system.

(18) Due to the high reliability of the switchable bypass device 1, the mechanical switch may be dispensed with, for example if the case of zero voltage at the MMC is avoided by other means. For example, the switchable bypass device may be configured such that it irreversibly switches into a permanent short circuit state in the event of a predetermined amount of overload. For example, a conduction path within the switchable bypass device is formed by melting if the predefined amount of overload is reached.

(19) A single trigger pulse is sufficient for the switchable bypass device 1 to stay permanently in the ON state until the switchable bypass device 1 is shorted by the further bypass device 10 or until the fault is cleared. This is described in more detail in connection with FIGS. 4A to 4C.

(20) The triggering may be performed via an electrical signal. However, an optical triggering may also be used. In the case of electrical triggering via a gate electrode of the switchable bypass device, the turn-on order in the event of a fault may be given such that the gate electrode, for which the polarity of the voltage between anode and cathode corresponds to that of the forward blocking of the corresponding thyristor function of the switchable bypass device, will be provided with the triggering pulse.

(21) The triggering may also be performed via an electrical or optical signal brought into the two gates at the same time. The control system controlling the module then does not need not to take into account the polarity of the anode to cathode voltage. For all the triggering options, only a single gate trigger pulse is needed to activate the protection. This represents substantial simplification compared to prior art.

(22) A further example for a critical internal fault is a valve AC terminal earth fault within the MMC so that some of the cells may experience an abnormally high voltage due to excessive charge. In this case a turn-on order may be sent to the switchable bypass device 1 which will prevent further charging of the cell. Thus, an over-voltage on the cell will be prevented. Due to the internal fault of the MMC the whole MMC will be shut down so that the current through the switchable bypass device 1 will be zero in the end. This will switch the switchable bypass device 1 into the OFF (or open) state so that the module will function as normal when the module is energized for the next time.

(23) The exemplary embodiment shown in FIG. 2 essentially corresponds to that described in connection with FIG. 1. In departure therefrom the module 100 is configured as a full-bridge arrangement with two additional switches, namely a third switch 103 and a fourth switch 104. Using a full-bridge arrangement three different voltage levels between the first module connection 108 and the second module connection 109 may be obtained. Compared to the half-bridge arrangement, this is, however, at the expense of additional switches.

(24) If the first switch 101 and the third switch 103 are closed, the voltage between the first and second module connection 108, 109 corresponds to the positive voltage of the energy store 105.

(25) If, on the other hand, the second switch 102 and the fourth switch 104 are closed, the voltage corresponds to the negative voltage of the energy store 105. If the second switch 102 and the third switch 103 or the first switch 101 and the fourth switch 104 are closed, the voltage at the first and second module connection is zero.

(26) The switchable bypass device 1 is also suited for other modules that require a bypass protection.

(27) FIG. 3 illustrates an exemplary embodiment of a switchable bypass device 1 in a schematic cutaway view. The switchable bypass device 1 comprises a semiconductor body 2 extending between a first main surface 21 and a second main surface 22.

(28) The semiconductor body comprises a first base layer 51 of a first conductivity type, a second base layer 52 of the first conductivity type and a third base layer 53 of a second conductivity type different than the first conductivity type arranged between the first base layer 51 and the second base layer 52 in vertical direction. A first main electrode 31 is arranged on the first main surface 21 and a second main electrode 32 is arranged on the second main surface 22. For instance, the first conductivity type is p-type and the second conductivity type is n-type or vice versa.

(29) The first main electrode 31 acts as a cathode for a first thyristor functional element 11 and as an anode for a second thyristor functional element 12. For the second thyristor functional element 12 the first main electrode 31 acts as an anode via the first emitter short region 71. The first thyristor functional element 11 and the second thyristor functional element 12 are illustrated in FIG. 3 using arrows. These functional elements represent two antiparallel connected thyristor structures arranged within the same semiconductor body 2.

(30) The first main electrode 31 adjoins at least one first emitter region 61 of the second conductivity type and a plurality of first emitter short regions 71 of the first conductivity type.

(31) The second main electrode adjoins at least one second emitter region 62 of the second conductivity type and at a plurality of second emitter short region 72 of the first conductivity type. The first thyristor functional element 11 is formed in this embodiment by the second emitter short region 72 acting as an anode, the second base layer 52, the third base layer 53, the first base layer 51 and the first emitter region 61.

(32) Accordingly, the second thyristor functional element 12 is formed by the first emitter short region 71 acting as an anode, the first base layer 51, the third base layer 53, the second base layer 52 and the second emitter region 62. Consequently, the emitter short regions 71, 72 also fulfil the function of an anode for the associated antiparallel thyristor functional element.

(33) Between the first base layer 51 and the third base layer 53 as well as between the third base layer 53 and the second base layer 52 p-n junctions extending over the entire area of the semiconductor body 2 are formed. Both the first thyristor functional element 11 and the second thyristor functional element 12 may thus use the entire area of these p-n junctions. A high surge current capability close to that of a single thyristor of the same size may be obtained in this manner.

(34) The semiconductor body 2 comprises silicon, for example. However, other semiconductor materials may also be used, for instance SiC (silicon carbide).

(35) The switchable bypass device 1 further comprises a first gate electrode 41 on the first main surface 21 and a second gate electrode 42 on the second main surface 22. A switchable bypass device 1 having two gate electrodes may be turned on with respect to both current directions.

(36) However, one of the first and second gate electrodes 41, 42 may also be dispensed with.

(37) The first gate electrode 41 forms an ohmic contact with the first base layer 51 via a first gate contact region 91 of the semiconductor body 2 adjoining the first main surface 21. The second gate electrode 42 forms an ohmic contact with the second base layer 52 via a second gate contact region 92 of the semiconductor body 2 adjoining the second main surface 22. The first gate contact region 91 and the second gate contact region 92 are of the same conductivity type as the first base layer 51.

(38) In the exemplary embodiment shown an amplifying gate structure 8 is integrated into the first gate electrode 41 and the second gate electrode 42. The amplifying gate structure 8 comprises a section 80 of the first gate electrode 41. For example, the section 80 is formed as a ring extending around a first gate electrode pad. The first gate electrode pad is configured as an external contact for the application of an external trigger current to the first gate electrode 41. The section 80 overlaps with a first partial region 81 of the first conductivity type and a second partial region 82 of the second conductivity type. This results in an amplification of current pulses applied to the first gate electrode 41 via the first gate electrode pad. In principle, this is a Darlington configuration of two bipolar transistors integrated within a thyristor body.

(39) The semiconductor body 2 is configured with respect to a charge carrier recombination lifetime such that the switchable bypass device 1 does not turn off in response to a voltage commutation. This is described in connection with FIGS. 4A through 4D.

(40) FIG. 4A shows exemplarily the measured voltage V and the current I as a function of time around the zero voltage (or current) crossing point during an approximately linear decrease of the current I. FIGS. 4B to 4D illustrate the charge carrier distributions between the first main electrode 31 and the second main electrode 32 for three different stages, labeled as 4B, 4C and 4D in FIG. 4A.

(41) In the stage 4B the first main electrode 31 acts as an anode and the second main electrode 32 acts as a cathode. A large number of electrons and holes is available in the semiconductor body 2 as schematically illustrated in FIG. 4B.

(42) At the zero voltage crossing point, labelled as 4C in FIG. 4A, the number of available charge carriers decreases but the lifetime of the charge carriers is so long that the formation of a space charge region is prevented (FIG. 4C). As the switchable bypass device 1 is not fully depleted from the free charge carriers, it can go back to the ON state just with changed polarity of the current (stage 4D illustrated in FIG. 4D). In stage 4D the first main electrode 31 acts as cathode and the second main electrode 32 as anode for the antiparallel thyristor functional element.

(43) This means that the switchable bypass device 1 represents an AC switch which remains in the ON state if the polarity of the voltage between the first and second main electrodes 31, 32 changes. For example, the frequency is at least 50 Hz. Therefore a single trigger pulse via one gate electrode is sufficient to switch the switchable bypass device 1 into the ON state for both polarities. Thus, one of the first and second gate electrodes may be omitted.

(44) If the switchable bypass device comprised two individual separate thyristor elements instead, the thyristor elements would have to be triggered each time the polarity of the voltage changes. This is a problem especially for the large-area thyristors with relatively slow turn-on due to the limited speed of lateral plasma (conducting area) spreading during the turn-on process.

(45) At least one of the first gate electrode 41 and the second gate electrode 42 may comprise several branches in order to improve the distribution of the gate pulses over the area of the switchable bypass device 1. For example, a structure resembling a snowflake may be formed by the branches. The first and second main electrodes 31, 32 are configured in each case as contiguous elements.

(46) The semiconductor body 2 may be a full wafer. However, the semiconductor body 2 may also be a part of a wafer, so that the switchable bypass device 1 is a chip obtained by singulation of a processed wafer into individual devices. In this case, the switchable bypass device may comprise a planar pn junction termination, for example using guard rings or a variation lateral doping (VLD). At the same time deep p-type sinks may be provided for reverse blocking capability.

(47) The exemplary embodiment of a switchable bypass device shown in FIGS. 5A and 5B essentially corresponds to that described in connection with FIG. 3.

(48) In departure therefrom, the first main electrode 31 comprises a plurality of first segments 310 that are spaced apart from one another. At least some of the first segments 310, for instance at least 50%, or at least 90% or all of the first segments are completely surrounded by the first gate electrode 41 in a view onto the first main surface 21.

(49) The first gate electrode 41 comprises a first grid structure 411 connected to a first gate electrode pad (not shown in the Figure).

(50) Each of the first segments 310 of the first main electrode 31 adjoin at least one first emitter region 61 of the second conductivity type and at least one first emitter short region 71 of the first conductivity type.

(51) In the exemplary embodiments shown in FIG. 5A the first grid structure 411 comprises a plurality of first cells 4110 of hexagonal shape thereby forming a honeycomb structure. However, other polygonal first cells may also apply for the first grid structure 411, for example tetragons or octagons.

(52) As illustrated in the cross-sectional view of FIG. 5B, a second main electrode 32 and a second gate electrode 42 are arranged on a second main surface 22 of the semiconductor body. Like the first main electrode 31, the second main electrode 32 is split into a plurality of second segments 320. At least some of the second segments 320, for instance at least 50%, or at least 90% or all of the second segments 320 are completely surrounded by the second gate electrode 42 in a view onto the second main surface 22.

(53) Each of the second segments 320 of the second main electrode 32 adjoins at least one second emitter region 62 of the second conductivity type and at least one second emitter short region 72 of the first conductivity type.

(54) During operation of the switchable bypass device 1 the first segments 310 of the first main electrode 31 may be electrically contacted to the same electrical potential, for instance by pressing a conductive plate or conductive wafer against the first main electrode 31. As shown in FIG. 5B, the thickness of the first gate electrode 41 within the first grid structure 411 is smaller than that of the first main electrode 31. Thus, the first grid structure 411 does not form an electrical contact to the plate or wafer. This applies to the second main electrode 32 as well.

(55) The number of cells may vary in wide limits depending on the intended application of the switchable bypass device, for instance between 10 and 5000. For example, a device with a diameter of 100 mm may comprise several hundred first cells formed by the first grid structure 411.

(56) A view onto the first main surface 21 may correspond to a view onto the second main surface 22. Therefore, views onto the second main surface 22 are not explicitly shown in the Figures. Features and parameters described in connection with the configuration on the first main surface 21, for example in connection with the first main electrode 31, the first gate electrode 41, the first grid structure 411, the first cells 4110, the first emitter region 61 and the first emitter short region 71 may likewise also apply for the corresponding element on the second main surface 22, for example for the second main electrode 32, the second gate electrode 42, the second grid structure 421, the second cells 4210, the second emitter region 62, and the second emitter short region 72, respectively.

(57) A length L1 of one side 4111 of the first cells 4110 is between 500 m and 5000 m or between 900 m and 3000 m inclusive, for instance. The larger the length L1, the larger the contiguous area of the first segments 310 of the first main electrode 31.

(58) A width W1 of one side of at least one of the first cells 4110 is between 100 m and 2000 m inclusive, for instance between 100 m and 500 m. The width of the sides together with their thickness define the cross-section of the first grid structure 411. The thickness of the first grid structure 411 is between 3 m and 30 m inclusive or between 5 m and 12 m inclusive, for instance. For instance, using these parameters the cross-section of the first grid structure 411 is big enough to avoid a significant voltage drop along the gate path from the first gate electrode pad to the outermost areas of the first grid structure 411.

(59) The terms length and width refer to extensions in lateral direction. Thicknesses refer to the extent in vertical direction, i.e. perpendicular to the first main surface.

(60) A maximum lateral extent E1 of the first emitter short regions 71 is between 50 m and 1000 m or between 100 m and 500 m inclusive, for instance.

(61) An edge-to-edge distance D1 between two emitter short regions 71 within the same first cell is between 200 m and 1000 m inclusive or between 300 m and 500 m inclusive, for instance. The distance between the emitter short regions may be chosen appropriately to provide sufficiently high dV/dt.

(62) An edge-to-edge distance D2 between the first grid structure 411 and the first emitter short region arranged closest to the first grid structure is between 50 m and 400 m or between 100 m and 200 m inclusive, for instance.

(63) The above parameters may take into account design rules that do not apply for existing device concepts. For instance this is because the emitter short regions on the cathode side of one thyristor functional element act as anode regions for the antiparallel thyristor functional element at the same time.

(64) Differing from FIG. 5A, for instance, first emitter short regions 71 arranged within one first cell may also have different values for the maximum lateral extent. For example the emitter short regions arranged closer to the edge of the first segments may be smaller than the maximum lateral extent of a first emitter short region arranged closer to the center of the respective first segment.

(65) Alternatively or in addition, the first emitter short region 71 in the center may be replaced by several smaller first emitter short regions 71.

(66) For example, first emitter short regions 71 arranged close to the edge of the first cell may have a diameter between 100 m and 250 m inclusive wherein first emitter short region 71 arranged closer to the center of the cell may have a diameter between 150 m and 500 m inclusive.

(67) In the example shown in FIG. 5B, each first segment 310 overlaps with a plurality of first emitter short regions 71 wherein one first emitter short region 71 is arranged in the center of the first segment 310, whereas the further first emitter short regions 71 are arranged along the circumference of the first segments 310. However, a single emitter short region 71 may also be sufficient.

(68) The described device structure provides a high di/dt capability due to the massively increased interface area between the gate electrodes and the main electrodes on the first and second main surfaces. Compared to conventional devices, short turn-on times after application of a gate current pulse may be obtained.

(69) In conventional devices, the distance of a short region from a main electrode edge is kept low since it is inversely proportional to the dV/dt capability. This reduces the di/dt capability. In contrast, high values for dV/dt and di/dt may be obtained at the same time for the described bypass device, for example due to the massively increased gate-cathode area.

(70) The exemplary embodiment of FIG. 6 essentially corresponds to that described in connection with FIG. 3.

(71) In departure therefrom, the arrangement of first emitter regions 61 and first emitter short regions 71 on the first main surface 21 differs from the arrangement of second emitter region 62 and second emitter short regions 72 on the second main surface.

(72) When seen onto the first main surface, at least some or all of the first emitter regions 61 overlap with one or more of the second emitter short regions 72. Using this arrangement, a length of a direct current path of the first thyristor functional element 11 and the second thyristor functional element 12 between the first main electrode 31 and the second main electrode 32 may be reduced compared to an arrangement where the first emitter regions 61 have the same size and position as the second emitter regions 62. Thus, the switchable bypass device may behave as if it had a thinner device body resulting in a lower ON state voltage drop and lower electrical losses.

(73) Furthermore, an asymmetric arrangement of the emitter regions 61, 62 and emitter short regions 71, 72 on the different main surfaces 21, 22 may be used in order to intentionally obtain different properties for different polarities.

(74) For example, different protection limits may be obtained for the different polarities. For example, different maximal surge current magnitudes may be obtained For example, one of them can fail at low surge current whereas the second one fails at high surge current. Thus, two different antiparallel functional elements may be incorporated into a single device. This may help to reduce the costs and/or to obtain a smaller footprint.

(75) The described asymmetric configuration of the switchable bypass device 1 may also be used for the exemplary embodiment of FIGS. 5A and 5B.

(76) As in the exemplary embodiments of FIG. 3 and FIGS. 5A and 5B, the switchable bypass device 1 may comprise only one gate electrode or two gate electrodes.

(77) This patent application claims the priority of European patent application EP 20209823.2, the disclosure content of which is hereby incorporated by reference.

(78) The invention described herein is not restricted by the description given with reference to the exemplary embodiments. Rather, the invention encompasses any novel feature and any combination of features, including in particular any combination of features in the claims, even if this feature or this combination is not itself explicitly indicated in the claims or exemplary embodiments.

LIST OF REFERENCE SIGNS

(79) 1 switchable bypass device 10 further bypass device 100 module 101 first switch 102 second switch 103 third switch 104 forth switch 105 energy store 108 first module connection 109 second module connection 11 first thyristor functional element 12 second thyristor functional element 2 semiconductor body 21 first main surface 22 second main surface 31 first main electrode 310 first segments 32 second main electrode 320 second segments 41 first gate electrode 411 first grid structure 4110 first cells 4111 side 42 second gate electrode 421 second grid structure 4210 second cells 51 first base layer 52 second base layer 53 third base layer 61 first emitter region 62 second emitter region 71 first emitter short region 72 second emitter short region 8 amplifying gate structure 80 section 81 first partial region 82 second partial region 91 first gate contact region 92 second gate contact region L1 length of side W1 width of side E1 maximum lateral extent of first emitter short region D1 edge-to-edge distance D2 edge-to-edge distance