Abstract
The present invention is a Class-D amplifier including: a capacitively-coupled amplifier, configured to receive an input signal and a feedback signal and generate an error signal; and a loop filter, coupled to input capacitor and the feedback capacitor, configured to generate a processed signal according to the error signal; and a pulse-width modulation (PWM) generator, coupled to the loop filter, configured to generate a plurality of PWM signals according to the processed signal and a control signal; and a voltage boosting power stage, coupled to the PWM generator, configured to generate a boosted output signal according to the plurality of PWM signals, the control signal and a power supply, and to feedback the boosted output signal to the loop filter, wherein the maximum voltage of the boosted output signal is greater than the voltage of the power supply.
Claims
1. A Class-D amplifier, comprising: a capacitively-coupled amplifier, configured to receive an input signal and a feedback signal, comprising: an input and a feedback capacitor, wherein the ratio between the input capacitor and the feedback capacitor set a closed-loop gain of the Class-D amplifier; and a preamplifier, configured to generate an error signal according to the input signal and the feedback signal; and a loop filter, coupled to the preamplifier, configured to generate a processed signal according to the error signal; a pulse-width modulation (PWM) generator, coupled to the loop filter, configured to generate a plurality of PWM signals and a control signal, wherein the PWM generator modulates the processed signal with a triangular carrier signal to generate the PWM signals, wherein the center point of the control signal aligns with the peak and valley of the triangular carrier signal; and a voltage boosting power stage, coupled to the PWM generator, configured to generate a boosted output signal according to the plurality of PWM signals, the control signal and a power supply, and to feedback the boosted output signal to the loop filter, and filters the high-frequency components in the boosted output signal, wherein the maximum voltage of the boosted output signal is greater than the voltage of the power supply, wherein the voltage boosting power stage comprises: a first transistor, comprising a first drain, a first gate and a first source; a second transistor, comprising a second drain, a second gate and a second source; a third transistor, comprising a third drain, a third gate and a third source; a fourth transistor, comprising a fourth drain, a fourth gate and a fourth source; a fifth transistor, comprising a fifth drain, a fifth gate and a fifth source; a sixth transistor, comprising a sixth drain, a sixth gate and a sixth source; an inductor; a first capacitor; and a second capacitor; wherein the first drain and the second drain are coupled to the power supply; the first source, the third drain and the fifth source are coupled to a first switching node; the second source, the fourth drain and the sixth source are coupled to a second switching node; the fifth drain is coupled to a first output node; the sixth drain is coupled to a second output node; the third source and the fourth source are coupled to ground; the inductor is connected between the first switching node and the second switching node; the capacitor is connected between the first output node and the ground; and the capacitor is connected between the second output node and the ground.
2. The Class-D amplifier of claim 1, wherein the PWM signals and the control signal are configured to control the on/off of the transistors, and providing the power to the inductor through the power supply or providing the power to a load through the inductor.
3. The Class-D amplifier of claim 2, wherein the voltage of the boosted output signal is determined by the duty cycle of providing the power to the inductor through the power supply and the duty cycle of providing the power to the load through the inductor.
4. The Class-D amplifier of claim 3, wherein the voltage of the boosted output signal is greater than the voltage of power supply within the duty cycle of providing the power to the inductor through the power supply greater than the duty cycle of providing the power to the load through the inductor.
5. The Class-D amplifier of claim 3, wherein the voltage of the boosted output signal is less than the voltage of power supply within the duty cycle of providing the power to the inductor through the power supply less than the duty cycle of providing the power to the load through the inductor.
6. The Class-D amplifier of claim 1, wherein the loop filter comprises at least one input stage amplifier for receiving the input signal and the feedback signal.
7. The Class-D amplifier of claim 1, wherein the loop filter comprises at least one integrator or at least one resonator.
8. The Class-D amplifier of claim 1, wherein the input capacitor comprises at least one capacitive digital-to-analog converter (CDAC).
9. The Class-D amplifier of claim 8, further comprising a delta-sigma modulator (DSM), choppers and a dynamic element matching (DEM) logic, wherein the DSM is used to truncate the bit number of input signal, and then chopped by the choppers, and the DEM logic drives the CDAC according to the chopped digital signal to deal with the mismatch error of CDAC.
10. The Class-D amplifier of claim 9, wherein DSM and choppers are implemented on digital signal processing (DSP).
11. The Class-D amplifier of claim 1, wherein the six transistors comprise n-channel MOSFETs.
12. The Class-D amplifier of claim 1, wherein the PWM generator includes the clock generator, two comparators, the control logic and the gate driver.
13. The Class-D amplifier of claim 1, wherein the capacitively-coupled amplifier further includes multiple choppers, including an input chopper and the feedback chopper inserted in the input path and feedback path, respectively, and including choppers in the preamplifier.
14. The Class-D amplifier of claim 1, further including sampling-and-reset switches connected to the output of the preamplifier.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] FIG. 1 (prior art) is a block diagram of a closed-loop Class-D amplifier with resistive feedback according to the prior art.
[0011] FIG. 2 (prior art) is a schematic diagram of a full-bridge power stage of a Class-D amplifier according to the prior art.
[0012] FIG. 3 (prior art) shows waveforms of the PWM signals generated by a PWM generator according to the prior art.
[0013] FIG. 4 is a block diagram of a closed-loop Class-D amplifier with capacitive feedback and voltage boosting power stage according to an example of the present invention.
[0014] FIG. 5 is a schematic diagram of a full-bridge voltage boosting power stage of a Class-D amplifier according to an example of the present invention.
[0015] FIG. 6 shows waveforms of the PWM signals and the control signal generated by a PWM generator according to an example of the present invention.
[0016] FIG. 7 is a detailed circuit diagram of a closed-loop analog-input Class-D amplifier with capacitive feedback and voltage boosting power stage in FIG. 4 according to an example of the present invention.
[0017] FIG. 8 is a detailed circuit diagram of a closed-loop digital-input Class-D amplifier with capacitive feedback and voltage boosting power stage in FIG. 4 according to an example of the present invention.
[0018] FIG. 9 is present invention compare to the typical Class-D amplifiers.
DESCRIPTION OF THE PREFERRED EMBODIMENT
[0019] FIG. 4 is a block diagram of a closed-loop Class-D amplifier with capacitive feedback and voltage boosting power stage according to an example of the present invention. The closed-loop Class-D amplifier with capacitive feedback and voltage boosting power stage includes an input capacitor 21, a feedback capacitor 22, a preamplifier 23, a loop filter 24, a PWM generator 25, a voltage boosting power stage 26 and a speaker load 27. The input capacitor 21, the feedback capacitor 22 and the preamplifier 23 together constitute a capacitively-coupled amplifier. The ratio between the input capacitor 21 and the feedback capacitor 22 set a closed-loop gain of the Class-D amplifier. The preamplifier 23 is configured to generate an error signal according to the input signal and feedback signal, wherein the input signal may be an audio signal. The loop filter 24 comprises at least one integrator or at least one resonator. The loop filter 24 is configured to generate a processed signal according to the error signal. The PWM generator 25 generates PWM signals and a control signal according to the processed signal. The voltage boosting power stage 26 generates a boosted output signal according to the PWM signals the control signal and the power supply and VBAT, filters the high-frequency components in the boosted output signal, wherein the boosted output signal may be greater than the power supply VBAT. Then, the boosted output signal drives the speaker load 27. The power supply VBAT may be a phone battery or an automotive battery. The voltage boosting power stage 26 requires additional transistors and LC components to implement the boost function, and the LC components can also act as a low-pass LC filter, thereby reducing EMI. Moreover, the one-step power conversion from the power supply VBAT to the speaker load 27 through the voltage boosting power stage 26 will be more power efficient compare to the prior art. The input capacitor 21 and feedback capacitor 22 don't contribute thermal noise, achieving high SNR. However, due to the rapid switching activities, the high-frequency components in the boosted output signal may directly couple through the feedback capacitor 22 to the input stage amplifier in the loop filter 24, causing slewing and degrading the linearity of the Class-D amplifier. Nevertheless, by virtue of LC filtering in voltage boosting power stage 26, the high-frequency components in boosted output signal can be suppressed.
[0020] FIG. 5 is a schematic diagram of a full-bridge voltage boosting power stage of a Class-D amplifier according to an example of the present invention. The voltage boosting power stage 26 (e.g., the voltage boosting power stage in FIG. 4) may be the full-bridge voltage boosting power stage 26. The full-bridge voltage boosting power stage 26 includes transistors M.sub.1, M.sub.2, M.sub.3, M.sub.4, M.sub.5 and M.sub.6, an inductor 261 and two capacitors 262, 263. Each of the transistors M.sub.1, M.sub.2, M.sub.3, M.sub.4, M.sub.5 and M.sub.6 may be an n-channel MOSFET. The power supply V.sub.BAT directly supplies the full-bridge voltage boosting power stage 26. The PWM signals and a control signal generated by a PWM generator (e.g., the PWM generator 25 in FIG. 4) are used to control the on/off of the transistors M.sub.1, M.sub.2, M.sub.3, M.sub.4, M.sub.5 and M.sub.6, and providing the power to the inductor through the power supply or providing the power to a load through the inductor. The transistors M.sub.1, M.sub.2, M.sub.3, M.sub.4, M.sub.5 and Me each comprise a drain, a gate and a source. The drain of transistor M.sub.1 is coupled to the power supply V.sub.BAT and its source is coupled to a switching node LXA. The drain of transistor M.sub.2 is coupled to the power supply V.sub.BAT and its source is coupled to a switching node LXB. The drain of transistor M.sub.3 is coupled to the switching node LXA and its source is coupled to the ground. The drain of transistor M.sub.4 is coupled to the switching node LXB and its source is coupled to the ground. The drain of transistor M.sub.5 is coupled to an output node V.sub.OUTA and its source is coupled to the node LXA. The drain of transistor M.sub.6 is coupled to an output node V.sub.OUTB and its source is coupled to the node LXB. An inductor 261 is connected between the switching node LXA and the switching node LXB. A capacitor 262 is connected between the output node V.sub.OUTA and the ground. A capacitor 263 is connected between the output node V.sub.OUTB and the ground. The output nodes V.sub.OUTA and V.sub.OUTB are coupled to the speaker load 27 for outputting the boosted signal (e.g., the speaker load 27 in FIG. 4). Compared to the full bridge power stage of a Class-D amplifier according to the prior art as shown in FIG. 2, the present invention only needs two additional transistors, one inductor 261 and two capacitors 262, 263 to boost the output signal while filtering the high-frequency components caused by the rapid switching activities. Thus, it can achieve high output power and low EMI at low cost.
[0021] FIG. 6 shows waveforms of the PWM signals and the control signal ENDE generated by a PWM generator according to an example of the present invention. In the PWM generator, the processed signals V.sub.LF+ and V.sub.LF are modulated with a triangular carrier signal V.sub.TRI to generate the PWM signals PWMA and PWMB, as well as the control signal EN.sub.DE, wherein the processed signals V.sub.LF+ and V.sub.LF are generated by the loop filter (e.g., the loop filter 24 in FIG. 4). These PWM signals PWMA and PWMB and the control signal EN.sub.DE can then be used to control the transistors M.sub.1, M.sub.2, M.sub.3, M.sub.4, M.sub.5 and M.sub.6 in the full-bridge voltage boosting power stage (e.g., the full-bridge voltage boosting power stage 26 in FIG. 5). As shown in FIG. 6, the term 1 refers to logic high and the term O refers to logic low. The full bridge voltage boosting power stage of the Class-D amplifier according to an example of the present invention operates in the following five phases: 1) When PWMA=1, PWMB=1 and EN.sub.DE=0, M.sub.1 and M.sub.2 turn ON, M.sub.3, M.sub.4, M.sub.5 and M.sub.6 turn OFF, the inductor current flows through a free-wheeling path formed by the inductor and the power supply V.sub.BAT. 2) When PWMA=1, PWMB=0 and EN.sub.DE=0, M.sub.1 and M.sub.4 turn ON, M.sub.2, M.sub.3, M.sub.5 and M.sub.6 turn OFF, the inductor is energized by the power supply V.sub.BAT and the inductor current flows from the left to the right. 3) When PWMA=0, PWMB=1, EN.sub.DE=0, M.sub.2 and M.sub.3 turn ON, M.sub.1, M.sub.4, M.sub.5 and Me turn OFF, the inductor is energized by the power supply V.sub.BAT and the inductor current flows from the right to the left. 4) When PWMA=0, PWMB=0, EN.sub.DE=0, M.sub.3 and M.sub.4 turn ON, M.sub.1, M.sub.2, M.sub.5 and M.sub.6 turn OFF, and the inductor current flows through a free-wheeling path formed by the inductor and the ground. 5) When EN.sub.DE=1, M.sub.5 and M.sub.6 turn ON, M.sub.1, M.sub.2, M.sub.5 and Me turn OFF, the inductor is de-energized to the speaker load and the capacitors. This five-state operation is called voltage-boosting BD (VBBD) double-sided modulation according to an example of the present invention.
[0022] In the BD double-side modulation according to the prior art, the power is delivered to the speaker load directly through the supply voltage PVDD (i.e., PWMA=0, PWMB=1 or PWMA=1, PWMB=0 in FIG. 3); however, in the VBBD double-side modulation according to an example of the present invention, the power is first delivered to the inductor through the power supply V.sub.BAT (i. e., PWMA=0, PWMB=1, EN.sub.DE=0 or PWMA=1, PWMB=0, EN.sub.DE=0 in FIG. 6), and then an additional state for power delivering to the speaker load through the inductor (i.e., EN.sub.DE=1 in FIG. 6). Based on the principle of voltage-second balance on the inductor, the voltage of the boosted output signal is determined by the duty cycle of the power delivery from the power supply V.sub.BAT to the inductor and the duty cycle of the power delivery from the inductor to the speaker load, wherein the voltage of the boosted output signal is greater than the voltage of power supply within the duty cycle of providing the power to the inductor through the power supply greater than the duty cycle of providing the power to the load through the inductor; alternatively, the voltage of the boosted output signal is less than the voltage of power supply within the duty cycle of providing the power to the inductor through the power supply less than the duty cycle of providing the power to the load through the inductor. In addition, due to the double-sided modulation, the effective switching frequency of the Class-D amplifier is doubled, thus reducing the ripple current on the inductor by half to lower ripple current loss. Also, the center point of the control signal EN.sub.DE is designed to align with the peak and valley of the triangular carrier signal V.sub.TRI, so there are no transistors switch at the peak and valley of the triangular carrier signal V.sub.TRI, and the chopping technique can also be adopted to chop the PWM signals PMWA and PWMB at the peak and valley of the triangular carrier signal V.sub.TRI without any sampling of PWM transients.
[0023] FIG. 7 is a detailed circuit diagram of a closed-loop analog-input Class-D amplifier with capacitive feedback and voltage boosting power stage in FIG. 4 according to an example of the present invention. The closed-loop analog-input Class-D amplifier with capacitive feedback and voltage boosting power stage includes a capacitively-coupled chopper amplifier 31, sampling-and-reset switches 32, second-order active-RC integrators 33, a clock generator 34, two comparators 35, a control logic 36, a gate driver 37, a voltage boosting power stage 26 and a speaker load 27. The capacitively-coupled chopper amplifier 31 consists of input capacitors 21, feedback capacitors 22, choppers 311, 312, 313, 314 and a preamplifier 23 (e.g., the preamplifier 23 in FIG. 4). The loop filter 24 (e.g., the loop filter 24 in FIG. 4) may include the second-order active-RC integrators 33. The PWM generator 25 (e.g., the PWM generator 25 in FIG. 4) may include the clock generator 34, two comparators 35, the control logic 36 and the gate driver 37. The ratio between the input capacitor 21 and the feedback capacitor 22 set a closed-loop gain of the Class D amplifier. The input chopper 311 and the feedback chopper 313 are inserted in the input path and feedback path, respectively, to mitigate the mismatch effect of the input capacitor 21 and the feedback capacitor 22, increasing the power supply rejection ratio (PSRR) of the closed-loop Class-D amplifier, wherein the chopper 311, 313 may be optional in some applications. The preamplifier 23 acts as a gain stage to suppress the noise contribution of the second-order active-RC integrators 33, and the preamplifier 23 also further includes choppers 312, 314 to mitigate the amplifier's flicker noise, wherein the choppers 312, 314 in preamplifier may be optional in some applications. The sampling-and-reset switches 32 are reset to the V.sub.CM during the chopping transitions to block the chopping glitches; otherwise, they are both connected to the output of the preamplifier 23, wherein the sampling-and-reset switches 32 may be optional in some applications. The second-order active-RC integrators 33 suppress the power stage non-ideal effects to achieve low THD. The clock generator 34 generates the triangular carrier signal and the control signal EN.sub.DE, wherein the center point of the control signal EN.sub.DE is designed to align with the peak and valley of the triangular carrier signal V.sub.TRI. In addition, the chopping transitions can be aligned with the peak and valley of V.sub.TRI to avoid sampling the signal-dependent transitions in V.sub.OUTA and V.sub.OUTB due to transistors switching in the power stage. The comparators 35 modulate the processed signals V.sub.LF+, V.sub.LF with the triangular carrier signal V.sub.TRI to generate the PWM signals PMWA and PWMB. The control logic 36 and the gate driver 37 control the operation of the voltage boosting power stage 26. The voltage boosting power stage 26 comprises six transistors (M.sub.1, M.sub.2, M.sub.3, M.sub.4, M.sub.5 and M.sub.6), one inductor 261, and two capacitors 262, 263, generating the boosted output signal to drive the speaker load 27, wherein the high-frequency components in boosted output signal can be suppressed by LC filtering, thus reducing EMI.
[0024] FIG. 8 is a detailed circuit diagram of a closed-loop digital-input Class-D amplifier with capacitive feedback and voltage boosting power stage in FIG. 4 according to an example of the present invention. Compare to the example of FIG. 7, the input capacitor 21 is replaced b y capacitive digital-to-analog converter (CDAC) 41. The input signal may be a digital-format audio signal. A delta-sigma modulator (DSM) 42 is used to truncate the bit number of input signal while maintaining signal quality, and then chopped by the choppers 43, wherein DSM 42 and choppers 43 are implemented on digital signal processing (DSP). A dynamic element matching (DEM) logic 44 drives the CDAC 41 according to the chopped digital signal to deal with the mismatch error of CDAC. The descriptions of rest of the circuits are similar to the example of FIG. 7.
[0025] In the present invention provides a low-EMI capacitively-coupled Class-D amplifiers with voltage boosting. Low THD is achieved by the closed-loop architecture with capacitive feedback, and the high SNR is also achieved thanks to no thermal noise contribution of the capacitor. The voltage boosting power stage generates the boosted output signal with LC filtering, thereby increasing the maximum output power and reducing EMI. Moreover, compare to the typical Class-D amplifiers shown in FIG. 9, the present invention neither needs to boost LC components of a converter nor needs an LC filter but only requires one inductor and two capacitors, which greatly reduce the system cost and bulk.
[0026] Furthermore, according to the present invention, power supply V.sub.BAT directly supplies power to the voltage boosting power stage such that one-step power conversion from power supply V.sub.BAT to a speaker load saves more power than the prior art (as shown in FIG. 2, two-step power conversion from power supply V.sub.BAT to a speaker load through a boost converter and a power stage reduces overall power efficiency.) To sum up, the present invention achieves low THD, high SNR, high output power and low EMI simultaneously.
[0027] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
