SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD

Abstract

In one embodiment, the semiconductor device (1) comprises a semiconductor body (2), a gate electrode (33) and a first electrode (31), whereinthe semiconductor body (2) comprises a first region (21) which is a source region or an emitter region, and comprises a well region (22) located next to the first region (21), the first region (21) is of a first conductivity type and the well region (22) is of a second conductivity type, the well region (22) is separated from the gate electrode (33) by a gate insulator layer (4), the first region (21) is electrically contacted by means of the first electrode (31), in the first region (21) there is at least one current limiting region (5), andthe at least one current limiting region (5) is a sub-region of the first region (21) with a decreased electrical conductivity.

Claims

1. A semiconductor device comprising a semiconductor body, a gate electrode and a first electrode, wherein the semiconductor body comprises a first region which is a source region or an emitter region, and comprises a well region located next to the first region, the first region is of a first conductivity type and the well region is of a different, second conductivity type, the well region is adjacent to the gate electrode and is separated from the gate electrode by a gate insulator layer, the first region is electrically contacted by means of the first electrode which is a source electrode or an emitter electrode, in the first region there is at least one current limiting region, the at least one current limiting region is a sub-region of the first region with a decreased electrical conductivity, and the semiconductor device is of planar design so that the gate insulation layer and the gate electrode are applied on a planar section of a top side of the semiconductor body, the first region is located at the top side, and wherein either, seen in cross-section of the semiconductor body through the first region and through the gate electrode, the first region extends all around the at least one current limiting region in directions towards the well region so that the first region is embedded in the well region and so that the at least one current limiting region is embedded in the first region, or the at least one current limiting region is completely embedded in the first region so that, seen in cross-section of the semiconductor body, the first region is all around the at least one current limiting region.

2. The semiconductor device according to claim 1, wherein, seen in top view of the semiconductor body, the gate electrode as well as the first electrode overlap with the first region, and the at least one current limiting region is distant from the gate electrode as well as from the first electrode.

3. The semiconductor device according to claim 1, wherein, seen in top view of the semiconductor body, the first region completely extends between the at least one current limiting region and the first electrode as well as between the at least one current limiting region and the gate electrode, the at least one current limiting region is located between the first electrode and the gate electrode.

4. The semiconductor device according to claim 1, wherein the at least one current limiting region is completely embedded in the first region so that, seen in cross-section of the semiconductor body, the first region is all around the at least one current limiting region.

5. The semiconductor device according to claim 1, wherein a volume of the at least one current limiting region is at least 10% and at most 95% of an overall volume of the first region.

6. The semiconductor device according to claim 1, wherein an electrical conductivity of the at least one current limiting region is between 5% and 90% of an electrical conductivity of remaining regions of the first region, wherein a crystal lattice in the at least one current limiting region has by at least a factor of two more defects than the remaining regions of the first region.

7. The semiconductor device according to claim 1, wherein the semiconductor body further comprises a drift region which is of the first conductivity type and also comprises a second region which is a drain region or a collector region, wherein the drift region is located between the well region and the second region, wherein the semiconductor device further comprises a second electrode which is a collector electrode or a drain electrode, the second electrode is located on a side of the second region remote from the drift region, and wherein the semiconductor body is of SiC.

8. The semiconductor device according to claim 1, wherein, seen in top view of the semiconductor body, the gate electrode and the first electrode each extend along a straight line, the first region extends in parallel with the gate electrode and the first electrode, or wherein, seen in top view of the semiconductor body, the gate electrode and the first electrode each comprise a plurality of sub-sections arranged along at least one arrangement line, the first region extends between adjacent sub-sections of the gate electrode and the first electrode.

9. The semiconductor device according to claim 1, wherein there is the exactly one current limiting region in the first region.

10. The semiconductor device according to claim 1, wherein there is a plurality of the current limiting regions in the first region, the current limiting regions are distant from one another, seen in top view of the semiconductor body.

11. A manufacturing method for a semiconductor device according to claim 1, the method comprises: providing the semiconductor body, forming the first region and the well region in the semiconductor body, applying a mask layer on the semiconductor body, irradiation at least one portion of the first region defined by the mask layer with at least one of x-ray, electrons, protons, neutrons or ions so that the at least one current limiting region is created in the at least one irradiated portion, and applying the gate insulator layer as well as the gate electrode and the first electrode to the semiconductor body.

12. (canceled)

13. (canceled)

14. (canceled)

Description

[0070] In the figures:

[0071] FIG. 1 is a schematic perspective sectional view of an exemplary embodiment of a semiconductor device described herein,

[0072] FIGS. 2 to 4 are schematic sectional views of exemplary embodiments of semiconductor devices described herein,

[0073] FIGS. 5 and 6 are schematic perspective sectional views of exemplary embodiments of semiconductor devices described herein,

[0074] FIGS. 7 to 9 are schematic sectional views of exemplary embodiments of semiconductor devices described herein,

[0075] FIGS. 10 and 11 are schematic diagrams of electric characteristics of simulations of an exemplary embodiment of a semiconductor device described herein, compared with corresponding semiconductor device free of the at least one current limiting region,

[0076] FIG. 12 is a schematic block diagram of an exemplary embodiment of a method for manufacturing semiconductor devices described herein,

[0077] FIG. 13 is a schematic sectional view of a method step of an exemplary embodiment of a method described herein, and

[0078] FIGS. 14 and 15 are schematic top views of exemplary embodiments of semiconductor devices described herein.

[0079] FIG. 1 illustrate an exemplary embodiment of a semiconductor device 1. The semiconductor device 1 comprises a semiconductor body 2 which is, for example, of SiC. In the semiconductor body 2, there is a first region 21, a well region 22 and a drift region 23. Further, there is a plug region 25 for electrically contacting the well region 22.

[0080] Further, the semiconductor device 1 comprises a gate electrode 33 which is separated from the semiconductor body 2 by means of a gate insulator layer 4. Further, there is a first electrode 31 which electrically contacts the first region 21 and the plug region 25. The gate insulator layer 4 and the first electrode 31 are located at a top side 20 of the semiconductor body 2. The top side 20 is of planar fashion. The gate electrode 33 and the first electrode 31 may each extend along a straight line along a direction perpendicular to the cross-section illustrated in FIG. 1.

[0081] The gate insulator layer 4 may be of a metal oxide, a semiconductor oxide, a metal nitride and/or a semiconductor nitride. For example, the a gate insulator layer 4 includes one or a plurality of the following materials: SiO.sub.2, Si.sub.3N.sub.4, Al.sub.2O.sub.3, Y.sub.2O.sub.3, ZrO.sub.2, HfO.sub.2, La.sub.2O.sub.3, Ta.sub.2O.sub.5, TiO.sub.2.

[0082] For example, the first region 21 and the drift region 23 are n-doped and the well region 22 and the plug region 25 are p-doped. If the semiconductor device 1 is an insulated-gate bipolar transistor, IGBT or a reverse-conducting insulated-gate bipolar transistor, RC-IGBT, then the first region 21 is an emitter region and the first electrode 31 is an emitter electrode. If the semiconductor device 1 is a junction gate field-effect transistor, JFET, a metal-insulator-semiconductor field-effect transistor, MISFET, or a metal-oxide-semiconductor field-effect transistor, MOSFET, then the first region 21 is a source region and the first electrode 31 is a source electrode.

[0083] In the first region 21, there is a current limiting region 5. The current limiting region 5 is of the same material as the rest of the first region, for example, of SiC. However, due to irradiating the part of the first region 21 that constitutes the current limiting region 5, in the current limiting region 5 the electrical conductivity is decreased, compared with the rest of the first region 21.

[0084] Thus, FIG. 1 depicts the basic concept of the proposed semiconductor device 1. A region, that is, the at least one current limiting region 5, is irradiated after source activation. Its width is defined by a mask design, while the depth of this region 5 depends on a mask thickness and the energy used for irradiation. During irradiation, for example, several point defects are formed. These defects can form electrically active levels in the band gap, like EH1, Z1/2, EH3, EH4, EH5 and EH6/7, compare G. Alfieri et al., Annealing behavior between room temperature and 2000 C. of deep level defects in electron-irradiated n-type 4H silicon carbide, Journal of Applied Physics 98, 043518 (2005), doi: 10.1063/1.2009816, and Alfieri et al., Isothermal Annealing Study of the EH1 and EH3 Levels in n-type 4H-SiC, J. Phys.: Condens. Matter 32, 46573 (2020), doi: 10.1088/1361-648X/abaeaf. These levels trap charge carriers and decrease the mobility. The lower mobility increases the value of the source resistance R.sub.S.

[0085] The current limiting region 5 runs along a straight line in parallel with the gate electrode 33 and the first electrode 31. The current limiting region 5 is located directly at the top side 20, like the first region 21. A depth of the first region 21 into the semiconductor body 2 exceeds a depth of the current limiting region 5 into the semiconductor body 2, starting from the top side 20. Towards the well region 22 in which the first region 21 is embedded, all around the current limiting region 5 there is the first region 21, seen in cross-section.

[0086] For example, the at least one current limiting region 5 is arranged mirror symmetrically in the first region 21, seen in top view as well as seen in cross-section. For example, seen in top view of the top side 20, the current limiting region 5 is arranged symmetrically in the first region 21 and between the electrodes 31, 33. Hence, there can be a line M of mirror symmetry concerning the current limiting region 5 and the first region 21.

[0087] The at least one current limiting region 5 can have different shapes and depths and can be uniform or also non-uniform along the direction perpendicular to the cross-section of FIG. 1, see also FIGS. 2 to 9 below.

[0088] With the proposed at least one current limiting region 5, the current flows in a more resistive and/or constricted path. This effect leads to an increased value of the source resistance R.sub.S or correspondingly of an emitter resistance. Increasing the value of R.sub.S will turn into a reduction of the saturation current I.sub.SAT, during a short circuit condition. A depth d of the current limiting region 5 and its length L in parallel with the top side 20 and along the cross-section of FIG. 1 could be properly designed to achieve the desired effect on the short circuit current, while keeping negligible its impact during conduction in nominal conditions, for example, on the total R.sub.DS,on.

[0089] For example, the carriers' effective channel-to-contact path length Leff is a minimum of a local resistance r along all possible routes S with incremental elements s within the first region 21, including the at least one current limiting region 5, L.sub.eff=min .sub.s rds.

[0090] The semiconductor device 1 of FIG. 1 is of a planar design. Contrary to that, the semiconductor device 1 of FIG. 2 is of a trench design. Thus, the gate electrode 33 and the gate insulator layer 4 are at least partially located in a trench into the semiconductor body 2. Accordingly, the top side 20 is not of planar fashion as it is penetrated by said trench, contrary to what is the case in FIG. 1. The gate electrode 33 reaches deeper into the semiconductor body 2 than the well region 22, for example, starting from the top side 20.

[0091] Further, in FIG. 2 it is shown that there are multiple first regions 21 and, thus, current limiting regions 5, arranged, for example, symmetrically with respect to the gate electrode 33. There can be a plurality of the units illustrated in FIG. 2 next to one another along a direction in parallel with the top side 20 so that there can be a plurality of stipes of the gate electrode 33 as well as of the first electrode 31 running perpendicular to the plane of projection of FIG. 2 and running in parallel with each other.

[0092] This symmetric arrangement of FIG. 2, see also FIG. 14, and/or the trench design of FIG. 2 can be applied analogously to all other embodiments, too.

[0093] The current limiting regions 5, one per first region 21, of FIG. 2 are of the same design as in FIG. 1, that is, of a trough with cuboid shape. According to FIG. 2, the trough has sharp edges and corners; according to FIG. 1, the trough has rounded edges and corners. Both designs are possible in all embodiments, depending on the manufacturing process of the at least one current limiting region 5.

[0094] Moreover, in FIG. 2 it is shown that there is a second electrode 32, and the semiconductor body 2 comprises a second region 24. For example, the second region 24 is a substrate on which the other regions 23, 22, 21, 25 are formed by means of growth and/or doping, like ion implantation. In case of an IGBT or RC-IGBT, the second electrode 32 is a collector electrode, and the second region is a collector region which is of the same doping type as the well region. In case of a MOSFET or MISFET, the second electrode 32 is a drain electrode, and the second region is a drain region which is of the same doping type as the first region. The same applies for all other embodiments of the semiconductor device 1.

[0095] Further, according to FIG. 2 the plug region 25 reaches deeper into the semiconductor body 2, starting from the top side 20, than the first region 21. Otherwise, see FIG. 1, the plug region 25 can have the same depth as the first region 21 or can also be shallower or deeper than the first region 21. Both possibilities can apply in all the embodiments.

[0096] As in FIG. 1, also in FIG. 2 the at least one current limiting region 5 per first region 21 is distant from the first electrode 31, from the gate electrode 33 and from the gate insulator layer 4.

[0097] For example, maximum doping concentrations of the first region 21, the second region 24 and the at least one plug region 25 are at least 110.sup.18 cm.sup.3 or are at least 510.sup.18 cm.sup.3 or at least 110.sup.19 cm.sup.3 and/or at most 510.sup.20 cm.sup.3 or at most 210.sup.20 cm.sup.3 or at most 110.sup.20 cm.sup.3. Further, a maximum doping concentration of the well region 22 and, thus, of a channel region next to the gate insulator layer 4 may be at least 510.sup.16 cm.sup.3 or at least 110.sup.17 cm.sup.3 and/or at most 510.sup.19 cm.sup.3 or at most 510.sup.18 cm.sup.3. Depending on the voltage class of the semiconductor device 1, a maximum doping concentration of the drift region 23 may be at least 110.sup.11 cm.sup.3 or at least 110.sup.12 cm.sup.3 or at least 110.sup.13 cm.sup.3 and/or at most 110.sup.17 cm.sup.3 or at most 510.sup.16 cm.sup.3 or at most 110.sup.16 cm.sup.3. For example, a thickness of the gate insulator layer 4 is between 10 nm and 250 nm or between 80 nm and 150 nm. These parameters may individually or collectively apply for all other embodiments, too.

[0098] Otherwise, the same as to FIG. 1 may also apply to FIG. 2, and vice versa.

[0099] In FIGS. 3 and 4, like in FIG. 1, there is one current limiting region 5 per first region 21. The current limiting region 5 can be arranged mirror symmetrically in the first region 25, the axis of mirror symmetry runs perpendicular to the top side 20.

[0100] Contrary to what is shown in FIG. 1, according to FIGS. 3 and 4 the current limiting region 5 extends beyond the gate insulator layer 4 as well as the gate electrode 33. Such an arrangement is possible in all other embodiments, too. Otherwise, contrary to what is shown in FIGS. 3 and 4, the current limiting region 5 may be located non-mirror symmetrically in the first region 21 so that the current limiting region 5 ends distant from the gate insulator layer 4 and, thus, may not run beyond the gate electrode 33. This is possible as well in all other embodiments.

[0101] According to FIG. 3, the current limiting region 5 is formed as a shallow trough in the first region 21 which is also formed as one trough. The depth d of the current limiting region 5 amounts, for example, between 10% and 90% or between 40% and 80% of a depth D of the first region 21. The first region 21 and the plug region 25 may be of the same depth, for example, within manufacturing tolerances. For example, the depth D of the first region 21 is at least 0.1 m and/or is at most 2 m.

[0102] According to FIG. 4, the current limiting region 5 is formed as a deep trough in the first region 21 which is formed as two troughs, one above the other, wherein the trough next to the top side 20 has a larger extent in parallel with the plane of projection of FIG. 4. In this case, too, the depth d of the current limiting region 5 can amount between 10% and 90% or between 40% and 80% of the depth D of the overall first region 21. Because of the design with two stacked troughs, the first region 21 can run deeper into the semiconductor body 2 than the plug region 25. It is possible that the plug region 25 is of the same depth as the trough of the first region 21 next to the top side 20, for example, within manufacturing tolerances. For example, the depth D of the first region 21 is at least 2 m and/or is at most 4 m.

[0103] For example, first the trough next to the top side 20 is formed by corresponding doping, and then the doping for the trough remote from the top side 20 is provided, for example, by using a different energy in an ion implantation step. Hence, the trough of FIG. 4 has a step-like design, seen in cross-section. Otherwise, a deep trough with the rectangular shape with rounded corners, for example, as depicted in FIG. 3, is likewise possible in the configuration of FIG. 4.

[0104] Both designs with a shallow or a deep first region 21 as shown in FIGS. 3 and 4 are possible in all other embodiments, too.

[0105] For example, the length L of the current limiting region 5 is between 10% and 90% or between 40% and 80% or between 50% and 70% of a width B of the first region 21. This is possible as well in all other embodiments.

[0106] Otherwise, the same as to FIGS. 1 and 2 may also apply to FIGS. 3 and 4, and vice versa.

[0107] According to FIGS. 5 to 7, there are multiple current limiting regions 5 per first region 21. Concerning the parameters d, D, B, L as stated above for the case of a single current limiting region 5 per first region 21, the same applies for the case for multiple current limiting regions 5 per first region 21, wherein L corresponds to an overall width of all the respective current limiting regions 5, compare, for example, FIG. 6. By means of the plurality of current limiting regions 5, there are more design parameters to achieve an optimized first region.

[0108] In case of one current limiting region 5 in the direction perpendicular to the gate electrode 33 and/or the first electrode 31, see FIG. 5, the overall width L is the same as a width W of an individual, insular current limiting region 5 as illustrated in FIG. 4.

[0109] However, according to FIG. 5 there is one stripe of current limiting regions 5 extending in parallel with the electrodes 31, 33. Seen in top view, the current limiting regions 5 are of rectangular or square shape, optionally with rounded corners, each having the width W and a length extent V. For example, V is between 0.5 L and 100 L or is between 0.5 L and 10 L or is between 0.7 L and 5 L.

[0110] For example, a distance Zs between adjacent current limiting regions 5 along the stripe is between 10% and 75% or between 10% and 40% of the width W and/or of the length extent V. The individual current limiting regions 5 in the stripe can be arranged in an equidistant manner or, other than shown in FIG. 5, with varying distances to one another. These aspects may also apply for all other embodiments, individually or collectively.

[0111] Other than shown, the current limiting regions 5 need not be of square shape, seen in top view, but can also be of rectangular, hexagonal, regular or irregular polygonal or circular shape, seen in top view. The same applies for all other embodiments.

[0112] According to FIGS. 5 to 7, all the current limiting regions 5 per first region 21 are of the same shape. This is not absolutely necessary. That is, differently shaped current limiting regions 5 may be combined within one first region 21.

[0113] There can be N stripes of the current limiting regions 5 between the electrodes 31, 33, where N is a natural number larger than or equal to two. For example, N is at most ten or is at most four. According to the example of FIG. 6, N is two. For example, it applies that 0.1 B/NW0.99 B/N or 0.4 B/NW0.95 B/N or 0.7 B/NW0.90 B/N. Alternatively, or additionally, for example, a distance Zt between adjacent current limiting regions 5 in a traverse direction perpendicular to the stripes is between 10% and 75% or between 10% and 40% of the length extent V. Alternatively, or additionally, for example, it applies that 0.1 B/NV100 B/N or 0.4 B/NV10 B/N or 0.7 B/NV5 B/N. The current limiting regions 5 can be arranged in an equidistant manner in parallel as well as perpendicular to the electrodes 31, 33.

[0114] As shown in FIG. 6, all the N stripes have the same number of current limiting regions 5 so that there are in each case K current limiting regions 5 next to one another in a direction in parallel with the stripes. Consequently, a regular array of NK current limiting regions 5 is formed, and all the current limiting regions 5 are of the same shape.

[0115] However, this is not necessary. That is, current limiting regions 5 of different shapes and sizes can be combined with each other, and there can be different numbers K of current limiting regions 5 per stripe and/or different numbers N of current limiting regions 5 in the direction in parallel with the width L. For example, there are current limiting regions 5 of different widths W so that there may be rows in parallel with the direction along the width L having a single broad current limiting region 5 and alternating with rows having a plurality of narrower current limiting regions 5, by way of example.

[0116] In FIG. 7 it is illustrated that N is three. As an option, the stripe most distant from the first electrode 31 reaches beyond the gate insulator layer 4. However, other than shown in FIG. 7, all the stripes can be distant from the gate electrode 33, for example, seen in top view of the top side 20.

[0117] Each one of the stripes of FIG. 7 can be composed of multiple current limiting regions 5, as in FIGS. 5 and 6, or there is only a single current limiting region 5 per stripe, as in FIGS. 1 to 4. The same applies for all other embodiments.

[0118] The current limiting regions 5 of FIGS. 5 to 7 are of shallow design, compare, for example, FIG. 3 above. It is also possible that all or some of the current limiting regions 5 per first region 21 are of the deep design as depicted in context with FIG. 4.

[0119] Otherwise, the same as to FIGS. 1 to 4 may also apply to FIGS. 5 to 7, and vice versa.

[0120] In the semiconductor device 1 of FIG. 8 the current limiting region 5 completely runs through the first region 21 from the top side 20 to the well region 22. Hence, all current from the first electrode 31 to the channel region of the well region 22 next to the gate insulator layer 4 has to flow through the current limiting region 5 of lower electric conductivity, disregarding possible minor currents around the current limiting region 5 through the part of the well region 22 on a side of the current limiting region 5 remote from the top side 20.

[0121] By means of the length in parallel with the plane of projection of FIG. 8 and by means of the electrical conductivity of the current limiting region 5, the resistance of the first region 21 can particularly precisely be adjusted.

[0122] Otherwise, the same as to FIGS. 1 to 7 may also apply to FIG. 8, and vice versa.

[0123] In the semiconductor device 1 of FIG. 9, the current limiting region 5 is completely embedded in the rest of the first region 21. That is, the first region 21 is all around the current limiting region 5. Accordingly, it is possible that the current limiting region 5 extends beyond the gate electrode 33. Other than shown, the current limiting region 5 may not extend below the gate electrode 33.

[0124] For example, a layer thickness of the first region 21 all around the current limiting region 5 has a thickness of at least 5% or of at least 10% and/or of at most 30% or of at most 45% of an overall thickness of the first region 21 together with the embedded current limiting region 5.

[0125] The design of FIG. 9 is also possible with a plurality of the current limiting regions 5 per first region 21, compare, for example, FIGS. 5 to 7, or also with a deep current limiting region 5, compare, for example, FIG. 4.

[0126] Otherwise, the same as to FIGS. 1 to 8 may also apply to FIG. 9, and vice versa.

[0127] FIGS. 10 and 11 show a simulated isothermal output J.sub.D vs. V.sub.DS at a gate-source voltage V.sub.GS=15 V and at a temperature of 300 K, and the electrothermal short-circuit waveforms at a drain-source voltage V.sub.DS=600 V and at V.sub.GS,Swing=5 V/+15V for the semiconductor device 1 of FIG. 8, compared to a corresponding reference MOSFET design 9 without any current limiting region. In the semiconductor device 1 corresponding to FIG. 8, the quotient d/D of the depth d of the current limiting region 5 and the depth D of the first region 21 is 1. The quotient L/B of the length L of the current limiting region 5 and the width B of the first region 21 is 0.5.

[0128] It can be noted that the achieved reduction of a maximum saturation current I.sub.SAT,peak during short-circuit is larger than the increase of the resistance in the on-state, R.sub.DS,on. Since the energy the device is subjected to during short circuit is directly related to the maximum value of I.sub.SAT, the semiconductor devices 1 described herein improve the short-circuit withstanding time without significantly affecting the conduction losses.

[0129] In FIG. 12, a method for producing the semiconductor devices 1 is illustrated. In a method step S1, the semiconductor body 2 is provided. For example, the semiconductor body 2 provides the drift region 23. Then, in a method step S2, the first region 21 and the well region 22 are formed in the semiconductor body 2 as well as the plug region 25.

[0130] Next, in step S3 at least one mask layer is provided on the top side 20 of the semiconductor body 2. Further, see step S4, at least one portion of the first region 21 defined by the mask layer is irradiated with at least one of x-ray, electrons, protons, neutrons or ions so that the at least one current limiting region 5 is created in the at least one irradiated portion. Then, in step S5, the gate insulator layer 4, the gate electrode 33 and the first electrode 31 are applied to the semiconductor body 2, and optionally the second electrode 32 as well.

[0131] In another step, not illustrated, the mask layer may partially or completely be removed, and the semiconductor device 1 may be finished.

[0132] The method steps S1 to S5 may not necessarily be performed in the stated order.

[0133] In FIG. 13, method step S5 is illustrated in more detail. As can be seen from FIG. 13, in this step S5 optionally the electrodes have not yet been applied. It is also possible that the gate insulator layer 4 is applied just after the irradiation step, symbolized in FIG. 13 by having the gate insulator layer 4 represented by a dashed line.

[0134] Hence, according to FIG. 13 the mask layer 6, which is, for example, of silicon dioxide, is applied on the top side 20 and is structured to represent the at least one current limiting region 5. In the area of the at least one current limiting region 5, the radiation R can reach the first region 21 through the mask layer 6. In other parts of the semiconductor body 2, it is possible that the radiation R cannot reach the semiconductor body 2.

[0135] Contrary to what is shown in FIG. 13, it is also possible to have the top side 20 completely free of the mask layer 6 in the area of the at least one current limiting region 5.

[0136] For example, the radiation R is composed of electrons, protons or neutrons with energies above about 0.1 MeV. With such a radiation, the crystal lattice of the material of the first region 21 can be damaged so that an increased number of point defects arise. Other than inflicting an increased defect density, it may alternatively or additionally be possible to neutralize the doping of the first region 21 by counter-doping, for example, so that the radiation R can also be composed of ions.

[0137] In FIG. 14 an example of the semiconductor device 1 is shown in top view. It can be seen that the stripe of the gate electrode 33 is located, for example, in a symmetric manner, between two stripes of a half of the first electrode 31 and, thus, between two stripes of the first region 21 having the current limiting region 5. The structure in FIG. 14 corresponds to a unit cell which can be multiplied so that a plurality of the unit cells can be arranged next to one another.

[0138] This stripe design can also be applied to the embodiments of FIGS. 1 and 3 to 9 analogously; in FIG. 2, this kind of symmetric design is already shown.

[0139] Otherwise, the same as to FIGS. 1 to 13 may also apply to FIG. 14, and vice versa.

[0140] Further, see FIG. 15, the semiconductor device 1 can also be of a cellular design, seen in top view, so that a rectangular or square unit cell can arise. For example, in the centre of the unit cell there is the first electrode 31 which is surrounded by the gate electrode 33 in a frame-like manner. Such unit cells can be arranged two-dimensionally so that the semiconductor device 1 can comprise a large number of such unit cells.

[0141] Otherwise, the same as to FIG. 14 may also apply to FIG. 15, and vice versa.

[0142] The components shown in the figures follow, unless indicated otherwise, exemplarily in the specified sequence directly one on top of the other. Components which are not in contact in the figures are exemplarily spaced apart from one another. If lines are drawn parallel to one another, the corresponding surfaces may be oriented in parallel with one another. Likewise, unless indicated otherwise, the positions of the drawn components relative to one another are correctly reproduced in the figures.

[0143] The invention described here is not restricted by the description on the basis of the exemplary embodiments. Rather, the invention encompasses any new feature and also any combination of features, which includes in particular any combination of features in the patent claims, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments.

LIST OF REFERENCE SIGNS

[0144] 1 semiconductor device [0145] 2 semiconductor body [0146] 20 top side of the semiconductor body [0147] 21 first region (source region or emitter region) [0148] 22 well region [0149] 23 drift region [0150] 24 second region (drain region or collector region) [0151] 25 plug region [0152] 31 first electrode (source electrode or emitter electrode) [0153] 32 second electrode (drain electrode or collector electrode) [0154] 33 gate electrode [0155] 4 gate insulator layer [0156] 5 current limiting region [0157] 6 mask layer [0158] 9 comparative example of a semiconductor device [0159] B width of the first region [0160] d depth of the current limiting region [0161] D depth of the first region [0162] E1 first example of the semiconductor device [0163] E2 first example of the semiconductor device [0164] E3 first example of the semiconductor device [0165] L length of the current limiting region [0166] M line of mirror symmetry [0167] R radiation [0168] S method step [0169] T time in us [0170] J.sub.D current density in the drain region in A/cm.sup.2 [0171] V.sub.DS voltage between the drain electrode and the source electrode in V [0172] V length extent of the current limiting regions [0173] W with of an insular current limiting region [0174] Zs distance between current limiting regions along a stripe [0175] Zt distance between current limiting regions in a traverse direction