Semiconductor device with a changeable polarization direction

Abstract

The present disclosure discloses a semiconductor device comprising a plurality of epitaxial layers including a barrier layer and a channel layer such that two-dimensional carrier densities are formed at an interface of the barrier layer and the channel layer, wherein a priority of charge carriers of the channel layer is based on a polarization direction of the barrier layer, and wherein the polarization direction of the barrier layer can be changed by applying an electric field across the barrier layer. The semiconductor device further comprises a first source terminal and a second source terminal, wherein in one of the first source terminal and the second source terminal is ohmic to electrons and other one is ohmic to holes. The semiconductor device further comprises a first drain terminal and a second drain terminal, a gate terminal, and a set terminal ohmic to the channel layer.

Claims

1. A semiconductor device, comprising: a plurality of epitaxial layers including a barrier layer and a channel layer; a gate terminal on the barrier layer; a set terminal ohmic to the channel layer, wherein two-dimensional carrier densities are formed at an interface of the barrier layer and the channel layer, wherein a priority of charge carriers of the channel layer is based on a polarization direction of the barrier layer, and wherein the polarization direction of the barrier layer is based on a polarity of an electric field across the barrier layer applied between the gate terminal and the set terminal; a first source terminal and a second source terminal, wherein the first source terminal is ohmic to electrons and the second source terminal is ohmic to holes; and a first drain terminal and a second drain terminal, wherein the first drain terminal is ohmic to the electrons and the second drain terminal is ohmic to the holes.

2. The semiconductor device of claim 1, wherein the barrier layer includes a Scandium-doped Aluminium Nitride (ScAlN) layer.

3. The semiconductor device of claim 1, wherein the channel layer includes Gallium nitride (GaN) layer.

4. The semiconductor device of claim 1, wherein a material of the first source terminal and the first drain terminal is different from a material of the second source terminal and the second drain terminal.

5. The semiconductor device of claim 1, wherein the first source terminal and the first drain terminal are Titanium (Ti) based n-type ohmic contacts.

6. The semiconductor device of claim 1, wherein the second source terminal and the second drain terminal are Nickel (Ni) based p-type ohmic contacts.

7. The semiconductor device of claim 1, wherein the gate terminal is made of one of: Titanium (Ti), Aluminium (Al), Nickel (Ni), Molybdenum (Mo), Tungsten (W), or Platinum (Pt).

8. The semiconductor device of claim 1, wherein the first drain terminal and the second drain terminal are interconnected by an interconnect.

9. The semiconductor device of claim 1, wherein the epitaxial layers are grown on a substrate by Molecular beam epitaxy (MBE), and wherein the substrate is one of a Sapphire substrate, a GaN substrate, a silicon substrate, or a Silicon Carbide (SiC) substrate.

10. A semiconductor device, comprising: a plurality of epitaxial layers including a barrier layer and a channel layer; a gate terminal on the barrier layer; a set terminal ohmic to the channel layer, wherein two-dimensional carrier densities are formed at an interface of the barrier layer and the channel layer, wherein a priority of charge carriers of the channel layer is based on a polarization direction of the barrier layer, and wherein the polarization direction of the barrier layer is based on a polarity of an electric field across the barrier layer applied between the gate terminal and the set terminal; a source terminal on the channel layer; a drain terminal on the channel layer.

11. The semiconductor device of claim 10, wherein the source terminal and the drain terminal are of same material.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a schematic of a semiconductor device, according to some embodiments of the present disclosure.

(2) FIG. 2A shows a charge balance diagram when the semiconductor device acts as a n-channel Field-Effect Transistor (n-FET), according to some embodiments of the present disclosure.

(3) FIG. 2B shows a charge balance diagram when the semiconductor device acts as a p-channel Field-Effect Transistor (p-FET), according to some embodiments of the present disclosure.

(4) FIG. 3 shows a schematic of a semiconductor device including one source terminal and one drain terminal, according to some embodiments of the present disclosure.

(5) FIG. 4 shows a schematic illustrating biaxial strain of Sc.sub.xAl.sub.(1x)N, Ga.sub.xAl.sub.(1x)N, and In.sub.xAl.sub.(1x)N barriers that are grown pseudomorphically on relaxed Indium Nitride (InN), Gallium Nitride (GaN), and Aluminium Nitride (AlN) buffer layer, according to some embodiments of the present disclosure.

(6) FIG. 5 shows a plot of piezoelectric coefficient e.sub.13.sup.MeAlN(x) vs Scandium (Sc) atom content, according to an embodiment of the present disclosure.

(7) FIG. 6 shows a plot of piezoelectric coefficient e.sub.33.sup.MeAlN(x) vs Sc-atom content, according to an embodiment of the present disclosure.

(8) FIG. 7 shows a plot of piezoelectric polarization vs an alloy composition x, according to some embodiments of the present disclosure.

(9) FIG. 8 shows a plot of predicted spontaneous polarization vs a metal atom content x, for metal-polar, random Me.sub.xAl.sub.(1x)N alloys with a wurtzite crystal structure, according to some embodiments of the present disclosure.

(10) FIG. 9 shows a plot of polarization induced surface charges and a total polarization vs the alloy composition x, for barriers of different materials, according to some embodiments of the present disclosure.

(11) FIG. 10 shows a plot of dielectric constant vs the alloy composition x, according to some embodiments of the present disclosure.

(12) FIG. 11 shows a plot of bandgap vs the alloy composition x, according to some embodiments of the present disclosure.

(13) FIG. 12 shows a plot of polarization induced electron sheet charge vs the alloy composition x, according to some embodiments of the present disclosure.

(14) The presently disclosed embodiments will be further explained with reference to the attached drawings. The drawings shown are not necessarily to scale, with emphasis instead generally being placed upon illustrating the principles of the presently disclosed embodiments.

DETAILED DESCRIPTION

(15) In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without these specific details. In other instances, apparatuses and methods are shown in block diagram form only in order to avoid obscuring the present disclosure.

(16) As used in this specification and claims, the terms for example, for instance, and such as, and the verbs comprising, having, including, and their other verb forms, when used in conjunction with a listing of one or more components or other items, are each to be construed as open ended, meaning that that the listing is not to be considered as excluding other, additional components or items. The term based on means at least partially based on. Further, it is to be understood that the phraseology and terminology employed herein are for the purpose of the description and should not be regarded as limiting. Any heading utilized within this description is for convenience only and has no legal or limiting effect.

(17) FIG. 1 shows a schematic of a semiconductor device 100, according to some embodiments of the present disclosure. The semiconductor device 100 includes epitaxial layers including a barrier layer 101 and a channel layer 103 such that two-dimensional carrier densities are formed at an interface 119 of the barrier layer 101 and the channel layer 103. Further, the semiconductor device 100 includes a buffer layer 105 and a substrate 107. The semiconductor device 100 includes a plurality of terminals, for example, a first source terminal 109a, a second source terminal 109b, a gate terminal 111, a first drain terminal 113a, a second drain terminal 113b, and a set terminal 115. The semiconductor device 100 further includes an insulating layer (not shown in figure) between the gate terminal 111 and the barrier layer 101.

(18) In some implementations, one of the first source terminal 109a and the second source terminal 109b is ohmic to electrons and other one is ohmic to holes. Further, one of the first drain terminal 113a and the second drain terminal 113b is ohmic to the electrons and other one is ohmic to the holes. For example, in an embodiment, the first source terminal 109a is ohmic to the electrons and the second source terminal 109b is ohmic to the holes., and the first drain terminal 113a is ohmic to the electrons and the second drain terminal 113b is ohmic to the holes. The first drain terminal 113a and the second drain terminal 113b are interconnected by an interconnect 117 to form a single output terminal. The gate terminal 111 is arranged on the barrier layer 101. The set terminal 115 is ohmic to the channel layer 103.

(19) Some embodiments are based on the recognition that, to work the semiconductor device 100 as a p-channel Field-Effect Transistor (also referred to as p-FET), the channel layer 103 should include the holes as majority charge carriers, and, to work the semiconductor device 100 as a n-channel Field-Effect Transistor (also referred to as n-FET), the channel layer 103 should include the electrons as the majority charge carriers. To that end, whether the semiconductor device 100 acts as p-FET or n-FET depends on the majority charge carriers in the channel layer 103.

(20) Some embodiments are based on the realization that a priority of charge carriers (i.e., majority charge carriers either holes or electrons) of the channel layer 103 depends on a polarization direction of the barrier layer 101. According to an embodiment, the barrier layer 101 is a III-Nitride compound layer, e.g., Scandium-doped Aluminum Nitride (ScAlN) layer. The barrier layer 101 may be also to be referred to as barrier. The ScAlN material has ferroelectricity characteristic. Ferroelectricity is a characteristic of materials that have a spontaneous electric polarization that can be reversed by application of an external electric field. All ferroelectrics are pyroelectric, with an additional property that their natural electrical polarization is reversible. To that end, the polarization direction of the barrier layer 101, which is the ScAlN layer, can be changed by application of an electric field across the barrier layer 101.

(21) Since the majority charge carriers of the channel layer 103 depends on the polarization direction of the barrier layer 101, and the polarization direction of the barrier layer 101 can be changed by the electric field applied across the barrier layer 101, the electric field can be applied across the barrier layer 101 to switch the polarization direction of the barrier layer 101 such that the semiconductor device 100 can be used as both n-FET and p-FET.

(22) For example, a first voltage can be applied between the gate terminal 111 and the set terminal 115 to form a 2-dimensional electron gas (2-DEG) at the interface 119 of the barrier layer 101 and the channel layer 103. When there is 2-DEG at the interface 119 of the barrier layer 101 and the channel layer 103, the semiconductor device 100 acts as n-FET. Similarly, a second voltage can be applied between the gate terminal 111 and the set terminal 115 to form a 2-dimensional hole gas (2-DHG) at the interface 119 of the barrier layer 101 and the channel layer 103. When there is 2-DHG at the interface 119 of the barrier layer 101 and the channel layer 103, the semiconductor device 100 acts as p-FET. The second voltage is different from the first voltage. For instance, the first voltage applied between the gate terminal 111 and the set terminal 115 may correspond to a positive bias voltage, and the second voltage applied between the gate terminal 111 and the set terminal 115 may correspond to a negative bias voltage.

(23) FIG. 2A shows a charge balance diagram 200 when the semiconductor device 100 acts as n-FET, according to some embodiments of the present disclosure. The charge balance diagram 200 is a plot of c-axis (metal polar) 201 v/s charge density 203. It may be observed from the charge balance diagram 200 that at an interface 205 (that represents the interface 119) of the barrier layer 101 and the channel layer 103, a charge density 207 of the barrier layer 101 is positive and a charge density 209 of the channel layer 103 is negative. Therefore, 2-DEG 211 exists at the interface 205 of the barrier layer 101 and the channel layer 103, and the semiconductor device 100 acts as n-FET.

(24) FIG. 2B shows a charge balance diagram 213 when the semiconductor device 100 acts as p-FET, according to some embodiments of the present disclosure. It may be observed from the charge balance diagram 213 that at the interface 205 of the barrier layer 101 and the channel layer 103, a charge density 215 of the barrier layer 101 is negative and a charge density 217 of the channel layer 103 is negative. Therefore, 2-DHG 219 exists at the interface 205 of the barrier layer 101 and the channel layer 103, and the semiconductor device 100 acts as p-FET.

(25) In such a manner, the semiconductor device 100 can act as both n-FET and p-FET.

(26) In an embodiment, the channel layer 103 of the semiconductor device 100 is a Gallium Nitride (GaN) layer. Specifically, the channel layer 103 corresponds to an unintentionally doped GaN layer. GaN is a binary III/V direct bandgap semiconductor and is a hard material that has a Wurtzite crystal structure. In an embodiment, the epitaxial layers (i.e., the barrier layer 101 and the channel layer 103) are grown on the substrate 107 by deposition methods. Examples of the substrate 107 include a Sapphire substrate, a GaN substrate, a silicon substrate, and a Silicon Carbide (SiC) substrate. The deposition methods may, for example, include Molecular beam epitaxy (MBE). MBE is an epitaxial process by which growth of materials takes place under Ultra-High Vacuum (UHV) conditions on a heated crystalline substrate by an interaction of adsorbed species supplied by atomic or molecular beams. MBE provides several capabilities favorable for the growth of high-purity, epitaxial thin-film metals. For instance, the UHV conditions result in the highest achievable purity of the grown films. Further, the gate terminal 111 is made of a metal, such as, Titanium (Ti), Aluminum (Al), Nickel (Ni), Molybdenum (Mo), Tungsten (W), or Platinum (Pt).

(27) In some embodiments, a material of the first source terminal 109a and the first drain terminal 113a is different from a material of the second source terminal 109b and the second drain terminal 113b. In other words, the first source terminal 109a and the first drain terminal 113a are made from a material that is different from a material with which the second source terminal 109b and the second drain terminal 113b are made. For example, the first source terminal 109a and the first drain terminal 113a are Ti based n-type ohmic contacts, and the second source terminal 109b and the second drain terminal 113b are Ni based p-type ohmic contacts. In another example, the first source terminal 109a and the first drain terminal 113a are Gold (Au) based n-type ohmic contacts, and the second source terminal 109b and the second drain terminal 113b are Au based p-type ohmic contacts.

(28) Alternatively, in some embodiments, instead of the two source terminals and two drain terminals (as shown in FIG. 1), the semiconductor device 100 may include only one source terminal and one drain terminal, which makes a design of the semiconductor device 100 simpler and cost-effective. Such a semiconductor device is described below in FIG. 3.

(29) FIG. 3 shows a schematic of a semiconductor device 300, according to some embodiments of the present disclosure. The semiconductor device 300 includes the barrier layer 101, the channel layer 103, the buffer layer 105, and the substrate 107. Further, the semiconductor device 100 includes a plurality of terminals, for example, a source terminal 301, a drain terminal 303, the gate terminal 111, and the set terminal 115. The source terminal 301 and the drain terminal 303 are arranged on the channel layer 103. The source terminal 301 and the drain terminal 303 are of same material. For example, the source terminal 301 and the drain terminal 303 are Ni based p-type ohmic contacts. As the barrier layer 101 of the semiconductor device 300 (and the semiconductor device 100) is made of the III-Nitride material, the semiconductor device 300 (also the semiconductor device 100) may be referred to as III-Nitride semiconductor device.

(30) Since the ferroelectricity characteristic of ScAlN (i.e., the barrier layer 101) enables the semiconductor device 100 (or the semiconductor device 300) to act as both n-FET and p-FET, it is imperative to model different material-based parameters of ScAlN such as a lattice parameter, a strain parameter, piezoelectric polarization, spontaneous polarization, and the like. The different material-based parameters of ScAlN are described below.

(31) Lattice Parameter and Strain Calculations:

(32) Lattice parameters a.sub.MeAln(x) and c.sub.MeAln(x) (here Me=Scandium (Sc), Gallium (Ga), Indium (In)) of wurtzite crystals according to Vegard's law:
a.sub.GaAlN(x)=3.1095+0.0891x,
a.sub.InAlN(x)=3.1095+0.4753x,
c.sub.GaAlN(x)=4.9939+0.2323x,
c.sub.InAlN(x)=4.9939+0.8063x,

(33) To describe predicted and experimentally observed nonlinearities of structural properties, quadratic equations of form bowing parameter are chosen:
Y.sub.ScAlN(x)=Y.sub.ScNx+Y.sub.AlN(1x)+bx(1x) where b=4Y.sub.ScAlN(x=0.5)2(Y.sub.ScN+Y.sub.AlN)

(34) Theoretical approach as well as experimental measurements for wurtzite Sc.sub.xAl.sub.(1x)N are restricted to Sc concentrations 0x0.5, because of phase transition to a cubic structure expected at about x=0.450.05.

(35) Further, nonlinear dependence of lattice constants can be described by:
a.sub.ScAlN(x)=3.741x+3.110(1x)0.242x(1x),
c.sub.ScAlN(x)=4.245x+4.994(1x)+1.114x(1x)

(36) For pseudomorphic heterostructures, a resulting biaxial strain is isotropic in a basal plane of a barrier (.sub.1=.sub.2) and causes stresses .sub.1=.sub.2, whereas a stress along an [0001]-axis .sub.3 has to be zero. Biaxial strain of the barriers is determined by

(37) ${}_1^{\mathrm{MeAlN}}=\frac{a^{\mathrm{buffer}}-a^{\mathrm{MeAlN}}\left(x\right)}{a^{MeAlN}\left(x\right)}\mathrm{where}\mathrm{Me}=\mathrm{Sc},\mathrm{Ga},\mathrm{In}$

(38) FIG. 4 shows a schematic 400 illustrating the biaxial strain .sub.1.sup.MeAlN(x) of Sc.sub.xAl.sub.(1x)N, Ga.sub.xAl.sub.(1x)N, and In.sub.xAl.sub.(1x)N barriers that are grown pseudomorphically on relaxed Indium Nitride (InN), GaN, and Aluminium Nitride (AlN) buffer layer, according to some embodiments of the present disclosure. A gray shaded region 401 indicates an interval of the biaxial strain 0.03.sub.1.sup.MeAlN(x)0.03, which is relevant for processing robust electronic devices based on pseudomorphic MeAlN/buffer heterostructures. Further, from FIG. 4 it may be observed that,
Me.sub.xAl.sub.(1x)N/InN,0x1: .sub.1.sup.MeAlN(x)0,
Me.sub.xAl.sub.(1x)N/AlN,0x1: .sub.1.sup.MeAlN(x)0,
Ga.sub.xAl.sub.(1x)N/GaN,0x1: .sub.1.sup.GaAlN(x)0,
In.sub.xAl.sub.(1x)N/GaN,0x0.18: .sub.1.sup.InAlN(x)0
0.18x1: .sub.1.sup.MeAlN(x)0,
Sc.sub.xAl.sub.(1x)N/GaN,0x0.2: .sub.1.sup.ScAlN(x)0 and
0.2x0.5: .sub.1.sup.ScAlN(x)0

(39) For .sub.1.sup.MeAlN(x)0, the barriers are under biaxial tensile strain, and a vector of the piezoelectric polarization is pointing from heterostructure surface toward its interface, if the wurtzite crystals are metal polar. For .sub.1.sup.MeAlN(x)0, the barriers are under biaxial compressive strain, and the piezoelectric polarization vector is pointing toward the heterostructure surface. If a polarity of the wurtzite crystals is N-face instead of Me-face, a sign and orientation of the piezoelectric (and spontaneous) polarization vector are inverted.

(40) Piezoelectric Polarization:

(41) According to an embodiment, the piezoelectric polarization as a function of strain for hexagonal materials belonging to C.sub.6v crystallographic point group is given by:

(42) $P_{\mathrm{PE},k}=\underset{l}{.Math.}{e}_{\mathrm{kl}}{}_l,\mathrm{where}k=1,2,3,l=1,.Math.,6.$

(43) A non-vanishing component of the piezoelectric polarization oriented along the [0001]-axis caused by the biaxial strain in the basal plane is

(44) $P_{\mathrm{PE},3}={}_1{e}_{31}+{}_2{e}_{32}+{}_3{e}_{33},=2{}_1{e}_{31}+{}_3{e}_{33},$
where 1=2,
where

(45) ${}_3=-2\frac{C_{13}}{C_{33}}{}_1,$
where C.sub.13 and C.sub.33 are elastic constants for crystals with the wurtzite structure.

(46) $=2{}_1\left({}_{31}-{}_{33}\frac{C_{13}}{C_{33}}\right)$
where

(47) ${}_1\left(x\right)={}_1^{barrier}\left(x\right)=\frac{a^{\mathrm{buffer}}-a^{\mathrm{barrier}}\left(x\right)}{a^{\mathrm{barrier}}\left(x\right)}$

(48) Some embodiments are based on recognition that besides the fact that the piezoelectric polarization along the c-axis is linearly dependent on a relative change of the lattice constant a.sub.barrier, P.sub.PE(biaxial),3 is always negative for the barriers under biaxial tensile strain (.sub.1.sup.barrier(x)0) and positive for crystals under the biaxial compressive strain (.sub.1.sup.barrier(x)0).

(49) A Density-Functional Theory (DFT) simulation yielded values for lattice parameter known as elastic coefficients (given in GPa) to observe a nonlinear behavior of lattice parameter of Sc.sub.xAl.sub.(1x)N and a linear behavior of lattice parameter of Ga.sub.xAl.sub.(1x)N and In.sub.xAl.sub.(1x)N described in the following equations:
C.sub.13.sup.ScAlN(x)=141.70x+108.00(1x)+51.95x(1x)
C.sub.33.sup.ScAlN(x)=155.17x+373.00(1x)+95.49x(1x)
C.sub.13.sup.GaAlN(x)=5x+108
C.sub.33.sup.GaAlN(x)=32x+373,
C.sub.13.sup.InAlN(x)=16x+108,
C.sub.13.sup.InAlN(x)=149x+373

(50) The DFT-simulation also resulted values for tensor components known as piezoelectric coefficients (given in C/m.sup.2) to observe the nonlinear behavior of lattice parameter of Sc.sub.xAl.sub.(1x)N and the linear behavior of lattice parameter of GaxAl.sub.(1x)N and In.sub.xAl.sub.(1x)N described in the following equations:
e.sub.13.sup.ScAlN(x)=1.353x0.593(1x)0.576x(1x)
e.sub.33.sup.ScAlN(x)=9.125x+1.471(1x)6.625x(1x)
e.sub.13.sup.GaAlN(x)=0.253x0.593,
e.sub.33.sup.GaAlN(x)=0.801x+1.471,
e.sub.13.sup.InAlN(x)=0.183x0.593,
e.sub.33.sup.InAlN(x)=0.661x+1.471.

(51) FIG. 5 shows a plot 500 of the piezoelectric coefficient e.sub.13.sup.MeAlN(x) vs Sc-atom content, according to an embodiment of the present disclosure. A line 501 represents the piezoelectric coefficient e.sub.13.sup.MeAlN(x) for Sc.sub.xAl.sub.(1x)N alloys with the wurtzite crystal structure over Sc-atom content (0x0.5). Lines 503 and 505 represent the piezoelectric coefficient e.sub.13.sup.MeAlN(x) for Ga.sub.xAl.sub.(1x)N and In.sub.xAl.sub.(1x)N, respectively, over a whole range of possible compositions (0x1).

(52) FIG. 6 shows a plot 600 of the piezoelectric coefficient e.sub.33.sup.MeAlN(x) vs the Sc-atom content, according to an embodiment of the present disclosure. A line 601 represents the piezoelectric coefficient e.sub.33.sup.MeAlN(x) for Sc.sub.xAl.sub.(1x)N alloys with the wurtzite crystal structure over Sc-atom content (0x0.5). Lines 603 and 605 represent the piezoelectric coefficient e.sub.33.sup.MeAlN(x) for Ga.sub.xAl.sub.(1x)N and In.sub.xAl.sub.(1x)N, respectively, over the whole range of possible compositions (0x1).

(53) From FIG. 5 and FIG. 6, it may be observed that values of the piezoelectric coefficients |e.sub.13.sup.MeAlN(x)| and |e.sub.33.sup.MeAlN(x)| are increased in a nonlinear way, if a number of Al-atoms of AlN substituted by Sc-atoms is enlarged. Further, because of opposite signs of the piezoelectric coefficients (e.sub.13.sup.MeAlN(x)<0, e.sub.33.sup.MeAlN(x)>0) and

(54) $21\left(\mathrm{31}-\mathrm{33}\frac{C_{13}}{C_{33}}\right),$
a value of the piezoelectric polarization for Sc.sub.xAl.sub.(1x)N is increased, if x is enlarged.

(55) For the same biaxial strain 1 and an alloy composition x, the value of piezoelectric polarization of Sc.sub.xAl.sub.(1x)N is larger compared to In.sub.xAl.sub.(1x)N and Ga.sub.xAl.sub.(1x)N.

(56) FIG. 7 shows a plot 700 of piezoelectric polarization

(57) $P_{\mathrm{PE}}^{\frac{\mathrm{MeAlN}}{\mathrm{AlN}}}\left(x\right)\mathrm{vs}$
the alloy composition x, according to some embodiments of the present disclosure. Stars 701 and 703 indicate an alloy composition of lattice-matched In.sub.xAl.sub.(1x)N/GaN [x=(0.180.01)] and Sc.sub.xAl.sub.(1x)N/GaN [x=(0.200.01)] heterostructures, respectively, which are free of piezoelectric polarization.

(58) For heterostructures with the barriers under moderate strain, the below equations can be used as an input as a cause for surface and interface bound sheet charges, depending on an implementation of polarization induced effects, in a self-consistent Schrdinger-Poisson solver based, e.g., on effective mass or tight-binding theory.

(59) $P_{\mathrm{PE}}^{\frac{\mathrm{GaAlN}}{\mathrm{GaN}}}\left(x\right)=-0.058\left(1-x\right)-0.031x\left(1-x\right),1.x0$$P_{\mathrm{PE}}^{\frac{\mathrm{InAlN}}{\mathrm{GaN}}}\left(x\right)=0.16x-0.058\left(1-x\right)-0.011x\left(1-x\right),0.39x0$$P_{\mathrm{PE}}^{\frac{\mathrm{ScAlN}}{\mathrm{GaN}}}\left(x\right)=3.194x-0.058\left(1-x\right)-2.986x\left(1-x\right)-3.603x^2\left(1-x\right),0.38x0$$P_{\mathrm{PE}}^{\frac{\mathrm{GaAlN}}{\mathrm{AlN}}}\left(x\right)=-0.028\left(1-x\right)-0.029x\left(1-x\right),1.x0$$P_{\mathrm{PE}}^{\frac{\mathrm{InAlN}}{\mathrm{AlN}}}\left(x\right)=0.187\left(1-x\right)-0.124x\left(1-x\right),0.2x0$$P_{\mathrm{PE}}^{\frac{\mathrm{ScAlN}}{\mathrm{AlN}}}\left(x\right)=1.199x-0.997x\left(1-x\right),0.21x0$$P_{\mathrm{PE}}^{\frac{\mathrm{InAlN}}{\mathrm{InN}}}\left(x\right)=-0.303\left(1-x\right)-0.106x\left(1-x\right),1.x0.78$

(60) From FIG. 7, it may be observed that the piezoelectric polarization increases if the number of Al-atoms substituted by another metal-atom (Me=Sc, Ga, In) is enlarged, independent of binary buffer layer chosen. For heterostructures grown on the AlN-buffer layer, the piezoelectric polarization of the barrier is always positive (oriented along the [0001]-axis), reaching maximum values of 0.028, 0.057, and 0.089 C/m2 for GaN/AlN, In0.20Al0.80N/AlN and Sc0.21A10.79N/AlN heterostructures, respectively. Piezoelectric barrier polarizations of InxAl1xN/GaN and ScxAl1xN/GaN heterostructures are also positive for x>0.18 and x>0.20, reaching 0.053 and 0.153 C/m2 for x=0.39 and x=0.38, respectively. For 0x<0.18 and 0x<0.20, barriers of the InxAl1xN/GaN and ScxAl1xN/GaN heterostructures as well as those of GaxAl1xN/GaN heterostructures show negative piezoelectric polarization with the highest value for AlN/GaN of 0.058 C/m2.

(61) The piezoelectric polarization

(62) 0$P_{\mathrm{PE}}^{\frac{\mathrm{barrier}}{\mathrm{buffer}}}\left(x\right)$
within barriers of the pseudomorphic MeAlN/buffer heterostructures in dependence on the alloy composition is determined by leveraging nonlinear and linear equations of the biaxial strain, the elastic coefficients, and the piezoelectric coefficients in order to examine the piezoelectric polarization of Sc.sub.xAl.sub.(1x)N in comparison to Ga.sub.xAl.sub.(1x)N and In.sub.xAl.sub.(1x)N.
Spontaneous and Total Polarization:

(63) FIG. 8 shows a plot 800 of predicted spontaneous polarization P.sub.SP.sup.GaAlN(x) vs a metal atom content x, for metal-polar, random Me.sub.xAl.sub.(1x)N (Me=Ga, In or Sc) alloys with the wurtzite crystal structure, according to some embodiments of the present disclosure.

(64) Nonlinear spontaneous polarization of the random alloys can be approximated by (in C/m2),
P.sub.SP.sup.GaAlN(x)=0.034x0.090(1x)+0.019x(1x),
P.sub.SP.sup.InAlN(x)=0.042x0.090(1x)+0.071x(1x)
P.sub.SP.sup.ScAlN(x)=0.874x+0.089(1x)+0.741x(1x)

(65) For metal polar GaAlN, InAlN and ScAlN barriers, and for the buffer layer, the spontaneous polarization is oriented along the direction. A value of the spontaneous polarization decreases, if Al-atoms are replaced by Ga or In, whereas the value of the spontaneous polarization is largely enhanced, if Al is substituted by Sc-atoms.

(66) FIG. 9 shows a plot 900 of polarization induced surface charges and a total polarization P.sub.T.sup.MeAlN(x) vs the alloy composition x, for barriers of different materials, according to some embodiments of the present disclosure. Stars 901 and 903 indicate the polarization induced surface charges and the total polarization of barriers (P.sub.T.sup.MeAlN=P.sub.SP.sup.MeAlN<0) in lattice-matched InxAl1xN/GaN [x=(0.180.01)] and ScxAl1xN/GaN [x=(0.200.01)] hetero structures, respectively.

(67) The total polarization is a sum of the piezoelectric polarization and the spontaneous polarization:

(68) $P_T^{\mathrm{MeAIN}}\left(x\right)=P_{\mathrm{SP}}^{\mathrm{MeAIN}}\left(x\right)+P_{\mathrm{PE}}^{\frac{\mathrm{MeAlN}}{\mathrm{buffer}}}\left(x\right)$

(69) From FIG. 9, it may be observed that a value of the total polarization is decreasing, with increasing number of Al-atoms substituted by Ga-, In-, or Sc-atoms. High total polarizations values above 0.10 C/m.sup.2 are observed for the barriers of the Ga.sub.xAl.sub.1xN/GaN and Sc.sub.xAl.sub.1xN/GaN heterostructures with 0x<0.31 as well as for the In.sub.xAl.sub.1xN/GaN heterostructures with 0x<0.11. The barriers of the Sc.sub.xAl.sub.1xN/GaN heterostructures show the highest values of the total polarization in an interval of 0x<0.31. The polarization induced surface sheet charges of metal polar barrier layers

(70) $\frac{1}{e}{}^{\mathrm{MeAlN}}$
can be determined through a division of the total polarizations P.sub.T.sup.MeAlN by an electron charge (e=1.60210.sup.19 C). For a lattice matched Sc.sub.0.20Al.sub.0.80N/GaN heterostructure, in which the piezoelectric polarization of the barrier vanishes, the total polarization is as high as 0.128 C/m.sup.2.

(71) Further, it is observed from FIG. 9 that the polarization induced surface sheet charges of the pseudomorphic heterostructures are always negative. Negative polarization induced surface sheet charges below 6.210.sup.13 cm.sup.2 are observed for the barriers of the Ga.sub.xAl.sub.1xN/GaN and Sc.sub.xAl.sub.1xN/GaN heterostructures with 0x<0.31 as well as for the In.sub.xAl.sub.1xN/GaN heterostructures with 0x<0.11. For the lattice-matched Sc.sub.0.20Al.sub.0.80N/GaN and In.sub.0.18Al.sub.0.82N/GaN heterostructures, barrier surface sheet charges of 7.9910.sup.13 and 4.1710.sup.13 cm.sup.2 are determined, respectively. These sheet charges are equal to about 8 and 4 elementary electron charges per every 100 surface atoms. Positive bound sheet charges at bottom of relaxed InN, GaN, and AlN buffer crystals are induced by a gradient in the spontaneous polarization only and are calculated to be 2.6210.sup.13, 2.1210.sup.13, and 5.5610.sup.13 cm.sup.2, respectively

(72) Sheet Charge Density and Polarization Induced 2-DEG:

(73) A higher bandgap of the barrier in comparison to the buffer layer is an additional criterion for a selection of suitable heterostructures for processing High Electron Mobility Transistors (HEMTs).
E.sub.g.sup.MeAlN>E.sub.g.sup.buffer

(74) Penetration of a conduction band edge below Fermi level is determined by an iterative approach,

(75) ${}^{\frac{\mathrm{MeAlN}}{\mathrm{buffer}}}\left(x\right)=E_0^{\frac{\mathrm{MeAlN}}{\mathrm{buffer}}}\left(x\right)+\frac{h^2}{4m_{\mathrm{buffer}}^{*}}{n}_s^{\frac{\mathrm{MeAlN}}{\mathrm{buffer}}}\left(x\right)$
where a ground sub band level of the 2-DEG is given as

(76) $E_0^{\frac{\mathrm{MeAlN}}{\mathrm{buffer}}}\left(x\right)={\left\{\frac{9{\mathrm{he}}^2}{16{}_0{}_{33}^{\mathrm{buffer}}\sqrt{8m_{\mathrm{buffer}}^{*}}}{n}_s^{\frac{\mathrm{MeAlN}}{\mathrm{buffer}}}\left(x\right)\right\}}^{\frac{2}{3}}$
where h=4.135710.sup.15 eV s is Planck constant and m*.sub.buffer is an effective electron mass of the buffer layer (M*.sub.GaN=0.222 m.sub.e, m*.sub.InN=0.055 m.sub.e). .sub.0 is a dielectric constant of vacuum, .sub.33.sup.buffer is a relative dielectric coefficient and

(77) $n_s^{\frac{\mathrm{MeAlN}}{\mathrm{buffer}}}$
is a sheet electron concentration.

(78) FIG. 10 shows a plot of 1000 of dielectric constant .sub.33.sup.MeAlN(x) vs the alloy composition x, according to some embodiments of the present disclosure. In the plot 1000, circles 1001, squares 1003, and rhombus 1005 represent measured values of the dielectric constant .sub.33.sup.MeAlN(x) of Sc.sub.xAl.sub.1xN. A line 1007 represents calculated dielectric constant .sub.33.sup.MeAlN(x) of Sc.sub.xAl.sub.1xN. Lines 1009 and 1011 represent the dielectric constant .sub.33.sup.MeAlN(x) of Ga.sub.xAl.sub.(1x)N and In.sub.xAl.sub.(1x)N, respectively.

(79) To describe physical properties of the barriers in dependence of the alloy composition in the intervals of x, the following interpolations are used:

(80) Dielectric Coefficient:
.sub.33.sup.GaAlN(x)=0.03x+10.31
.sub.33.sup.InAlN(x)=4.30x+10.3
.sub.33.sup.ScAlN(x)=89.93x+10.31(1x)62.48x(1x)

(81) For .sub.1.sup.MeAlN(x)0, the barriers are under the biaxial tensile strain, and the vector of the piezoelectric polarization is pointing from the heterostructure surface toward its interface, if the crystals are metal polar. For .sub.1.sup.MeAlN(x)0, the barriers are under the biaxial compressive strain, and the piezoelectric polarization vector is pointing toward the heterostructure surface. If the polarity of the wurtzite crystals is N-face instead of Me-face, the sign and orientation of the piezoelectric (and spontaneous) polarization vector are inverted.

(82) FIG. 11 shows a plot 1100 of bandgap E.sub.g.sup.MeAlN vs the alloy composition x, according to some embodiments of the present disclosure. In the plot 1100, black circles 1101, circles 1103, and rhombus 1105 represent measured values of the bandgap E.sub.g.sup.MeAlN of Sc.sub.xAl.sub.1xN. A line 1107 represents calculated bandgap E.sub.g.sup.MeAlN of Sc.sub.xAl.sub.1xN. Lines 1109 and 1111 represent the bandgap E.sub.g.sup.MeAlN for Ga.sub.xAl.sub.(1x)N and In.sub.xAl.sub.(1x)N, respectively.

(83) Bandgap equations are given as:
E.sub.g.sup.GaAlN(x)=3.42x+6.13(1x)1.0x(1x), for 0x1.0
E.sub.g.sup.InAlN(x)=3.42x+6.13(1x)4.5x(1x), for 0x1.0
E.sub.g.sup.ScAlN(x)=3.42x+6.13(1x)1.5x (1x), for 0x0.5

(84) FIG. 12 shows a plot 1200 of polarization induced electron sheet charge

(85) $n_s^{\frac{\mathrm{MeAlN}}{\mathrm{AlN}}}\left(x\right)\mathrm{vs}$
the alloy composition x, according to some embodiments of the present disclosure. A line 1201 represents the polarization induced electron sheet charge of pseudomorphic, metal polar Ni/Sc.sub.xAl.sub.1xN/GaN. Lines 1203, 1205, and 1207 represent the polarization induced electron sheet charge of Ni/In.sub.xAl.sub.1xN/GaN, Ni/Ga.sub.xAl.sub.1xN/GaN and Ni/In.sub.xAl.sub.1xN/InN heterostructures, respectively. Dark parts 1209, 1211, 1213, and 1215 of the lines 1201-1207 indicate the polarization induced electron sheet charges vs alloy compositions, which can be achieved if limitations set by the maximum strain, a critical barrier thickness and depletion caused by Schottky contact are considered. Stars 1217 and 1219 indicate the polarization induced electron sheet charges of lattice-matched In.sub.xAl.sub.1xN/GaN [x=(0.180.01)] and Sc.sub.xAl.sub.1xN/GaN [x=(0.200.01)] heterostructures, respectively.

(86) The polarization induced electron sheet charges

(87) $n_s^{\frac{\mathrm{MeAlN}}{\mathrm{buffer}}}\left(x\right)$
which can be reached within specific intervals of barrier alloy compositions, can be approximated by: (given in 10.sup.13 cm.sup.2)

(88) $n_s^{\frac{\mathrm{GaAlN}}{\mathrm{buffer}}}\left(x\right)=-0.22x+6.59\left(1-x\right)-3.19x\left(1-x\right),0.68x0.92$$n_s^{\frac{\mathrm{InAlN}}{\mathrm{buffer}}}\left(x\right)=-7.59x+6.61\left(1-x\right)-14.x\left(1-x\right),0.12x0.21$$n_s^{\frac{\mathrm{ScAlN}}{\mathrm{buffer}}}\left(x\right)=-23.87x+5.62\left(1-x\right)+34.1x\left(1-x\right),0.15x0.23$$n_s^{\frac{\mathrm{InAlN}}{\mathrm{buffer}}}\left(x\right)=-0.1x+20.1\left(1-x\right)-12.x\left(1-x\right),0.85x0.98$

(89) To demonstrate influence of the Schottky contact on the electron sheet charge of Ni/Me.sub.xAl.sub.1xN/buffer heterostructures,

(90) $n_s^{\frac{\mathrm{MeAlN}}{\mathrm{buffer}}}\left(d^{\mathrm{MeAlN}}\right)$
is calculated by the below equation in an interval of 0<d.sup.MeAlN<50 nm for different MeAlN barrier and alloy compositions x:

(91) 0$n_s^{\frac{\mathrm{MeAlN}}{\mathrm{buffer}}}\left(x\right)=\frac{1}{e}{}^{\frac{\mathrm{MeAlN}}{\mathrm{buffer}}}\left(x\right)-\frac{{}_0{E}_F^{\mathrm{buffer}}}{e^2}\left(\frac{{}_{33}^{\mathrm{MeAlN}}\left(x\right)}{d^{\mathrm{MeAlN}}}+\frac{{}_{33}^{\mathrm{buffer}}}{d^{\mathrm{buffer}}}\right)=\frac{{}_0{}_{33}^{\mathrm{MeAlN}}\left(x\right)}{e^2{d}^{\mathrm{MeAlN}}}\left(e{}^{\mathrm{MeAlN}}\left(x\right)+{}^{\frac{\mathrm{MeAlN}}{\mathrm{buffer}}}\left(x\right)-E_C^{\frac{\mathrm{MeAlN}}{\mathrm{buffer}}}\left(x\right)\right)$

(92) For barrier thicknesses larger than a space charge zone, the electron sheet charges are increasing by increasing d.sup.MeAlN, independent of the alloy composition of MeAlN-barriers. Such an increasing trend is caused by reduced depletion originating from Ni-gate contact, if a distance between the Schottky contact and a position of electron accumulation is enlarged

(93) The semiconductor device 100 (or the semiconductor device 300) can be used as a logical inverter. For example, when the semiconductor device 100 acts p-FET, the semiconductor device 100 outputs 1 (high) for an input 0 (low). When the semiconductor device 100 acts n-FET, the semiconductor device outputs 0 for an input 1. Since the semiconductor device 100 can be used as both n-FET and p-FET, an area of inverter circuit using the semiconductor device 100 is reduced, which in turn reduces a capacitance. Consequently, switching speed is increased. Further, such semiconductor device 100 based inverters can be applied to design of logic gates and other more complex digital circuits.

(94) The following description provides exemplary embodiments only, and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the following description of the exemplary embodiments will provide those skilled in the art with an enabling description for implementing one or more exemplary embodiments. Contemplated are various changes that may be made in the function and arrangement of elements without departing from the spirit and scope of the subject matter disclosed as set forth in the appended claims.

(95) Specific details are given in the following description to provide a thorough understanding of the embodiments. However, understood by one of ordinary skill in the art can be that the embodiments may be practiced without these specific details. For example, systems, processes, and other elements in the subject matter disclosed may be shown as components in block diagram form in order not to obscure the embodiments in unnecessary detail. In other instances, well-known processes, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the embodiments. Further, like reference numbers and designations in the various drawings indicate like elements.

(96) Also, individual embodiments may be described as a process which is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process may be terminated when its operations are completed but may have additional steps not discussed or included in a figure. Furthermore, not all operations in any particularly described process may occur in all embodiments. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, the function's termination can correspond to a return of the function to the calling function or the main function.

(97) Embodiments of the present disclosure may be embodied as a method, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts concurrently, even though shown as sequential acts in illustrative embodiments.

(98) Although the present disclosure has been described with reference to certain preferred embodiments, it is to be understood that various other adaptations and modifications can be made within the spirit and scope of the present disclosure. Therefore, it is the aspect of the appended claims to cover all such variations and modifications as come within the true spirit and scope of the present disclosure.