Input Facility, Controller, and Measurement Apparatus

Abstract

An input facility for a controller or measurement apparatus includes at least one input circuit for providing at least one digital or at least one analog input for a controller or measurement apparatus, wherein the at least one input circuit includes at least one phase modulation converter that has an amplitude modulator with carrier suppression to which an input signal can be supplied on the input side in order to obtain a carrierless amplitude-modulated signal, an adder for adding a carrier signal shifted by 90 to the carrierless amplitude-modulated signal and for obtaining a phase-modulated signal, a limiter to which the phase-modulated signal is supplied and with which a noise amplitude modulation in the phase-modulated signal can be suppressed, and a demodulation facility to which the signal output from the limiter is supplied and that can be sampled therein with at least one sampling clock signal.

Claims

1. An input facility comprising an input module for a programmable logic controller or a measurement apparatus comprising an oscilloscope or a digital multimeter, the input facility comprising: at least one input circuit which provides at least one digital or at least one analog input for the programmable logic controller or the measurement apparatus, the at least one input circuit comprising at least one phase modulation converter, and the at least one phase modulation converter including: an amplitude modulator with carrier suppression to which an input signal is suppliable on an input side to obtain a carrierless amplitude-modulated signal; an adder for adding a sinusoidal carrier signal shifted by 90 to the carrierless amplitude-modulated signal and for obtaining a phase-modulated signal; a limiter to which the phase-modulated signal is supplied and with which a noise amplitude modulation in the phase-modulated signal is suppressible; and a demodulation facility to which the signal output by the limiter is supplied and which is sampled therein with at least one sampling clock signal.

2. The input facility as claimed in claim 1, wherein at least one electrical isolation is provided between the amplitude modulator and the demodulation facility of the at least one phase-modulation converter; and wherein the at least one electrical isolation comprises at least a pair of coupling capacitors.

3. The input facility as claimed in claim 1, wherein the at least one phase modulation converter is formed as multi-channeled to provide a plurality of inputs; wherein the at least one multi-channel phase modulation converter comprises a central demodulation facility and for each channel a separate amplitude modulator, a separate adder and a separate limiter; and wherein each separate limiter of the plurality of channels is connected to the central demodulation facility, such that each signal output from the plurality of limiters is suppliable to the central demodulation facility and is sampled therein with the at least one sampling clock signal.

4. The input facility as claimed in claim 1, wherein the at least one phase modulation converter is formed as multi-channeled to provide a plurality of inputs; wherein the at least one multi-channel phase modulation converter comprises a central demodulation facility and for each channel a separate amplitude modulator, a separate adder and a separate limiter; and wherein each separate limiter of the plurality of channels is connected to the central demodulation facility, such that each signal output from the plurality of limiters is suppliable to the central demodulation facility and is sampled therein with the at least one sampling clock signal.

5. The input facility as claimed in claim 3, wherein each amplitude modulator of the plurality of channels is connected to the central demodulation facility; wherein the input facility is configured such that each amplitude modulator of the plurality of channels is clocked via the central demodulation facility; and wherein at least one carrier signal generated by the central demodulation facility is suppliable to each amplitude modulator of the plurality of channels.

6. The input facility as claimed in claim, 1 wherein the input facility has a plurality of input circuits for providing a plurality of inputs.

7. The input facility as claimed in claim 6, wherein each input circuit of the plurality of input circuits comprises at least one phase modulation converter.

8. The input facility as claimed in claim 1, wherein the demodulation facility of the at least one phase-modulation converter is implemented on at least one of (i) at least one Field Programmable Gate Array (FPGA) and at least one Application-Specific Integrated Circuit (ASIC).

9. The input facility as claimed in claim 8, wherein the input facility is formed as a programmable logic controller, and the demodulation facility of the at least one phase-modulation converter is implemented on a backplane bus ASIC of the controller.

10. The input facility as claimed in claim 1, wherein the at least one input circuit comprises a signal processing module, and the at least one phase modulation converter is connected downstream of the at least one signal processing module; and wherein the at least one signal processing module comprises at least one of (i) at least one resistor, (ii) at least one diode formed as a Zener diode and (iii) at least one transistor.

11. The input facility as claimed in claim 1, wherein the input facility includes at least one filter configured for a frequency of one of 13.56 MHZ, 27 MHz, 40 MHZ and 433 MHz; wherein the at least one phase modulation converter of the input facility includes at least one filter configured for a frequency of one of 13.56 MHZ, 27 MHz, 40 MHz and 433 MHz.

12. A controller formed as a programmable logic controller, comprising at least one input facility as claimed in claim 1.

13. A measurement apparatus forming the oscilloscope or digital multimeter, comprising at least one input facility as claimed in claim 1.

14. The input facility as claimed in claim 1, wherein the input facility is implemented in the programmable logic controller or the measurement apparatus comprising the oscilloscope or digital multimeter.

15. A phase-modulation converter, comprising: an amplitude modulator with carrier suppression to which an input signal is suppliable on an input side to obtain a carrierless amplitude-modulated signal; an adder for adding to the carrierless amplitude-modulated signal a sinusoidal carrier signal shifted by 90 and for obtaining a phase-modulated signal; a limiter to which the phase-modulated signal is supplied and with which a noise amplitude modulation in the phase-modulated signal is suppressible; and a demodulation facility to which the signal output from the limiter is supplied and which can be sampled therein with at least one sampling clock signal; wherein the phase-modulation converter is implemented in an input circuit of a programmable logic controller or in an input circuit of a measurement apparatus comprising an oscilloscope or digital multimeter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Further advantages and features of the present invention will become clear with the aid of the description given below, which refers to the enclosed drawing, in which:

[0064] FIG. 1 shows a purely schematic diagram of an exemplary embodiment of an inventive programmable logic controller, which comprises at least one inventive input module;

[0065] FIG. 2 shows a purely schematic, enlarged diagram of the input module of the controller of FIG. 1;

[0066] FIG. 3 shows an enlarged, purely schematic diagram of clock generator facility, XOR module, integrator and further components of the demodulation facility of the input module of FIG. 2;

[0067] FIG. 4 shows a purely schematic diagram of a clock generator facility, XOR module, integrator and further components of an alternatively embodied demodulation facility for the use of sampling clock signals;

[0068] FIG. 5 shows an enlarged, purely schematic diagram of the three clock generation blocks of the clock generator facility of the demodulation facilities in accordance with FIGS. 3 and 4;

[0069] FIG. 6 shows, in a purely schematic diagram, a further exemplary embodiment of an inventive input module in a multi-channel embodiment; and

[0070] FIG. 7 shows an enlarged, purely schematic diagram of the demodulation facility of the multi-channel input module of FIG. 6.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

[0071] In the figures, elements and components that are the same or similar are provided with the same reference numbers.

[0072] In a simplified, schematic block diagram FIG. 1 shows an exemplary embodiment of an inventive controller S. In the present exemplary embodiment, this is formed as a programmable logic controller (PLC).

[0073] The controller S comprises at least one input facility, which is formed as a preferably modular input module B. Two input modules B are shown in FIG. 1, a single-channel module with one input terminal, in particular input pin I, and a multi-channel module with three input-side terminals or terminal points I. However, this is to be understood as being purely exemplary. The controller S can also comprise only one input module B or more than two input modules B, which can each be formed both as single-channel and also as multi-channel modules. The number of three input terminals I in the multi-channel variant from FIG. 1 is also purely exemplary. A multi-channel input module in accordance with the present invention can also define just two or more than 3, such as 4, 5, 6, 7, 8 or more inputs for the controller S. The input-side terminals or terminal points I of the input modules B form input-side terminals or terminal point I of the controller S.

[0074] It is also to be understood as being exemplary that the apparatus shown in in FIG. 1 is formed as a controller S. As an alternative, this could also be implemented by a measurement apparatus, where an oscilloscope or a (digital) multimeter might be given as examples for such an apparatus.

[0075] The, or in the case of more than one, the respective input module B (cf. FIGS. 1 and 2) comprises at least one input circuit 1 for providing at least one digital and/or at least one analog input for the controller S or measurement apparatus.

[0076] As evident from the enlarged diagram from FIG. 2, the input circuit 1, as well as the input-side terminal point I has an output-side terminal point O, which in the example shown also form corresponding terminal points of the input module B. The terminal points I, O can involve terminal pins. The input circuit 1 further optionally comprises a signal processing module V connected downstream from the input-side terminal point I, in particular serving for signal conditioning which, for example, has at least one resistor and/or at least one diode, in particular a Zener diode, and/or at least one transistor, which are not shown separately in the simplified FIG. 2.

[0077] Connected after the signal processing module V is a phase modulation converter P. This represents an analog-digital converter. The input signal Sig.sub.A, which can involve an analog, but also a digital signal, can be supplied via the terminal point I, and can reach the phase modulation converter P via the optionally provided signal processing module V. The phase modulation converter P comprises an amplitude modulator 2 with carrier suppression, to which an input signal Sig.sub.A can be supplied at the input 3 or is supplied during operation. The amplitude modulator 2 is configured to obtain a carrierless amplitude-modulated signal Sig.sub.AM from the input signal Sig.sub.A, which is transmitted via two differential lines to the subsequent stages. It should be noted that the two lines for the differential transmission are not shown separately in the Figures, but just one is shown for the sake of simplicity. The amplitude modulator 2 can, for example, involve a switch modulator or a ring modulator. A switch modulator can in this case comprise at least one in particular digital switch and/or at least one mechanical relay and/or at least one reed relay and/or at least one Micro-Electro-Mechanical Systems (MEMS) switch or be provided by these.

[0078] At a second input 4 the amplitude modulator 2 is supplied with a square-wave or sinusoidal carrier signal Sig.sub.T, the generation of which will be discussed in greater detail below. The amplitude-modulated signal Sig.sub.AM emerges as a differential signal for the output 5 of the amplitude modulator 2.

[0079] The amplitude-modulated signal Sig.sub.AM subsequently passes through an analog filter 6 connected downstream from the amplitude modulator 2 and is supplied to adder 7 of the apparatus 1, again connected downstream, via its input 8. A further square-wave or sinusoidal carrier signal Sig.sub.T90, which is phase-shifted by 90 in relation to the sinusoidal carrier signal Sig.sub.T is supplied to the adder 7 at a further input 9. By adding the carrierless amplitude-modulated signal Sig.sub.AM and sinusoidal carrier signal Sig.sub.T90, a phase-modulated signal Sig.sub.PM with noise amplitude modulation is obtained.

[0080] The signal Sig.sub.PM is output at an output 10 of the adder 7 and supplied to a limiter 11 via its input 12. The limiter 11 is configured to suppress a noise amplitude modulation in the signal Sig.sub.PM. The obtained signal Sig.sub.BA, which is also referred to here as the limited signal, emerges at the output 13 of the limiter 11.

[0081] The signal Sig.sub.BA now carries the modulation in temporally different zero crossings by comparison with the 90 carrier signal Sig.sub.T90 or the suppressed carrier signal Sig.sub.T. This is shown purely schematically in FIG. 2 at the top to the right of the limiter 11. The figure shows, in a graph plotted against time in each case, the signal Sig.sub.BA (above) and the signal Sig.sub.T (below) as well as the temporal offset t. The amplitude of the signal Sig.sub.BA fluctuates between 0 and 1, i.e., a signal digital in its amplitude has been obtained.

[0082] The limited signal Sig.sub.BA is supplied to an input 14 of a digital circuit part 15, which serves to demodulate the signal Sig.sub.BA and optionally further purposes. It should be noted, even if in FIG. 2 no further components are shown between the limiter 11 and the digital circuit part 15, it is by no means excluded that such components are present. In other words, the limited signal Sig.sub.BA can be supplied to the digital circuit part 15 directly or also via further components, which can also require a further processing of the signal.

[0083] Furthermore, it should be noted that a coupling capacitor K can be provided in each case, for example, between the analog filter 6 and the analog adder 7 and also between the adder 7 and the limiter 11, which is indicated accordingly in FIG. 2. The pair of coupling capacitors K is used for galvanic isolation or forms such isolation, which in the case of a phase-modulation converter 1 can be provided very simply and almost at any point in the signal path P up to the digital circuit part 15, which represents a significant advantage of the phase-modulation converter 1.

[0084] The digital circuit part 15 can comprise at least one FPGA and/or ASIC or be implemented by at least one FPGA and/or ASIC. In the exemplary illustrated embodiment, the digital circuit part is implemented by an ASIC 15. The ASIC 15 involves a backplane bus ASIC 15 of the PLC S.

[0085] Implemented on the ASIC 15 is a demodulation facility 16 of the apparatus 1, via which digital demodulation of the limited signal Sig.sub.BA can be performed. The demodulation facility 16 can also be referred to as a digital demodulator. In other words, this is integrated in the backplane bus ASIC 15 present in any case of the controller S, which has proved to be especially advantageous.

[0086] With the framework of the demodulation there is, inter alia, sampling of the signal Sig.sub.BA via at least one sampling clock signal CLK0, CLK1, CLK2, CLK3, a comparison with a reference signal Sig.sub.RF likewise sampled with the at least one sampling clock signal and an integration of the comparison, where the generation of the reference signal Sig.sub.RF and the comparison is discussed in more detail below.

[0087] FIG. 3 contains a purely schematic block diagram for the digital demodulation using the demodulation facility 16 for the case in which the sampling is undertaken with a sampling clock signal CLK0. FIG. 4 shows an alternative exemplary embodiment for the use of a plurality of sampling clock signals for the sampling, here of four sampling clock signals CLK0, CLK1, CLK2, CLK3, for example.

[0088] The demodulation facility 16 comprises a clock generation facility 17 and at least one buffer 18 for the limited signal Sig.sub.BA, which is preferably implemented by a FIFO buffer, and is referred to here as the signal buffer 18. Furthermore, at least one further buffer 19 is provided for the reference signal Sig.sub.RF, which is likewise preferably configured as a FIFO buffer and, to distinguish it from the buffer 18 for the signal Sig.sub.BA, is referred to as the reference buffer 19. It should be noted that, despite these different designations, the at least one signal buffer 18 and the at least one reference buffer 19 area can be formed with the same configuration and are formed with the same configuration, here.

[0089] The number of signal buffers 18 and the number of reference buffers 19 expediently matches and corresponds in each case to the number of sampling clock signals CLK0, CLK1, CLK2, CLK3 used. The demodulation facility 16 shown in FIG. 3 thus comprises exactly one signal buffer 18 and exactly one reference buffer 19.

[0090] FIG. 4 shows by way of example that four sampling clock signals CLK0, CLK1, CLK2, CLK3 can be used for sampling the limited signal Sig.sub.BA and simultaneously the reference signal Sig.sub.RF. The demodulation facility 16 from FIG. 4 accordingly comprises four, preferably identical, signal buffers 18 and four, preferably identical, reference buffers 19. In FIG. 2, for reasons of clarity, the buffers 18, 19 are shown behind one another and the frontmost buffer 18, 19 is shown with a solid line, while the buffers 18, 19 lying behind it are shown with a dashed line, in order to illustrate that these can optionally additionally be present.

[0091] Connected downstream of the buffers 18, 19 and connected to the outputs of the buffers 18, 19 is an XOR module 20, which comprises an XOR gate or can be implemented by such a gate. Specifically, the output of the at least one signal buffer 18 is connected to an input of the XOR module 20 and the output of the at least one reference buffer 19 is connected to the other input of the XOR module 20, such that values output can be transferred to this and compared. In the exemplary embodiment from FIG. 4, the outputs of all four signal buffers 18 are connected to one input of the XOR module 20 and the outputs of all four reference buffers 19 are connected to the other input of the XOR module 20.

[0092] Beyond this, an integrator 21 connected downstream of the XOR module 20 is present, via which the values output by the XOR module 20 can be integrated.

[0093] In the exemplary embodiment illustrated in FIGS. 3 and 4, the clock generation facility 17 of the demodulation facility 16 comprises three clock blocks 22, 23, 24 in all. With these three clock blocks 22, 23, 24, a total of seven clock signals CLK0, CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7 are generated, also the sampling clock signals CLK0 (FIG. 3) or CLK0, CLK1, CLK2, CLK3 (FIG. 4) used for the sampling. It should be noted that the clock blocks 22, 23, 24 can also be referred to as clock modules.

[0094] Each of the clock blocks 22, 23, 24 comprises in this case a phase locked loop PLL with a voltage-controlled oscillator VCO. The internal structure of the three clock blocks 22, 23, 24 is shown, once again greatly simplified and purely schematically, in FIG. 5. Here, the phase locked loop PLL with voltage-controlled internal oscillator VCO of the respective clock block 22, 23, 24 is shown simplified as a block element.

[0095] The internal oscillator VCO of each clock block 22, 23, 24 is regulated to an external reference signal from an external clock source 25 which, for example, can be given by a quartz resonator, with a correspondingly set factor to a higher inner frequency f.sub.VCO. The three clock blocks 22, 23, 24 can be supplied from the same external clock source 25, which does not absolutely have to be the case however.

[0096] The clock blocks 22, 23, 24 can, for example, each be implemented by a Mixed-Mode Clock Manager (MCM) module or block or can comprise such a module. The manufacturers Xilinx or AMD for example offer FPGAs with such modules or blocks. FPGAs from Lattice Semiconductor should be mentioned as further examples, in particular the EPS, ECP5, EPC5-5G series, which likewise make possible a fine division of the phase and do so with up to 300 steps.

[0097] Each of the clock blocks 22, 23, 24 has a plurality of clock outputs, which are indicated in FIG. 5 by a block element provided, labeled with a reference number of 26. Each clock output can assume various dividers, and thus frequencies, and various permanently defined phase positions. All clocks are derived in this case from f.sub.VCO. As well as the block element 26 representing the clock outputs there are the sampling clock signals CLK0, CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7 generated and output by the respective clock block 22, 23, 24 in the exemplary embodiment shown. The corresponding numbering CLK0, CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7 is also to be found in FIGS. 3 and 4, this alongside arrows for their actual use, which is discussed in detail below. Each clock block 22, 23, 24 or its oscillator VCO has both phase-locked taps 27 and also at least one phase-variable tap 28. The phase-variable tap 28 makes possible a subdivision of the phase position into fine steps. In the illustrated forms of embodiment, there can be a subdivision into 56 steps, i.e., into steps of 360/n with n=56. The number of 56 steps is to be understood in this case as being exemplary.

[0098] The clock block 22 is used to provide the fast sampling clocks, i.e., sampling clock signals, for the sampling of both the limited signal Sig.sub.BA, and also of the reference signal Sig.sub.RF. In the example in accordance with FIG. 3, it involves the sampling clock signal CLK0, in the sampling in accordance with FIG. 4, the sampling clock signals CLK0, CLK1, CLK2, CLK3.

[0099] 256 MHz is mentioned purely by way of example for a frequency of the fast sampling clock signals CLK0, CLK1, CLK2, CLK3 used for the sampling, which are derived from f.sub.VCO. f.sub.VCO can, for example, amount to 1024 MHz. Naturally, other frequencies are also possible. It is expediently true to say that the frequency of (respective) sampling clock signals CLK0, CLK1, CLK2, CLK3 lies above the modulator frequency of the amplitude modulator 2 by at least one order of magnitude, preferably by two orders of magnitude.

[0100] The second clock block 23 serves to generate slow internal signals. In the exemplary illustrated embodiment, this generates the clock signals CLK4, CLK5 and CLK6. CLK4 is a slow internal clock, which amounts to 32 MHz in the present example, which once again is to be understood as being exemplary and which is used for the buffers 18, 19 and also the XOR module 20 and the integrator 21, which is indicated in FIG. 3 by corresponding arrows. CLK5 corresponds to a square-wave or sinusoidal signal, CLK6 to a signal offset by 90 to the square-wave or sinusoidal signal, i.e., in particular a cosine signal. The square-wave or sinusoidal signal is output via an output 29 of the ASIC 15 in the direction of the adder 7 in order to obtain Sig.sub.T90 and supply it to the input 9 of the adder 7. Via an output 30 of the ASIC 15 the cosine signal is output as Sig.sub.T in the direction of the amplitude modulator 2, in concrete terms to its input 4. It should be noted that an analog filter 6 is still located between the output 29 of the ASIC 15 and the input 9 of the adder 7. On the other hand, such a filter is not shown between the output 30 of the ASIC 15 and the input 4 of the amplitude modulator 2, even if it is not excluded that such a filter is likewise located here.

[0101] The third clock block 24 serves to generate CLK7, which corresponds to the reference signal Sig.sub.RF or is used for the generation thereof. This involves a purely internal signal, which does not leave the ASIC 15.

[0102] The three clock blocks 22, 23, 24 can essentially match in their structure. One difference between the clock block 22 and the blocks 23 and 24, however, consists of the feedback path 31 of the phase-locked loop PLL or of its oscillator VCO being connected to the phase-variable tap 28 of the oscillator VCO, while in the clock modules 23 and 24 the feedback path 31 is connected to a phase-locked tap 27 (cf. FIG. 5).

[0103] In operation of the apparatus, in the case of FIG. 3, the one signal buffer 18 serves to sample the limited signal Sig.sub.BA with the fast sampling clock signal CLK0, or in the case of FIG. 4 with the four signal buffers 18 to sample the limited signal Sig.sub.BA with the four fast sampling clock signals CLK0, CLK1, CLK2, CLK3 with a fixed phase offset to one another as well as the synchronization to the slower internal clock domain. On the input side, the limited signal Sig.sub.BA is supplied for sampling to the (respective) signal buffer 18. The (respective) signal buffer 18 receives both one of the fast sampling clock signals CLK0, CLK1, CLK2, CLK3 for sampling, this from the clock block 22, and also the slower internal clock signal CLK4, to which there is synchronization by means of the (respective) signal buffer 18, this by the clock block 23. It should be noted that in FIG. 4, for use of the number of clock signals CLK0, CLK1, CLK2, CLK3 and associated buffers 18, 19, the arrows for the slower internal clock CLK4 are not inserted additionally for reasons of clarity.

[0104] The (respective) signal buffer 18 has an input with a bit width of 1 and an output with a bit width of 8. The ratio of the bit widths from input to output of the (respective) signal buffers 18 is chosen as similar to the ratio of the clocks CLKi/CLK4, with i=0, 1, 2, 3, or vice versa. In the example described here CLKi/CLK4=256 MHz/32 MHz=8, with i=0, 1, 2, 3.

[0105] Whenever 8 sampling values are accumulated in a signal buffer 18, this number of values is output from the signal buffer 18 and is output to the XOR module 20. The values are output with the slower clock of CLK4, i.e. 32 MHz in this case. It can also be said that the (respective) signal buffer 18 delivers as output the fully sampled digital limited signal Sig.sub.BA in the temporally correct order.

[0106] For the (respective) reference buffer 19 what has been stated above applies fully analogously, with the difference that this is not supplied with the limited signal Sig.sub.BA, but with the reference signal Sig.sub.RF for sampling with the (respective) fast sampling clock signal CLK0, CLK1, CLK2, CLK3 and for synchronization to CLK4, as indicated in FIGS. 3 and 4 schematically by associated arrows.

[0107] The fully sampled digital reference signal, which is clocked with the same clock signal CLK0 or with the same clock signals CLK0, CLK1, CLK2, CLK3 is thus obtained from the (respective) reference buffer 19. Thus, the temporal sequence for the fully sampled limited Sig.sub.BA signal matches that of the signal obtained from the signal buffer or buffers 18.

[0108] In the embodiment illustrated in FIG. 4 with the four sampling clock signals CLK0, CLK1, CLK2, CLK3, each signal buffer 18 in this case outputs another part of the signal. Each sampling domain delivers a data block. In the same domain, in line with this the reference signals Sig.sub.RF are sampled. Then, in the XOR module 20 a block-by-block comparison is possible.

[0109] To achieve an increased resolution, there can optionally be provision, with the framework of the sampling for the phase position of the one sampling clock signal CLK0 (FIG. 3) or of the number of sampling clock signals CLK0, CLK1, CLK2, CLK3 (FIG. 4), which are used for the sampling of the limited signal Sig.sub.BA and the reference signal Sig.sub.RF, to be dynamically changed. For this, the feedback path 31 of the clock block 22 for the generation of the fast clock signals CLK0, CLK1, CLK2, CLK3, as mentioned above, is connected to the phase-variable tap 28 of the oscillator VCO.

[0110] The phase position of the signal fed back to the oscillator VCO via the feedback path 31 is continuously or repetitively changed. This preferably occurs cyclically for example every couple of microseconds, such as every 42 microseconds. The shifting of the phase position is undertaken in such cases by steps of 360/56 in each case and in the same direction. A logic 32 is provided (cf. FIG. 2), which is preferably implemented on ASIC 15, which also comprises or forms the demodulation facility 16, and which the corresponding controller converts for the dynamic phase position change of the sampling clock signals. The logic 32 can be a component of the demodulation facility 16.

[0111] In the exemplary embodiment illustrated in FIG. 4, the number of sampling clock signals CLK0, CLK1, CLK2, CLK3 are all generated from the output signal of the one oscillator VCO of the clock block 22. Accordingly, the repeated changing of the phase position of the feedback signal results in a repeated changing of the phase positions of all sampling clock signals CLK0, CLK1, CLK2, CLK3 used for the sampling synchronously and by the same-size steps.

[0112] Through the stepping of the feedback signal over the feedback path 31 the phase position of all CLK outputs of the clock module 22 also changes synchronously for each phase step of the oscillator VCO. The individual sampling clock signals CLK0, CLK1, CLK2, CLK3 can additionally continue to be rigidly offset in relation to one another by 90.

[0113] In the case described, a phase step of

[00001]$t_{\mathrm{STEP}}=1/\left(768\mathrm{MHz}*56\right)=1/43.008\mathrm{GHz}=23.25\mathrm{ps}.$

[0114] The 256 MHz sampling clocks CLK0-CLK3 offset from one another by 90 means that only a phase difference of

[00002]$t_{\mathrm{diff}}=1/\left(256\mathrm{MHz}*4\right)=976.56\mathrm{ps}$ [0115] must be bridged to cover all possible discrete sampling points by means of the finely stepped phase steppings. In ASIC 15, 42 (976.56 ps/23.25 ps) periods of the modulator frequency are summed.

[0116] The computational solution is produced as

[00003]$\log 2\left(90/360*43008\mathrm{MHz}/1\mathrm{MHz}\right)=13.39\mathrm{bits}$ [0117] without changing the frequency of the amplitude modulator 2.

[0118] The data rate reduces from 1 MHz to 1 MHz/42=23.8 kHz.

[0119] By contrast, without the dynamic phase shifting, a computational solution would be produced of

[00004]$\log 2\left(90/360*4*256\mathrm{MHz}/1\mathrm{MHz}\right)=8\mathrm{bits}.$

[0120] As emphasized above, the resolution increase by the dynamic phase shifting is optional. In particular, for the case in which one or more digital inputs is provided, as a rule a lower resolution can also suffice. Accordingly, the modulator frequency of the amplitude modulator 2 can also be increased. With this, on the one hand, the data rate increases and, on the other hand, filter elements can once again be significantly smaller.

[0121] It would also be conceivable to employ integrated filters, as are used in large volumes in the RFID/ISM area. For example, filters for frequencies of 13.56 MHz or 27 MHz or 40 MHz or 433 MHz should be mentioned.

[0122] With the same architecture, despite this a resolution of

[00005]$\log 2\left(90/360*43008\mathrm{MHz}/13.56\mathrm{MHz}\right)=9.6\mathrm{bits}\left(\mathrm{RFID}\mathrm{frequency}\right)$ [0123] or a resolution of

[00006]$\log 2\left(90/360*43008\mathrm{MHz}/315\mathrm{MHz}\right)=5.09\mathrm{bits}\left(\mathrm{SAW}\mathrm{filter}\mathrm{for}\mathrm{ISM}\mathrm{band}\right)$ [0124] would still be produced, which is still sufficient for establishing in particular a digital state.

[0125] With the XOR modules 20 connected downstream of the buffers 18, 19, it is established following on from the fast sampling (with or without dynamic phase shifting) and the synchronization at what points in time the limited signal Sig.sub.BA and the reference signal Sig.sub.RF are different. The subsequent integration via the integrator 21 produces the modified value, which is output as Sig.sub.O from the ASIC 15 or will initially be further processed (cf. FIG. 2).

[0126] In an expedient manner, there is integration in each case until such time as the dynamic change of the phase position of the sampling clock signals CLK0, CLK1, CLK2, CLK3 described here has occurred over an angular range of 360/m, where m corresponds to the number of sampling clock signals used for the sampling of the limited signal Sig.sub.BA. The inventive apparatus 1, in particular its demodulation facility 16 or an FPGA 15 of the apparatus, can be configured accordingly.

[0127] Particularly for the case in which there is no dynamic change of the phase position of the sampling clock signal or signals CLK0, CLK1, CLK2, CLK3, a new converted digital value is produced with each period.

[0128] Sig.sub.O is in particular a digital signal or digital value in the range of values of, for example, 0 to 2.sup.a with the resolution a of the phase-modulation converter P. This digital value can be forwarded or further processed and supplied for use. There can be, for example, provision, for the case of a digital input, for there to be a comparison with a threshold value and then only 1 bit (0/1) being forwarded per channel C1, C2, . . . , Cn, in order to keep the amount of data as small as possible.

[0129] It should be noted that preferably, independent of whether the input signal Sig.sub.A at the input-side terminal point I, such as PLC terminal, is analog or digital, the signal is considered to be an analog value particularly up to the demodulation facility 16 or through the demodulation facility 16. Only during the interpretation of the value can a (superordinate) logic then decide whether the signal is now digital or describes a value, especially a process variable, in an analog manner.

[0130] FIG. 6 shows, in a purely schematic diagram, a further exemplary embodiment of an inventive input facility in the form of an input module B. This can likewise be a component of a programmable logic controller not shown in any greater detail or also of a measurement apparatus. The example in accordance with FIG. 6 is formed as multi-channeled in this case, specifically as a two-channel apparatus. For this, it comprises an input circuit 1 with a multi-channel phase modulation converter P. It should be noted that FIG. 6 is intended to show the basic structure of a multi-channel configuration, where, for reasons of clarity, only a few of the components of the input circuit 1 and of its phase-modulation converter P are shown, these being partly even more simplified than in FIG. 1.

[0131] As evident, a separate signal processing module V is present for each of the two channels C1, C2. Also provided for each channel C1, C2 are a separate amplitude modulator 2, at least one galvanic isolation with two coupling capacitors K, and also a separate adder 7 and limiter 11. In other words, these components scale with the number of channels C1, C2.

[0132] By contrast, the phase modulation converter 2, despite the multi-channel embodiment, comprises just one central demodulation facility 16, which is preferably implemented on an FPGA or ASIC 15. The limiters 11 of the number of, here two, channels C1, C2 are connected in this case to the central demodulation facility 16, so that the central demodulation facility 16 is supplied with signals Sig.sub.BA output in each case from the number of limiters 11 and in each case can be sampled therein with at least one sampling clock signal CLK0, CLK1, CLK2, CLK3. The connection is a signaling connection. The number of limiters 11 can be connected directly or also via further elements to the central demodulation facility 16.

[0133] By comparison with the realization of a conventional ADC on the process side, the phase modulation converter 2 has the further advantage that a separate complete converter for each channel C1, C2 does not have to be constructed. There is also no need for the complete generation of the supply voltages, references and the filters necessary for each channel for the converter, which is frequently more expensive than the actual converter, both with regards to costs and also to space on the printed circuit board. The present solution, on the other hand, is markedly leaner and lower-cost. In particular, a separate FPGA or ASIC 15 is also not required for each channel.

[0134] There can be provision for a scaling within the one ASIC 15 (or alternatively of an FPGA) for the number of channels C1, C2, . . . , Cn. This is shown (purely schematically) in FIG. 7.

[0135] An ASIC input 14 is provided on the ASIC 15 in this case for each channel C1, C2, . . . . Cn, as well as separate buffers 18, 19, a separate XOR module 20 and a separate integrator 21. The functioning for each channel C1, C2, . . . , Cn, is as described in detail above in conjunction with FIG. 3 for the use of a sampling clock signal CLK0 and in conjunction with FIG. 4 for the use of four sampling clock signals CLK0, CLK1, CLK2, CLK3 for the case of just one channel.

[0136] The components scaled-up for the number of channels C1, C2, . . . , Cn, are connected in this case to one central clock generation facility 17. This can, as already described here with reference to FIGS. 2 to 5, comprise three clock generation modules 22, 23, 24 for example, via which clock signals CLK0, CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7 can be generated, which are then used for all channels C1, C2, . . . , Cn. This is indicated in FIG. 7 by arrows, which connect the central clock generation facility 17 to the components present in multiples for the channels C1, C2, . . . , Cn, in particular the buffers 18, 19 and integrators 21.

[0137] The values output by the integrators 21 can, for example, be passed to a tapping off and preparation logic 33 present on the ASIC 15, which taps these off and prepares them, possibly for a higher logic (not shown).

[0138] As evident in FIG. 6, the ASIC 15 or the demodulation facility 16 implemented thereon are connected to the amplitude modulators 2 of the number of channels C1, C2. The input module B in this case is configured such that the amplitude modulators 2 of the number of channels C1, C2 can be clocked via the central demodulation facility 16, and/or such that the amplitude modulators 2 of the number of channels C1, C2 can be supplied with at least one carrier signal generated by the central demodulation facility 16.

[0139] Specifically, the output 30 that can also be seen in FIG. 7 is connected to each of the amplitude modulators 2 of the number of channels C1, C2 and is connected in each case to its input 4 (cf. FIG. 1). With this embodiment, a gating function, as is often needed for clock-synchronous reading in of inputs, in particular digital inputs, is already implicitly realized.

[0140] All channels C1, C2, . . . , Cn are derived from the same reference clock. Consequently, a clock-synchronous operation is produced automatically. Solely the delay times and the reaction times of the switch modulators 2 can still vary from channel to channel C1, C2, . . . , Cn.

[0141] In a phase modulation converter P, there is no transmission of 1 and 0, but an analog sampling in particular of the limited signal Sig.sub.BA. This is also in the case in which the phase modulation converter P is used for a digital input, i.e., for digital signals. In the analog area, it is possible, as well as the two states 1 and 0 to also cover additional states, in particular a third state. This can be used in order, together with the actual signal state, to transmit diagnostic information, such as information about a wire or line break and to do this with an additional channel C1, C2, . . . , Cn being needed. The input signal Sig.sub.A can, in other words, as well as the actual signal information, comprise diagnostic information, which can be transmitted as well via the same channel C1, C2, . . . , Cn.

[0142] Through the transmission of the information about the electrical isolation K associated with the use of the phase-modulation converter in the frequency range a marked advantage as regards EM compatibility is further produced. Common Mode Faults are suppressed by the AC coupling capacitors K. Only a sensibility as regards asymmetry exists. There can, however, easily be a filtering here via low-voltage capacitors on the logic side.

[0143] Although the invention has been illustrated and described in greater detail by the preferable exemplary embodiment, the invention is not restricted by the disclosed examples and other variations can be derived herefrom by the person skilled in the art, without departing from the scope of protection of the invention.

[0144] Thus, while there have been shown, described and pointed out fundamental novel features of the invention as applied to a preferred embodiment thereof, it will be understood that various omissions and substitutions and changes in the form and details of the methods described and the devices illustrated, and in their operation, may be made by those skilled in the art without departing from the spirit of the invention. For example, it is expressly intended that all combinations of those elements and/or method steps that perform substantially the same function in substantially the same way to achieve the same results are within the scope of the invention. Moreover, it should be recognized that structures and/or elements and/or method steps shown and/or described in connection with any disclosed form or embodiment of the invention may be incorporated in any other disclosed or described or suggested form or embodiment as a general matter of design choice. It is the intention, therefore, to be limited only as indicated by the scope of the claims appended hereto.