PUSH-PULL SOURCE FOLLOWER CIRCUIT USING BIASING TECHNIQUE TO PROGRAM BIAS CURRENT AND OUTPUT MEAN VOLTAGE INDEPENDENTLY

Abstract

A push-pull source follower circuit includes a main source follower, a first biasing circuit, and a second biasing circuit. The main source follower includes a first transistor and a second transistor between a first power rail and a second power rail, where the first transistor and the second transistor include an N-type transistor and a P-type transistor. The first biasing circuit programs a bias current of the main source follower through generating a first bias voltage of the first transistor. The second biasing circuit programs an output mean voltage of the push-pull source follower circuit through generating a second bias voltage of the second transistor. The bias current and the output mean voltage are programmed independently.

Claims

1. A push-pull source follower circuit comprising: a main source follower, comprising: a first transistor, having a control terminal, a first connection terminal, and a second connection terminal, wherein the second connection terminal of the first transistor is coupled to a first power rail, and the first terminal of the first transistor is coupled to an output node of the push-pull source follower circuit; and a second transistor, having a control terminal, a first connection terminal, and a second connection terminal, wherein the second connection terminal of the second transistor is coupled to a second power rail, the first terminal of the second transistor is coupled to the output node of the push-pull source follower circuit, and the first transistor and the second transistor comprise an N-type transistor and a P-type transistor; a first biasing circuit, configured to program a bias current of the main source follower through generating and outputting a first bias voltage to the control terminal of the first transistor; and a second biasing circuit, configured to program an output mean voltage of the push-pull source follower circuit through generating and outputting a second bias voltage to the control terminal of the second transistor; wherein the bias current and the output mean voltage are programmed independently.

2. The push-pull source follower circuit of claim 1, wherein the first biasing circuit comprises: a replica source follower, wherein the replica source follower corresponds to the first transistor of the main source follower, and comprises: a third transistor, having a control terminal, a first connection terminal, and a second connection terminal, wherein the first bias voltage is generated at the control terminal of the third transistor, and the second connection terminal is coupled to the first power rail; a first error amplifier, having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first error amplifier is coupled to the first connection terminal of the third transistor, the second input terminal of the first error amplifier is configured to receive a first input voltage indicative of the output mean voltage, and the output terminal of the first error amplifier is coupled to the control terminal of the third transistor; and a current source, coupled to the first connection terminal of the third transistor, and configured to provide a reference current.

3. The push-pull source follower circuit of claim 2, wherein the reference current is programmable, and the bias current of the main source follower is set by programming the reference current.

4. The push-pull source follower circuit of claim 2, wherein the first biasing circuit further comprises: a first low-pass filter, coupled between the second input terminal of the first error amplifier and the output node of the push-pull source follower circuit, wherein the first low-pass filter is configured to apply low-pass filtering to an output voltage of the push-pull source follower circuit for generating the first input voltage.

5. The push-pull source follower circuit of claim 4, wherein the second biasing circuit comprises: a second error amplifier, having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second error amplifier is configured to receive a second input voltage indicative of a mean voltage, and the second input terminal of the second error amplifier is configured to receive a reference voltage, and the second bias voltage is generated at the output terminal of the second error amplifier.

6. The push-pull source follower circuit of claim 5, wherein the second biasing circuit further comprises: a second low-pass filter, coupled between the first input terminal of the second error amplifier and the output node of the push-pull source follower circuit, wherein the second low-pass filter is configured to apply low-pass filtering to the output voltage of the push-pull source follower circuit for generating the second input voltage.

7. The push-pull source follower circuit of claim 5, wherein the output voltage of the push-pull source follower is supplied to a next-stage circuit, and the second biasing circuit further comprises: a second low-pass filter, coupled between the first input terminal of the second error amplifier and an output node of the next-stage circuit, wherein the second low-pass filter is configured to apply low-pass filtering to an output voltage of the next-stage circuit for generating the second input voltage.

8. The push-pull source follower circuit of claim 5, wherein the output voltage of the push-pull source follower is supplied to a next-stage circuit, and the second biasing circuit further comprises: a second low-pass filter, coupled between the first input terminal of the second error amplifier and an internal node of the next-stage circuit, wherein the second low-pass filter is configured to apply low-pass filtering to an internal-node voltage of the next-stage circuit for generating the second input voltage.

9. The push-pull source follower circuit of claim 5, wherein the reference voltage is programmable, and the output mean voltage of the push-pull source follower circuit is set by programming the reference voltage.

10. The push-pull source follower circuit of claim 2, wherein the input voltage is set by a first reference voltage.

11. The push-pull source follower circuit of claim 10, wherein the second biasing circuit comprises: a second error amplifier, having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second error amplifier is configured to receive a second input voltage indicative of the output mean voltage, and the second input terminal is configured to receive the first reference voltage, and the second bias voltage is generated at the output terminal of the second error amplifier.

12. The push-pull source follower circuit of claim 11, wherein the second biasing circuit further comprises: a second low-pass filter, coupled between the first input terminal of the second error amplifier and the output node of the push-pull source follower circuit, wherein the second low-pass filter is configured to apply low-pass filtering to the output voltage of the push-pull source follower circuit for generating the second input voltage.

13. The push-pull source follower circuit of claim 11, wherein the first reference voltage is programmable, and the output mean voltage of the push-pull source follower circuit is set by programming the first reference voltage.

14. The push-pull source follower circuit of claim 10, wherein the output voltage of the push-pull source follower is supplied to a next-stage circuit, and the second biasing circuit comprises: a replica next-stage circuit, wherein the replica next-stage circuit corresponds to the next-stage circuit, and the first reference voltage is supplied to the replica next-stage circuit; and a second error amplifier, having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second error amplifier is configured to receive a second input voltage indicative of a mean voltage, and the second input terminal of the second error amplifier is configured to receive a second reference voltage obtained from the replica next-stage circuit, and the second bias voltage is generated at the output terminal of the second error amplifier.

15. The push-pull source follower circuit of claim 14, wherein the second reference voltage is generated an output node of the replica next-stage circuit, and the second biasing circuit further comprises: a second low-pass filter, coupled between the first input terminal of the second error amplifier and an output node of the next-stage circuit, wherein the second low-pass filter is configured to apply low-pass filtering to an output voltage of the next-stage circuit for generating the second input voltage.

16. The push-pull source follower circuit of claim 14, wherein the second reference voltage is generated at an internal node of the replica next-stage circuit, and the second biasing circuit further comprises: a second low-pass filter, coupled between the first input terminal of the second error amplifier and an internal node of the next-stage circuit, wherein the second low-pass filter is configured to apply low-pass filtering to an internal-node voltage of the next-stage circuit for generating the second input voltage.

17. The push-pull source follower circuit of claim 14, wherein the second reference voltage is programmable, and the output mean voltage of the push-pull source follower circuit is set by programming the second reference voltage.

18. The push-pull source follower circuit of claim 2, wherein the third transistor of the replica source follower is a scaled version of the first transistor of the main source follower.

19. The push-pull source follower circuit of claim 1, wherein the first transistor is the P-type transistor, the second transistor is the N-type transistor, a voltage delivered on the first power rail is lower than a voltage delivered on the second power rail.

20. The push-pull source follower circuit of claim 1, wherein the first transistor is the N-type transistor, the second transistor is the P-type transistor, a voltage delivered on the first power rail is higher than a voltage delivered on the second power rail.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1 is a diagram illustrating a first push-pull source follower design using the proposed biasing technique according to an embodiment of the present invention.

[0008] FIG. 2 is a diagram illustrating a second push-pull source follower design using the proposed biasing technique according to an embodiment of the present invention.

[0009] FIG. 3 is a diagram illustrating a third push-pull source follower design using the proposed biasing technique according to an embodiment of the present invention.

[0010] FIG. 4 is a diagram illustrating a fourth push-pull source follower design using the proposed biasing technique according to an embodiment of the present invention.

[0011] FIG. 5 is a diagram illustrating a fifth push-pull source follower design using the proposed biasing technique according to an embodiment of the present invention.

[0012] FIG. 6 is a diagram illustrating a sixth push-pull source follower design using the proposed biasing technique according to an embodiment of the present invention.

DETAILED DESCRIPTION

[0013] Certain terms are used throughout the following description and claims, which refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms include and comprise are used in an open-ended fashion, and thus should be interpreted to mean include, but not limited to . . . . Also, the term couple is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

[0014] FIG. 1 is a diagram illustrating a first push-pull source follower design using the proposed biasing technique according to an embodiment of the present invention. The push-pull source follower circuit 100 is based on a complementary structure, and adopts the proposed biasing technique to independently program a bias current and an output mean voltage. In this embodiment, the push-pull source follower circuit 100 includes a main source follower 102 and a plurality of biasing circuits 104 and 106. The main source follower 102 includes transistors MN2 and MP2, where the transistor MN2 is an NMOS transistor acting as an N-type source follower, and the transistor MP2 is a PMOS transistor acting as a P-type source follower. The transistor MN2 has a gate terminal (which acts as a control terminal), a source terminal (which acts as a first connection terminal), and a drain terminal (which acts as a second connection terminal), where the source terminal is coupled to an output node N of the push-pull source follower circuit 100, and the drain terminal is coupled to a power rail on which a supply voltage VDD is delivered. The transistor MP2 has a gate terminal (which acts as a control terminal), a source terminal (which acts as a first connection terminal, and a drain terminal (which acts as a second connection terminal), where the source terminal is coupled to the output node N of the push-pull source follower circuit 100, and the drain terminal is coupled to a power rail on which a ground voltage GND is delivered.

[0015] The biasing circuit 104 is configured to program a bias current of the main source follower 102 through generating and outputting a bias voltage V.sub.CM_P to the gate terminal of the transistor MP2. The bias voltage V.sub.CM_P may be supplied to the gate terminal of the transistor MP2 through a coupling circuit 108 such as an active coupler or a passive coupler. For example, the coupling circuit 108 may be implemented using a direct-current (DC) level shifter including an alternating-current (AC) coupling capacitor and a DC bias resistor, where the AC coupling capacitor passes an AC component of an input voltage V.sub.IN, and the DC bias resistor adds a DC bias (i.e., bias voltage V.sub.CM_P) to the AC component V.sub.IN, thus resulting in a gate voltage (V.sub.IN+V.sub.CM_P) at the gate terminal of the transistor MP2.

[0016] The biasing circuit 106 is configured to program an output mean voltage (i.e., a DC level of an output voltage V.sub.OUT) of the push-pull source follower circuit 100 through generating and outputting a bias voltage V.sub.CM_N to the gate terminal of the transistor MN2. The bias voltage V.sub.CM_N may be supplied to the gate terminal of the transistor MN2 through a coupling circuit 110 such as an active coupler or a passive coupler. For example, the coupling circuit 110 may be implemented using a DC level shifter including an AC coupling capacitor and a DC bias resistor, where the AC coupling capacitor passes an AC component of the input voltage V.sub.IN, and the DC bias resistor adds a DC bias (i.e., bias voltage V.sub.CM_N) to the AC component V.sub.IN, thus resulting in a gate voltage (V.sub.IN+V.sub.CM_N) at the gate terminal of the transistor MN2.

[0017] In this embodiment, the bias current and the output mean voltage are programmed independently. Regarding the biasing circuit 104, it includes a replica source follower 111, a current source 112, a low-pass filter 114, an error amplifier AMP1, and a capacitor C1. The replica source follower 111 corresponds to the transistor MP2 of the main source follower 102, and includes a transistor MP1, where the transistor MP1 is a PMOS transistor acting as a P-type source follower. The transistor MP1 has a gate terminal (which acts as a control terminal), a source terminal (which acts as a first connection terminal), and a drain terminal (which acts as a second connection terminal), where the bias voltage V.sub.CM_P is generated at the gate terminal, and the drain terminal is coupled to a power rail on which the ground voltage GND is delivered. Specifically, the replica source follower 111 is a replica of the P-type source follower (i.e., transistor MP2) included in the main source follower 102, where a current-to-voltage (I-V) characteristic of the replica source follower 111 may be the same as that of the P-type source follower included in the main source follower 102. In some embodiments of the present invention, the replica source follower 111 (particularly, transistor MP1 of replica source follower 111) may be a scaled version of the P-type source follower in the main source follower 102 (particularly, transistor MP2 of main source follower 102). For example, the transistor MP1 may be a scaled-down version of the transistor MP2 for power saving and area saving. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention.

[0018] The error amplifier AMP1 has a first input terminal, a second input terminal, and an output terminal, where the first input terminal is coupled to the source terminal of the transistor MP1, the second input terminal is configured to receive an input voltage V.sub.DC1 indicative of the output mean voltage, and the output terminal is coupled to the gate terminal of the transistor MP1.

[0019] The low-pass filter 114 is coupled between the second input terminal of the error amplifier AMP1 and the output node N of the push-pull source follower circuit 100, and is configured to apply low-pass filtering to the output voltage V.sub.OUT of the push-pull source follower circuit 100 for generating the input voltage V.sub.DC1. Specifically, the low-pass filter output is a DC component of the output voltage V.sub.OUT.

[0020] The current source 112 is coupled between the first input terminal of the error amplifier AMP1 and the power rail on which the supply voltage VDD is delivered, and is configured to provide a reference current I.sub.bias. The reference current I.sub.bias acts as a bias current flowing through the transistor MP1, such that an output voltage V.sub.REP_O of the replica source follower 111 is established at the source terminal of the transistor MP1 under a condition that the bias voltage V.sub.CM_P is applied to the gate terminal of the transistor MP1. The error amplifier AMP1 adaptively adjusts the bias voltage V.sub.CM_P according to an error between the output voltage V.sub.REP_O and the input voltage V.sub.DC1. The bias voltage V.sub.CM_P is held by the capacitor C1. Since the reference current I.sub.bias flowing through the transistor MP1 has a constant current value, the output voltage (i.e., source voltage of transistor MP1) V.sub.REP_O changes in response to a change of the bias voltage (i.e., gate voltage of transistor MP1) V.sub.CM_P. In other words, the error amplifier AMP1 adaptively adjusts the bias voltage V.sub.CM_P to minimize the error between the output voltage V.sub.REP_O and the input voltage V.sub.DC1. Hence, the error amplifier AMP1 will make the output voltage V.sub.REP_O same as or close to the input voltage V.sub.DC1 that is the mean of the output voltage V.sub.OUT.

[0021] Since the replica source follower 111 is a replica (e.g., scaled version) of the P-type source follower of the main source follower 102, a bias current of the main source follower 102 is also a replica (e.g., scaled version) of the reference current I.sub.bias under a condition that gate terminals of transistors MP1 and MP2 are biased by the same bias voltage V.sub.CM_P, drain terminals of transistors MP1 and MP2 are set by the same ground voltage GND, and source terminals of transistors MP1 and MP2 have the same DC voltage V.sub.REP_O=V.sub.DC1=mean of V.sub.OUT. In this embodiment, the reference current I.sub.bias is programmable, and the bias current of the main source follower 102 is set by programming the reference current I.sub.bias provided by the current source 112. To put it simply, the reference current I.sub.bias is one programmable parameter of the push-pull source follower circuit 100.

[0022] Regarding the biasing circuit 106, it includes an error amplifier AMP2, a low-pass filter 116, and a capacitor C2. The error amplifier AMP2 has a first input terminal, a second input terminal, and an output terminal, where the first input terminal is configured to receive an input voltage V.sub.DC2 indicative of a mean voltage, the second input terminal is configured to receive a reference voltage V.sub.REF, and the bias voltage V.sub.CM_N is generated at the output terminal.

[0023] In a first exemplary design of the biasing circuit 106, the low-pass filter 116 is coupled between the first input terminal of the error amplifier AMP2 and the output node N of the push-pull source follower circuit 100, and is configured to apply low-pass filtering to the output voltage V.sub.OUT for generating the input voltage V.sub.DC2. Specifically, the input voltage V.sub.DC2 is indicative of the output mean voltage due to the low-pass filter output being a DC component of the output voltage V.sub.OUT.

[0024] As shown in FIG. 1, the output voltage V.sub.OUT of the push-pull source follower circuit 100 is supplied to a next-stage circuit (denoted by CKT_NXT) 10. Hence, the output voltage V.sub.OUT of the push-pull source follower circuit 100 is received at an input node of the next-stage circuit 10, an internal-node voltage V.sub.INT1 is generated at an internal node of the next-stage circuit 10, and an output voltage V.sub.OUT2 is generated at an output node of the next-stage circuit 10. It should be noted that the next-stage circuit 10 may be any arbitrary circuit depending upon actual design considerations. For example, the next-stage circuit 10 may be an RLC network, a buffer circuit, or an amplifier circuit.

[0025] In a second exemplary design of the biasing circuit 106, the low-pass filter 116 is coupled between the first input terminal of the error amplifier AMP2 and the output node of the next-stage circuit 10, and is configured to apply low-pass filtering to the output voltage V.sub.OUT2 for generating the input voltage V.sub.DC2. Specifically, the input voltage V.sub.DC2 is indicative of an output mean voltage of the next-stage circuit 10 due to the low-pass filter output being a DC component of the output voltage V.sub.OUT2.

[0026] In a third exemplary design of the biasing circuit 106, the low-pass filter 116 is coupled between the first input terminal of the error amplifier AMP2 and the internal node of the next-stage circuit 10, and is configured to apply low-pass filtering to the internal-node voltage V.sub.INT1 for generating the input voltage V.sub.DC2. Specifically, the input voltage V.sub.DC2 is indicative of an internal mean voltage of the next-stage circuit 10 due to the low-pass filter output being a DC component of the internal-node voltage V.sub.INT1.

[0027] The error amplifier AMP2 adaptively adjusts the bias voltage V.sub.CM_N according to an error between the reference voltage V.sub.REF and the input voltage V.sub.DC2. The bias voltage V.sub.CM_N is held by the capacitor C2. Since the drain terminal of the transistor MN2 is coupled to a fixed voltage (i.e., supply voltage VDD), the input voltage V.sub.DC2 (e.g., mean voltage of V.sub.OUT, V.sub.OUT2, Or V.sub.INT1) changes in response to a change of the bias voltage (i.e., gate voltage of transistor MN2) V.sub.CM_N. In other words, the error amplifier AMP2 adaptively adjusts the bias voltage V.sub.CM_N to minimize the error between the reference voltage V.sub.REF and the input voltage V.sub.DC2. Hence, the error amplifier AMP2 will make the input voltage V.sub.DC2 (e. g., mean voltage of V.sub.OUT, V.sub.OUT2, or V.sub.INT1) same as or close to the reference voltage V.sub.REF.

[0028] Since the internal-node voltage V.sub.INT1 and the output voltage V.sub.OUT2 of the next-stage circuit 10 are derived from the output voltage V.sub.OUT of the preceding push-pull source follower circuit 100, the mean of the internal-node voltage V.sub.INT1 and the output voltage V.sub.OUT2 can be set by controlling the output mean voltage of the preceding push-pull source follower circuit 100. In this embodiment, the reference voltage V.sub.REF is programmable, and the output mean voltage of the push-pull source follower circuit 100 is set by programming the reference voltage V.sub.REF provided by a voltage generator (not shown). To put it simply, the reference voltage V.sub.REF is another programmable parameter of the push-pull source follower circuit 100. If the mean of the output voltage V.sub.OUT of the push-pull source follower circuit 100 (i.e., the mean of the input voltage of the next-stage circuit 10) is concerned, the low-pass filter 116 is configured to receive the output voltage V.sub.OUT as its filter input. If the mean of the internal-node voltage V.sub.INT1 of the next-stage circuit 10 is concerned, the low-pass filter 116 is configured to receive the internal-node voltage V.sub.INT1 as its filter input. If the mean of the output voltage V.sub.OUT2 of the next-stage circuit 10 is concerned, the low-pass filter 116 is configured to receive the output voltage V.sub.OUT2 as its filter input.

[0029] Regarding the push-pull source follower circuit 100, the biasing circuit 104 is used to set the bias voltage V.sub.CM_P of the P-type source follower of the main source follower 102, and the biasing circuit 106 is used to set the bias voltage V.sub.CM_N of the N-type source follower of the main source follower 102. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. Alternatively, roles of the biasing circuits 104 and 106 may be swapped.

[0030] FIG. 2 is a diagram illustrating a second push-pull source follower design using the proposed biasing technique according to an embodiment of the present invention. The push-pull source follower circuit 200 is based on a complementary structure, and adopts the proposed biasing technique to independently program a bias current and an output mean voltage. In this embodiment, the push-pull source follower circuit 200 includes a main source follower 202 and a plurality of biasing circuits 204 and 206. The main source follower 202 includes transistors MN2 and MP2, where the transistor MN2 is an NMOS transistor acting as an N-type source follower, and the transistor MP2 is a PMOS transistor acting as a P-type source follower. The transistor MN2 has a gate terminal (which acts as a control terminal), a source terminal (which acts as a first connection terminal), and a drain terminal (which acts as a second connection terminal), where the source terminal is coupled to an output node N of the push-pull source follower circuit 200, and the drain terminal is coupled to a power rail on which a supply voltage VDD is delivered. The transistor MP2 has a gate terminal (which acts as a control terminal), a source terminal (which acts as a first connection terminal, and a drain terminal (which acts as a second connection terminal), where the source terminal is coupled to the output node N of the push-pull source follower circuit 200, and the drain terminal is coupled to a power rail on which a ground voltage GND is delivered.

[0031] The biasing circuit 204 is configured to program a bias current of the main source follower 202 through generating and outputting a bias voltage V.sub.CM_N to the gate terminal of the transistor MN2. The bias voltage V.sub.CM_N may be supplied to the gate terminal of the transistor MN2 through a coupling circuit 208 such as an active coupler or a passive coupler. For example, the coupling circuit 208 may be implemented using a DC level shifter including an AC coupling capacitor and a DC bias resistor, where the AC coupling capacitor passes an AC component of an input voltage V.sub.IN, and the DC bias resistor adds a DC bias (i.e., bias voltage V.sub.CM_N) to the AC component V.sub.IN, thus resulting in a gate voltage (V.sub.IN+V.sub.CM_N) at the gate terminal of the transistor MN2.

[0032] The biasing circuit 206 is configured to program an output mean voltage (i.e., a DC level of an output voltage V.sub.OUT) of the push-pull source follower circuit 200 through generating and outputting a bias voltage V.sub.CM_P to the gate terminal of the transistor MP2. The bias voltage V.sub.CM_P may be supplied to the gate terminal of the transistor MP2 through a coupling circuit 210 such as an active coupler or a passive coupler. For example, the coupling circuit 210 may be implemented using a DC level shifter including an AC coupling capacitor and a DC bias resistor, where the AC coupling capacitor passes an AC component of the input voltage V.sub.IN, and the DC bias resistor adds a DC bias (i.e., bias voltage V.sub.CM_P) to the AC component V.sub.IN, thus resulting in a gate voltage (V.sub.IN+V.sub.CM_P) at the gate terminal of the transistor MP2.

[0033] In this embodiment, the bias current and the output mean voltage are programmed independently. Regarding the biasing circuit 204, it includes a replica source follower 211, a current source 212, a low-pass filter 214, an error amplifier AMP1, and a capacitor C1. The replica source follower 211 corresponds to the transistor MN2 of the main source follower 202, and includes a transistor MN1, where the transistor MN1 is an NMOS transistor acting as an N-type source follower. The transistor MN1 has a gate terminal (which acts as a control terminal), a source terminal (which acts as a first connection terminal), and a drain terminal (which acts as a second connection terminal), where the bias voltage V.sub.CM_N is generated at the gate terminal, and the drain terminal is coupled to the power rail on which the supply voltage VDD is delivered. Specifically, the replica source follower 211 is a replica of the N-type source follower (i.e., transistor MN2) included in the main source follower 202, where an I-V characteristic of the replica source follower 211 may be the same as that of the N-type source follower included in the main source follower 202. In some embodiments of the present invention, the replica source follower 211 (particularly, transistor MN1 of replica source follower 211) may be a scaled version of the N-type source follower in the main source follower 202 (particularly, transistor MN2 of main source follower 202). For example, the transistor MN1 may be a scaled-down version of the transistor MN2 for power saving and area saving. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention.

[0034] The error amplifier AMP1 has a first input terminal, a second input terminal, and an output terminal, where the first input terminal is coupled to the source terminal of the transistor MN1, the second input terminal is configured to receive an input voltage V.sub.DC1 indicative of the output mean voltage, and the output terminal is coupled to the gate terminal of the transistor MN1.

[0035] The low-pass filter 214 is coupled between the second input terminal of the error amplifier AMP1 and the output node N of the push-pull source follower circuit 200, and is configured to apply low-pass filtering to the output voltage V.sub.OUT of the push-pull source follower circuit 200 for generating the input voltage V.sub.DC1. Specifically, the low-pass filter output is a DC component of the output voltage V.sub.OUT.

[0036] The current source 212 is coupled between the first input terminal of the error amplifier AMP1 and the power rail on which the ground voltage GND is delivered, and is configured to provide a reference current I.sub.bias. The reference current I.sub.bias acts as a bias current flowing through the transistor MN1, such that an output voltage V.sub.REP_O of the replica source follower 211 is established at the source terminal of the transistor MN1 under a condition that the bias voltage V.sub.CM_N is applied to the gate terminal of the transistor MN1. The error amplifier AMP1 adaptively adjusts the bias voltage V.sub.CM_N according to an error between the output voltage V.sub.REP_O and the input voltage V.sub.DC1. The bias voltage V.sub.CM_N is held by the capacitor C1. Since the reference current I.sub.bias flowing through the transistor MN1 has a constant current value, the output voltage (i.e., source voltage of transistor MN1) V.sub.REP_O changes in response to a change of the bias voltage (i.e., gate voltage of transistor MN1) V.sub.CM_N. In other words, the error amplifier AMP1 adaptively adjusts the bias voltage V.sub.CM_N to minimize the error between the output voltage V.sub.REP_O and the input voltage V.sub.DC1. Hence, the error amplifier AMP1 will make the output voltage V.sub.REP_O same as or close to the input voltage V.sub.DC1 that is the mean of the output voltage V.sub.OUT.

[0037] Since the replica source follower 211 is a replica (e.g., scaled version) of the N-type source follower of the main source follower 202, a bias current of the main source follower 202 is also a replica (e.g., scaled version) of the reference current I.sub.bias under a condition that gate terminals of transistors MN1 and MN2 are biased by the same bias voltage V.sub.CM_N, drain terminals of transistors MN1 and MN2 are set by the same supply voltage VDD, and source terminals of transistors MN1 and MN2 have the same DC voltage V.sub.REP_O=V.sub.DC1=mean of V.sub.OUT. In this embodiment, the reference current I.sub.bias is programmable, and the bias current of the main source follower 202 is set by programming the reference current I.sub.bias provided by the current source 212. To put it simply, the reference current I.sub.bias is one programmable parameter of the push-pull source follower circuit 200.

[0038] Regarding the biasing circuit 206, it includes an error amplifier AMP2, a low-pass filter 216, and a capacitor C2. The error amplifier AMP2 has a first input terminal, a second input terminal, and an output terminal, where the first input terminal is configured to receive an input voltage V.sub.DC2 indicative of a mean voltage, the second input terminal is configured to receive a reference voltage V.sub.REF, and the bias voltage V.sub.CM_P is generated at the output terminal.

[0039] In a first exemplary design of the biasing circuit 206, the low-pass filter 216 is coupled between the first input terminal of the error amplifier AMP2 and the output node N of the push-pull source follower circuit 200, and is configured to apply low-pass filtering to the output voltage V.sub.OUT for generating the input voltage V.sub.DC2. Specifically, the input voltage V.sub.DC2 is indicative of the output mean voltage due to the low-pass filter output being a DC component of the output voltage V.sub.OUT.

[0040] As shown in FIG. 2, the output voltage V.sub.OUT of the push-pull source follower circuit 200 is supplied to a next-stage circuit (denoted by CKT_NXT) 20. Hence, the output voltage V.sub.OUT of the push-pull source follower circuit 200 is received at an input node of the next-stage circuit 20, an internal-node voltage V.sub.INT1 is generated at an internal node of the next-stage circuit 20, and an output voltage V.sub.OUT2 is generated at an output node of the next-stage circuit 20. It should be noted that the next-stage circuit 20 may be any arbitrary circuit depending upon actual design considerations. For example, the next-stage circuit 20 may be an RLC network, a buffer circuit, or an amplifier circuit.

[0041] In a second exemplary design of the biasing circuit 206, the low-pass filter 216 is coupled between the first input terminal of the error amplifier AMP2 and the output node of the next-stage circuit 20, and is configured to apply low-pass filtering to the output voltage V.sub.OUT2 for generating the input voltage V.sub.DC2. Specifically, the input voltage V.sub.DC2 is indicative of an output mean voltage of the next-stage circuit 20 due to the low-pass filter output being a DC component of the output voltage V.sub.OUT2.

[0042] In a third exemplary design of the biasing circuit 206, the low-pass filter 216 is coupled between the first input terminal of the error amplifier AMP2 and the internal node of the next-stage circuit 20, and is configured to apply low-pass filtering to the internal-node voltage V.sub.INT1 for generating the input voltage V.sub.DC2. Specifically, the input voltage V.sub.DC2 is indicative of an internal mean voltage of the next-stage circuit 20 due to the low-pass filter output being a DC component of the internal-node voltage V.sub.INT1.

[0043] The error amplifier AMP2 adaptively adjusts the bias voltage V.sub.CM_P according to an error between the reference voltage V.sub.REF and the input voltage V.sub.DC2. The bias voltage V.sub.CM_P is held by the capacitor C2. Since the drain terminal of the transistor MN2 is coupled to a fixed voltage (i.e., ground voltage GND), the input voltage V.sub.DC2 (e.g., mean voltage of V.sub.OUT, V.sub.OUT2, or V.sub.INT1) changes in response to a change of the bias voltage (i.e., gate voltage of transistor MP2) V.sub.CM_P. In other words, the error amplifier AMP2 adaptively adjusts the bias voltage V.sub.CM_P to minimize the error between the reference voltage V.sub.REF and the input voltage V.sub.DC2. Hence, the error amplifier AMP2 will make the input voltage V.sub.DC2 (e. g., mean voltage of V.sub.OUT, V.sub.OUT2, or V.sub.INT1) same as or close to the reference voltage V.sub.REF.

[0044] Since the internal-node voltage V.sub.INT1 and the output voltage V.sub.OUT2 of the next-stage circuit 20 are derived from the output voltage V.sub.OUT of the preceding push-pull source follower circuit 200, the mean of the internal-node voltage V.sub.INT1 and the output voltage V.sub.OUT2 can be set by controlling the output mean voltage of the preceding push-pull source follower circuit 200. In this embodiment, the reference voltage V.sub.REF is programmable, and the output mean voltage of the push-pull source follower circuit 200 is set by programming the reference voltage V.sub.REF provided by a voltage generator (not shown). To put it simply, the reference voltage V.sub.REF is another programmable parameter of the push-pull source follower circuit 200. If the mean of the output voltage V.sub.OUT of the push-pull source follower circuit 200 (i.e., the mean of the input voltage of the next-stage circuit 20) is concerned, the low-pass filter 216 is configured to receive the output voltage V.sub.OUT as its filter input. If the mean of the internal-node voltage V.sub.INT1 of the next-stage circuit 20 is concerned, the low-pass filter 216 is configured to receive the internal-node voltage V.sub.INT1 as its filter input. If the mean of the output voltage V.sub.OUT2 of the next-stage circuit 20 is concerned, the low-pass filter 216 is configured to receive the output voltage V.sub.OUT2 as its filter input.

[0045] Regarding the push-pull source follower circuit 100/200, the error amplifier AMP1 of the biasing circuit 104/204 obtains the output mean voltage as the input voltage V.sub.DC1 through the low-pass filter 114/214. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. Alternatively, an output mean voltage referenced by the error amplifier AMP1 of one biasing circuit for biasing current control may be directly set by a reference voltage which is referenced by the error amplifier AMP2 of another biasing circuit for output mean voltage control.

[0046] FIG. 3 is a diagram illustrating a third push-pull source follower design using the proposed biasing technique according to an embodiment of the present invention. The push-pull source follower circuit 300 is based on a complementary structure, and adopts the proposed biasing technique to independently program a bias current and an output mean voltage. In this embodiment, the push-pull source follower circuit 300 includes a main source follower 302 and a plurality of biasing circuits 304 and 306. The main source follower 302 includes transistors MN2 and MP2, where the transistor MN2 is an NMOS transistor acting as an N-type source follower, and the transistor MP2 is a PMOS transistor acting as a P-type source follower. The transistor MN2 has a gate terminal (which acts as a control terminal), a source terminal (which acts as a first connection terminal), and a drain terminal (which acts as a second connection terminal), where the source terminal is coupled to an output node N of the push-pull source follower circuit 300, and the drain terminal is coupled to a power rail on which a supply voltage VDD is delivered. The transistor MP2 has a gate terminal (which acts as a control terminal), a source terminal ((which acts as a first connection terminal, and a drain terminal (which acts as a second connection terminal), where the source terminal is coupled to the output node N of the push-pull source follower circuit 300, and the drain terminal is coupled to a power rail on which a ground voltage GND is delivered.

[0047] The biasing circuit 304 is configured to program a bias current of the main source follower 302 through generating and outputting a bias voltage V.sub.CM_P to the gate terminal of the transistor MP2. The bias voltage V.sub.CM_P may be supplied to the gate terminal of the transistor MP2 through a coupling circuit 308 such as an active coupler or a passive coupler. For example, the coupling circuit 308 may be implemented using a DC level shifter including an AC coupling capacitor and a DC bias resistor, where the AC coupling capacitor passes an AC component of an input voltage V.sub.IN, and the DC bias resistor adds a DC bias (i.e., bias voltage V.sub.CM_P) to the AC component V.sub.IN, thus resulting in a gate voltage (V.sub.IN+V.sub.CM_P) at the gate terminal of the transistor MP2.

[0048] The biasing circuit 306 is configured to program an output mean voltage (i.e., a DC level of an output voltage V.sub.OUT) of the push-pull source follower circuit 300 through generating and outputting a bias voltage V.sub.CM_N to the gate terminal of the transistor MN2. The bias voltage V.sub.CM_N may be supplied to the gate terminal of the transistor MN2 through a coupling circuit 310 such as an active coupler or a passive coupler. For example, the coupling circuit 310 may be implemented using a DC level shifter including an AC coupling capacitor and a DC bias resistor, where the AC coupling capacitor passes an AC component of the input voltage V.sub.IN, and the DC bias resistor adds a DC bias (i.e., bias voltage V.sub.CM_N) to the AC component V.sub.IN, thus resulting in a gate voltage (V.sub.IN+V.sub.CM_N) at the gate terminal of the transistor MN2.

[0049] In this embodiment, the bias current and the output mean voltage are programmed independently. Regarding the biasing circuit 306, it includes an error amplifier AMP2, a low-pass filter 314, and a capacitor C2. The error amplifier AMP2 has a first input terminal, a second input terminal, and an output terminal, where the first input terminal is configured to receive an input voltage V.sub.DC2 indicative of a mean voltage, the second input terminal is configured to receive a reference voltage V.sub.REF, and the bias voltage V.sub.CM_N is generated at the output terminal. The major difference between the biasing circuits 106 and 306 is that a source of the input voltage V.sub.DC2 has only a single choice being the output voltage V.sub.OUT of the push-pull source follower circuit 300 since the reference voltage V.sub.REF is also used by the biasing circuit 304 for indicating the output mean voltage of the push-pull source follower circuit 300. As shown in FIG. 3, the low-pass filter 314 is coupled between the first input terminal of the error amplifier AMP2 and the output node N of the push-pull source follower circuit 300, and is configured to apply low-pass filtering to the output voltage V.sub.OUT for generating the input voltage V.sub.DC2. Specifically, the input voltage V.sub.DC2 is indicative of the output mean voltage due to the low-pass filter output being a DC component of the output voltage V.sub.OUT.

[0050] The error amplifier AMP2 adaptively adjusts the bias voltage V.sub.CM_N according to an error between the reference voltage V.sub.REF and the input voltage V.sub.DC2. The bias voltage V.sub.CM_N is held by the capacitor C2. Since the drain terminal of the transistor MN2 is coupled to a fixed voltage (i.e., supply voltage VDD), the input voltage V.sub.DC2 (e.g., mean voltage of V.sub.OUT) changes in response to a change of the bias voltage (i.e., gate voltage of transistor MN2) V.sub.CM_N. In other words, the error amplifier AMP2 adaptively adjusts the bias voltage V.sub.CM_N to minimize the error between the reference voltage V.sub.REF and the input voltage V.sub.DC2. Hence, the error amplifier AMP2 will make the input voltage V.sub.DC2 (e.g., mean voltage of V.sub.OUT) same as or close to the reference voltage V.sub.REF. In this embodiment, the reference voltage V.sub.REF is programmable, and the output mean voltage of the push-pull source follower circuit 300 is set by programming the reference voltage V.sub.REF provided by a voltage generator (not shown). To put it simply, the reference voltage V.sub.REF is one programmable parameter of the push-pull source follower circuit 300.

[0051] Regarding the biasing circuit 304, it includes a replica source follower 311, a current source 312, an error amplifier AMP1, and a capacitor C1. The replica source follower 311 corresponds to the transistor MP2 of the main source follower 302, and includes a transistor MP1, where the transistor MP1 is a PMOS transistor acting as a P-type source follower. The transistor MP1 has a gate terminal (which acts as a control terminal), a source terminal (which acts as a first connection terminal), and a drain terminal (which acts as a second connection terminal), where the bias voltage V.sub.CM_P is generated at the gate terminal, and the drain terminal is coupled to the power rail on which the ground voltage GND is delivered. Specifically, the replica source follower 311 is a replica of the P-type source follower (i.e., transistor MP2) included in the main source follower 302, where an I-V characteristic of the replica source follower 311 may be the same as that of the P-type source follower included in the main source follower 302. In some embodiments of the present invention, the replica source follower 311 (particularly, transistor MP1 of replica source follower 311) may be a scaled version of the P-type source follower in the main source follower 302 (particularly, transistor MP2 of main source follower 302). For example, the transistor MP1 may be a scaled-down version of the transistor MP2 for power saving and area saving. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention.

[0052] The error amplifier AMP1 has a first input terminal, a second input terminal, and an output terminal. The major difference between the biasing circuits 104 and 304 is that the biasing circuit 304 has no low-pass filter coupled between the second input terminal of the error amplifier AMP1 and the output node N of the push-pull source follower circuit 300. As shown in FIG. 3, the first input terminal of the error amplifier AMP1 is coupled to the source terminal of the transistor MP1, the second input terminal is configured to receive the same reference voltage V.sub.REF used by the error amplifier AMP2, and the output terminal of the error amplifier AMP1 is coupled to the gate terminal of the transistor MP1.

[0053] The current source 312 is coupled between the first input terminal of the error amplifier AMP1 and the power rail on which the supply voltage VDD is delivered, and is configured to provide a reference current I.sub.bias. The reference current I.sub.bias acts as a bias current flowing through the transistor MP1, such that an output voltage V.sub.REP_O of the replica source follower 311 is established at the source terminal of the transistor MP1 under a condition that the bias voltage V.sub.CM_P is applied to the gate terminal of the transistor MP1. The error amplifier AMP1 adaptively adjusts the bias voltage V.sub.CM_P according to an error between the output voltage V.sub.REP_O and the reference voltage V.sub.REF (which is a target level of the output mean voltage). The bias voltage V.sub.CM_P is held by the capacitor C1. Since the reference current I.sub.bias flowing through the transistor MP1 has a constant current value, the output voltage (i.e., source voltage of transistor MP1) V.sub.REP_O changes in response to a change of the bias voltage (i.e., gate voltage of transistor MP1) V.sub.CM_P. In other words, the error amplifier AMP1 adaptively adjusts the bias voltage V.sub.CM_P to minimize the error between the output voltage V.sub.REP_O and the reference voltage V.sub.REF. Hence, the error amplifier AMP1 will make the output voltage V.sub.REP_O same as or close to the reference voltage V.sub.REF.

[0054] Since the replica source follower 311 is a replica (e.g., scaled version) of the P-type source follower of the main source follower 302, a bias current of the main source follower 302 is also a replica (e.g., scaled version) of the reference current I.sub.bias under a condition that gate terminals of transistors MP1 and MP2 are biased by the same bias voltage V.sub.CM_P, drain terminals of transistors MP1 and MP2 are set by the same ground voltage GND, and source terminals of transistors MP1 and MP2 have the same DC voltage V.sub.REP_O=V.sub.REF=mean of V.sub.OUT. In this embodiment, the reference current I.sub.bias is programmable, and the bias current of the main source follower 302 is set by programming the reference current I.sub.bias provided by the current source 312. To put it simply, the reference current I.sub.bias is another programmable parameter of the push-pull source follower circuit 300.

[0055] Regarding the push-pull source follower circuit 300, the biasing circuit 304 is used to set the bias voltage V.sub.CM_P of the P-type source follower of the main source follower 302, and the biasing circuit 306 is used to set the bias voltage V.sub.CM_N of the N-type source follower of the main source follower 302. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. Alternatively, roles of the biasing circuits 304 and 306 may be swapped.

[0056] FIG. 4 is a diagram illustrating a fourth push-pull source follower design using the proposed biasing technique according to an embodiment of the present invention. The push-pull source follower circuit 400 is based on a complementary structure, and adopts the proposed biasing technique to independently program a bias current and an output mean voltage. In this embodiment, the push-pull source follower circuit 400 includes a main source follower 402 and a plurality of biasing circuits 404 and 406. The main source follower 402 includes transistors MN2 and MP2, where the transistor MN2 is an NMOS transistor acting as an N-type source follower, and the transistor MP2 is a PMOS transistor acting as a P-type source follower. The transistor MN2 has a gate terminal (which acts as a control terminal), a source terminal (which acts as a first connection terminal), and a drain terminal (which acts as a second connection terminal), where the source terminal is coupled to an output node N of the push-pull source follower circuit 400, and the drain terminal is coupled to a power rail on which a supply voltage VDD is delivered. The transistor MP2 has a gate terminal (which acts as a control terminal), a source terminal (which acts as a first connection terminal, and a drain terminal (which acts as a second connection terminal), where the source terminal is coupled to the output node N of the push-pull source follower circuit 400, and the drain terminal is coupled to a power rail on which a ground voltage GND is delivered.

[0057] The biasing circuit 404 is configured to program a bias current of the main source follower 402 through generating and outputting a bias voltage V.sub.CM_N to the gate terminal of the transistor MN2. The bias voltage V.sub.CM_N may be supplied to the gate terminal of the transistor MN2 through a coupling circuit 408 such as an active coupler or a passive coupler. For example, the coupling circuit 408 may be implemented using a DC level shifter including an AC coupling capacitor and a DC bias resistor, where the AC coupling capacitor passes an AC component of an input voltage V.sub.IN, and the DC bias resistor adds a DC bias (i.e., bias voltage V.sub.CM_N) to the AC component V.sub.IN, thus resulting in a gate voltage (V.sub.IN+V.sub.CM_N) at the gate terminal of the transistor MN2.

[0058] The biasing circuit 306 is configured to program an output mean voltage (i.e., a DC level of an output voltage V.sub.OUT) of the push-pull source follower circuit 400 through generating and outputting a bias voltage V.sub.CM_P to the gate terminal of the transistor MP2. The bias voltage V.sub.CM_P may be supplied to the gate terminal of the transistor MP2 through a coupling circuit 410 such as an active coupler or a passive coupler. For example, the coupling circuit 410 may be implemented using a DC level shifter including an AC coupling capacitor and a DC bias resistor, where the AC coupling capacitor passes an AC component of the input voltage V.sub.IN, and the DC bias resistor adds a DC bias (i.e., bias voltage V.sub.CM_P) to the AC component V.sub.IN, thus resulting in a gate voltage (V.sub.IN+V.sub.CM_P) at the gate terminal of the transistor MP2.

[0059] In this embodiment, the bias current and the output mean voltage are programmed independently. Regarding the biasing circuit 406, it includes an error amplifier AMP2, a low-pass filter 414, and a capacitor C2. The error amplifier AMP2 has a first input terminal, a second input terminal, and an output terminal, where the first input terminal is configured to receive an input voltage V.sub.DC2 indicative of a mean voltage, the second input terminal is configured to receive a reference voltage V.sub.REF, and the bias voltage V.sub.CM_P is generated at the output terminal. The major difference between the biasing circuits 106 and 406 is that a source of the input voltage V.sub.DC2 has only a single choice being the output voltage V.sub.OUT of the push-pull source follower circuit 400 since the reference voltage V.sub.REF is also used by the biasing circuit 404 for indicating the output mean voltage of the push-pull source follower circuit 400. As shown in FIG. 4, the low-pass filter 414 is coupled between the first input terminal of the error amplifier AMP2 and the output node N of the push-pull source follower circuit 400, and is configured to apply low-pass filtering to the output voltage V.sub.OUT for generating the input voltage V.sub.DC2. Specifically, the input voltage V.sub.DC2 is indicative of the output mean voltage due to the low-pass filter output being a DC component of the output voltage V.sub.OUT.

[0060] The error amplifier AMP2 adaptively adjusts the bias voltage V.sub.CM_P according to an error between the reference voltage V.sub.REF and the input voltage V.sub.DC2. The bias voltage V.sub.CM_P is held by the capacitor C2. Since the drain terminal of the transistor MP2 is coupled to a fixed voltage (i.e., ground voltage GND), the input voltage V.sub.DC2 (e.g., mean voltage of V.sub.OUT) changes in response to a change of the bias voltage (i.e., gate voltage of transistor MP2) V.sub.CM_P. In other words, the error amplifier AMP2 adaptively adjusts the bias voltage V.sub.CM_P to minimize the error between the reference voltage V.sub.REF and the input voltage V.sub.DC2. Hence, the error amplifier AMP2 will make the input voltage V.sub.DC2 (e.g., mean voltage of V.sub.OUT) same as or close to the reference voltage V.sub.REF. In this embodiment, the reference voltage V.sub.REF is programmable, and the output mean voltage of the push-pull source follower circuit 400 is set by programming the reference voltage V.sub.REF provided by a voltage generator (not shown). To put it simply, the reference voltage V.sub.REF is one programmable parameter of the push-pull source follower circuit 400.

[0061] Regarding the biasing circuit 404, it includes a replica source follower 411, a current source 412, an error amplifier AMP1, and a capacitor C1. The replica source follower 411 corresponds to the transistor MN2 of the main source follower 402, and includes a transistor MN1, where the transistor MN1 is an NMOS transistor acting as an N-type source follower. The transistor MN1 has a gate terminal (which acts as a control terminal), a source terminal (which acts as a first connection terminal), and a drain terminal (which acts as a second connection terminal), where the bias voltage V.sub.CM_N is generated at the gate terminal, and the drain terminal is coupled to the power rail on which the supply voltage VDD is delivered. Specifically, the replica source follower 411 is a replica of the N-type source follower (i.e., transistor MN2) included in the main source follower 402, where an I-V characteristic of the replica source follower 411 may be the same as that of the N-type source follower included in the main source follower 402. In some embodiments of the present invention, the replica source follower 411 (particularly, transistor MN1 of replica source follower 411) may be a scaled version of the N-type source follower in the main source follower 402 (particularly, transistor MN2 of main source follower 402). For example, the transistor MN1 may be a scaled-down version of the transistor MN2 for power saving and area saving. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention.

[0062] The error amplifier AMP1 has a first input terminal, a second input terminal, and an output terminal. The major difference between the biasing circuits 104 and 404 is that the biasing circuit 404 has no low-pass filter coupled between the second input terminal of the error amplifier AMP1 and the output node N of the push-pull source follower circuit 400. As shown in FIG. 4, the first input terminal of the error amplifier AMP1 is coupled to the source terminal of the transistor MN1, the second input terminal is configured to receive the same reference voltage V.sub.REF used by the error amplifier AMP2, and the output terminal of the error amplifier AMP1 is coupled to the gate terminal of the transistor MN1.

[0063] The current source 412 is coupled between the first input terminal of the error amplifier AMP1 and the power rail on which the ground voltage GND is delivered, and is configured to provide a reference current I.sub.bias. The reference current I.sub.bias acts as a bias current flowing through the transistor MN1, such that an output voltage V.sub.REP_O of the replica source follower 411 is established at the source terminal of the transistor MN1 under a condition that the bias voltage V.sub.CM_N is applied to the gate terminal of the transistor MN1. The error amplifier AMP1 adaptively adjusts the bias voltage V.sub.CM_N according to an error between the output voltage V.sub.REP_O and the reference voltage V.sub.REF (which is a target level of the output mean voltage). The bias voltage V.sub.CM_N is held by the capacitor C1. Since the reference current I.sub.bias flowing through the transistor MN1 has a constant current value, the output voltage (i.e., source voltage of transistor MN1) V.sub.REP_O changes in response to a change of the bias voltage (i.e., gate voltage of transistor MN1) V.sub.CM_N. In other words, the error amplifier AMP1 adaptively adjusts the bias voltage V.sub.CM_N to minimize the error between the output voltage V.sub.REP_O and the reference voltage V.sub.REF. Hence, the error amplifier AMP1 will make the output voltage V.sub.REP_O same as or close to the reference voltage V.sub.REF.

[0064] Since the replica source follower 411 is a replica (e.g., scaled version) of the N-type source follower of the main source follower 402, a bias current of the main source follower 402 is also a replica (e.g., scaled version) of the reference current I.sub.bias under a condition that gate terminals of transistors MN1 and MN2 are biased by the same bias voltage V.sub.CM_N, drain terminals of transistors MN1 and MN2 are set by the same supply voltage VDD, and source terminals of transistors MN1 and MN2 have the same DC voltage V.sub.REP_O=V.sub.REF=mean of V.sub.OUT. In this embodiment, the reference current I.sub.bias is programmable, and the bias current of the main source follower 402 is set by programming the reference current I.sub.bias provided by the current source 412. To put it simply, the reference current I.sub.bias is another programmable parameter of the push-pull source follower circuit 400.

[0065] Regarding the push-pull source follower circuit 300/400, an output mean voltage referenced by the error amplifier AMP1 of one biasing circuit 304/404 for biasing current control is directly set by a reference voltage V.sub.REF which is referenced by the error amplifier AMP2 of another biasing circuit 306/406 for output mean voltage control. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. Alternatively, an output mean voltage referenced by the error amplifier AMP1 of one biasing circuit for biasing current control may be directly set by a reference voltage V.sub.REF which is supplied to a replica next-stage circuit for creating another reference voltage referenced by the error amplifier AMP2 of another biasing circuit for output mean voltage control.

[0066] FIG. 5 is a diagram illustrating a fifth push-pull source follower design using the proposed biasing technique according to an embodiment of the present invention. The push-pull source follower circuit 500 is based on a complementary structure, and adopts the proposed biasing technique to independently program a bias current and an output mean voltage. In this embodiment, the push-pull source follower circuit 500 includes a main source follower 502 and a plurality of biasing circuits 504 and 506. The main source follower 502 includes transistors MN2 and MP2, where the transistor MN2 is an NMOS transistor acting as an N-type source follower, and the transistor MP2 is a PMOS transistor acting as a P-type source follower. The transistor MN2 has a gate terminal (which acts as a control terminal), a source terminal (which acts as a first connection terminal), and a drain terminal (which acts as a second connection terminal), where the source terminal is coupled to an output node N of the push-pull source follower circuit 500, and the drain terminal is coupled to a power rail on which a supply voltage VDD is delivered. The transistor MP2 has a gate terminal (which acts as a control terminal), a source terminal (which acts as a first connection terminal, and a drain terminal (which acts as a second connection terminal), where the source terminal is coupled to the output node N of the push-pull source follower circuit 500, and the drain terminal is coupled to a power rail on which a ground voltage GND is delivered.

[0067] The biasing circuit 504 is configured to program a bias current of the main source follower 502 through generating and outputting a bias voltage V.sub.CM_P to the gate terminal of the transistor MP2. The bias voltage V.sub.CM_P may be supplied to the gate terminal of the transistor MP2 through a coupling circuit 508 such as an active coupler or a passive coupler. For example, the coupling circuit 508 may be implemented using a DC level shifter including an AC coupling capacitor and a DC bias resistor, where the AC coupling capacitor passes an AC component of an input voltage V.sub.IN, and the DC bias resistor adds a DC bias (i.e., bias voltage V.sub.CM_P) to the AC component V.sub.IN, thus resulting in a gate voltage (V.sub.IN+V.sub.CM_P) at the gate terminal of the transistor MP2.

[0068] The biasing circuit 506 is configured to program an output mean voltage (i.e., a DC level of an output voltage V.sub.OUT) of the push-pull source follower circuit 500 through generating and outputting a bias voltage V.sub.CM_N to the gate terminal of the transistor MN2. The bias voltage V.sub.CM_N may be supplied to the gate terminal of the transistor MN2 through a coupling circuit 510 such as an active coupler or a passive coupler. For example, the coupling circuit 510 may be implemented using a DC level shifter including an AC coupling capacitor and a DC bias resistor, where the AC coupling capacitor passes an AC component of the input voltage V.sub.IN, and the DC bias resistor adds a DC bias (i.e., bias voltage V.sub.CM_N) to the AC component V.sub.IN, thus resulting in a gate voltage (V.sub.IN+V.sub.CM_N) at the gate terminal of the transistor MN2.

[0069] As shown in FIG. 5, the output voltage V.sub.OUT of the push-pull source follower circuit 500 is supplied to a next-stage circuit (denoted by CKT_NXT) 10. Hence, the output voltage V.sub.OUT of the push-pull source follower circuit 500 is received at an input node of the next-stage circuit 10, an internal-node voltage V.sub.INT1 is generated at an internal node of the next-stage circuit 10, and an output voltage V.sub.OUT2 is generated at an output node of the next-stage circuit 10. It should be noted that the next-stage circuit 10 may be any arbitrary circuit depending upon actual design considerations. For example, the next-stage circuit 10 may be an RLC network, a buffer circuit, or an amplifier circuit.

[0070] In addition, a reference voltage V.sub.REF used by an error amplifier AMP1 is supplied to a replica next-stage circuit (denoted by replica CKT_NXT) 516. Hence, the reference voltage V.sub.REF is received at an input node of the replica next-stage circuit 516, an internal-node voltage V.sub.REF_INT1 is generated at an internal node of the replica next-stage circuit 516, and an output voltage V.sub.REF_OUT2 is generated at an output node of the replica next-stage circuit 516. It should be noted that a voltage-to-voltage (V-V) characteristic between V.sub.OUT and V.sub.OUT2 is the same as that between V.sub.REF and V.sub.REF_OUT2, and the V-V characteristic between V.sub.OUT and V.sub.INT1 is the same as that between V.sub.REF and V.sub.REF_INT1.

[0071] In this embodiment, the bias current and the output mean voltage are programmed independently. Regarding the biasing circuit 506, it includes an error amplifier AMP2, a low-pass filter 514, the replica next-stage circuit 516, and a capacitor C2. The replica next-stage circuit 516 corresponds to the next-stage circuit 10. Specifically, the replica next-stage circuit 516 is a replica of the next-stage circuit 10, where the V-V characteristic of the replica next-stage circuit 516 may be the same as that of the next-stage circuit 10. The error amplifier AMP2 has a first input terminal, a second input terminal, and an output terminal, where the first input terminal is configured to receive an input voltage V.sub.DC2 indicative of a mean voltage, the second input terminal is configured to receive a reference voltage V.sub.REF2, and the bias voltage V.sub.CM_N is generated at the output terminal. The major difference between the biasing circuits 306 and 506 is that the reference voltage V.sub.REF2 is provided from the replica next-stage circuit 516.

[0072] In a first exemplary design of the biasing circuit 506, the reference voltage V.sub.REF2 is set by the output voltage V.sub.REF_OUT2 generated at the output node of the replica next-stage circuit 516; and the low-pass filter 514 is coupled between the first input terminal of the error amplifier AMP2 and the output node of the next-stage circuit 10, and is configured to apply low-pass filtering to the output voltage V.sub.OUT2 for generating the input voltage V.sub.DC2. Specifically, the input voltage V.sub.DC2 is indicative of an output mean voltage of the next-stage circuit 10 due to the low-pass filter output being a DC component of the output voltage V.sub.OUT2.

[0073] In a second exemplary design of the biasing circuit 506, the reference voltage V.sub.REF2 is set by the internal-node voltage V.sub.REF_INT1 generated at the internal node of the replica next-stage circuit 516; and the low-pass filter 514 is coupled between the first input terminal of the error amplifier AMP2 and the internal node of the next-stage circuit 10, and is configured to apply low-pass filtering to the internal-node voltage V.sub.INT1 for generating the input voltage V.sub.DC2. Specifically, the input voltage V.sub.DC2 is indicative of an internal mean voltage of the next-stage circuit 10 due to the low-pass filter output being a DC component of the internal-node voltage V.sub.INT1.

[0074] The error amplifier AMP2 adaptively adjusts the bias voltage V.sub.CM_N according to an error between the reference voltage V.sub.REF2 and the input voltage V.sub.DC2. The bias voltage V.sub.CM_N is held by the capacitor C2. Since the drain terminal of the transistor MN2 is coupled to a fixed voltage (i.e., supply voltage VDD), the input voltage V.sub.DC2 (e. g., mean voltage of V.sub.OUT2 or V.sub.INT1) changes in response to a change of the bias voltage (i.e., gate voltage of transistor MN2) V.sub.CM_N. In other words, the error amplifier AMP2 adaptively adjusts the bias voltage V.sub.CM_N to minimize the error between the reference voltage V.sub.REF2 and the input voltage V.sub.DC2. Hence, the error amplifier AMP2 will make the input voltage V.sub.DC2 (e.g., mean voltage of V.sub.OUT2 Or V.sub.INT1) same as or close to the reference voltage V.sub.REF2 (e. g., V.sub.REF_OUT2 OF V.sub.REF_INT1). Since the next-stage circuit 10 and the replica next-stage circuit 516 have the same V-V characteristic, the mean of the output voltage V.sub.OUT is the same as or close to the reference voltage V.sub.REF when the input voltage V.sub.DC2 (e. g., mean voltage of V.sub.OUT2 or V.sub.INT1) is the same as or close to the reference voltage V.sub.REF2 (e. g., V.sub.REF_OUT2 or V.sub.REF_INT1). In other words, the bias voltage V.sub.CM_N is adaptively adjusted to make the output mean voltage of the push-pull source follower circuit 500 equal to the reference voltage V.sub.REF. In this embodiment, the reference voltage V.sub.REF is programmable, and the output mean voltage of the push-pull source follower circuit 500 is set by programming the reference voltage V.sub.REF provided by a voltage generator (not shown). To put it simply, the reference voltage V.sub.REF is one programmable parameter of the push-pull source follower circuit 500.

[0075] Regarding the biasing circuit 504, it includes a replica source follower 511, a current source 512, the error amplifier AMP1, and a capacitor C1. The replica source follower 511 corresponds to the transistor MP2 of the main source follower 502, and includes a transistor MP1, where the transistor MP1 is a PMOS transistor acting as a P-type source follower. The transistor MP1 has a gate terminal (which acts as a control terminal), a source terminal (which acts as a first connection terminal), and a drain terminal (which acts as a second connection terminal), where the bias voltage V.sub.CM_P is generated at the gate terminal, and the drain terminal is coupled to the power rail on which the ground voltage GND is delivered. Specifically, the replica source follower 511 is a replica of the P-type source follower (i.e., transistor MP2) included in the main source follower 502, where an I-V characteristic of the replica source follower 511 may be the same as that of the P-type source follower included in the main source follower 502. In some embodiments of the present invention, the replica source follower 511 (particularly, transistor MP1 of replica source follower 511) may be a scaled version of the P-type source follower in the main source follower 502 (particularly, transistor MP2 of main source follower 502). For example, the transistor MP1 may be a scaled-down version of the transistor MP2 for power saving and area saving. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention.

[0076] The error amplifier AMP1 has a first input terminal, a second input terminal, and an output terminal, where the first input terminal is coupled to the source terminal of the transistor MP1, the second input terminal is configured to receive the reference voltage V.sub.REF (which is a target level of the output mean voltage), and the output terminal is coupled to the gate terminal of the transistor MP1.

[0077] The current source 512 is coupled between the first input terminal of the error amplifier AMP1 and the power rail on which the supply voltage VDD is delivered, and is configured to provide a reference current I.sub.bias. The reference current I.sub.bias acts as a bias current flowing through the transistor MP1, such that an output voltage V.sub.REP_O of the replica source follower 511 is established at the source terminal of the transistor MP1 under a condition that the bias voltage V.sub.CM_P is applied to the gate terminal of the transistor MP1. The error amplifier AMP1 adaptively adjusts the bias voltage V.sub.CM_P according to an error between the output voltage V.sub.REP_O and the reference voltage V.sub.REF. The bias voltage V.sub.CM_P is held by the capacitor C1. Since the reference current I.sub.bias flowing through the transistor MP1 has a constant current value, the output voltage (i.e., source voltage of transistor MP1) V.sub.REP_O changes in response to a change of the bias voltage (i.e., gate voltage of transistor MP1) V.sub.CM_P. In other words, the error amplifier AMP1 adaptively adjusts the bias voltage V.sub.CM_P to minimize the error between the output voltage V.sub.REP_O and the reference voltage V.sub.REF. Hence, the error amplifier AMP1 will make the output voltage V.sub.REP_O same as or close to the reference voltage V.sub.REF.

[0078] Since the replica source follower 511 is a replica (e.g., scaled version) of the P-type source follower of the main source follower 502, a bias current of the main source follower 502 is also a replica (e.g., scaled version) of the reference current I.sub.bias under a condition that gate terminals of transistors MP1 and MP2 are biased by the same bias voltage V.sub.CM_P, drain terminals of transistors MP1 and MP2 are set by the same ground voltage GND, and source terminals of transistors MP1 and MP2 have the same DC voltage V.sub.REP_O=V.sub.REF=mean of V.sub.OUT. In this embodiment, the reference current I.sub.bias is programmable, and the bias current of the main source follower 502 is set by programming the reference current I.sub.bias provided by the current source 512. To put it simply, the reference current I.sub.bias is another programmable parameter of the push-pull source follower circuit 500.

[0079] Regarding the push-pull source follower circuit 500, the biasing circuit 504 is used to set the bias voltage V.sub.CM_P of the P-type source follower of the main source follower 502, and the biasing circuit 506 is used to set the bias voltage V.sub.CM_N of the N-type source follower of the main source follower 502. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. Alternatively, roles of the biasing circuits 504 and 506 may be swapped.

[0080] FIG. 6 is a diagram illustrating a sixth push-pull source follower design using the proposed biasing technique according to an embodiment of the present invention. The push-pull source follower circuit 600 is based on a complementary structure, and adopts the proposed biasing technique to independently program a bias current and an output mean voltage. In this embodiment, the push-pull source follower circuit 600 includes a main source follower 602 and a plurality of biasing circuits 604 and 606. The main source follower 602 includes transistors MN2 and MP2, where the transistor MN2 is an NMOS transistor acting as an N-type source follower, and the transistor MP2 is a PMOS transistor acting as a P-type source follower. The transistor MN2 has a gate terminal (which acts as a control terminal), a source terminal (which acts as a first connection terminal), and a drain terminal (which acts as a second connection terminal), where the source terminal is coupled to an output node N of the push-pull source follower circuit 600, and the drain terminal is coupled to a power rail on which a supply voltage VDD is delivered. The transistor MP2 has a gate terminal (which acts as a control terminal), a source terminal (which acts as a first connection terminal, and a drain terminal (which acts as a second connection terminal), where the source terminal is coupled to the output node N of the push-pull source follower circuit 600, and the drain terminal is coupled to a power rail on which a ground voltage GND is delivered.

[0081] The biasing circuit 604 is configured to program a bias current of the main source follower 602 through generating and outputting a bias voltage V.sub.CM_N to the gate terminal of the transistor MN2. The bias voltage V.sub.CM_N may be supplied to the gate terminal of the transistor MN2 through a coupling circuit 608 such as an active coupler or a passive coupler. For example, the coupling circuit 608 may be implemented using a DC level shifter including an AC coupling capacitor and a DC bias resistor, where the AC coupling capacitor passes an AC component of an input voltage V.sub.IN, and the DC bias resistor adds a DC bias (i.e., bias voltage V.sub.CM_N) to the AC component V.sub.IN, thus resulting in a gate voltage (V.sub.IN+V.sub.CM_N) at the gate terminal of the transistor MN2.

[0082] The biasing circuit 606 is configured to program an output mean voltage (i.e., a DC level of an output voltage V.sub.OUT) of the push-pull source follower circuit 600 through generating and outputting a bias voltage V.sub.CM_P to the gate terminal of the transistor MP2. The bias voltage V.sub.CM_P may be supplied to the gate terminal of the transistor MP2 through a coupling circuit 610 such as an active coupler or a passive coupler. For example, the coupling circuit 610 may be implemented using a DC level shifter including an AC coupling capacitor and a DC bias resistor, where the AC coupling capacitor passes an AC component of the input voltage V.sub.IN, and the DC bias resistor adds a DC bias (i.e., bias voltage V.sub.CM_P) to the AC component V.sub.IN, thus resulting in a gate voltage (V.sub.IN+V.sub.CM_P) at the gate terminal of the transistor MP2.

[0083] As shown in FIG. 6, the output voltage V.sub.OUT of the push-pull source follower circuit 600 is supplied to a next-stage circuit (denoted by CKT_NXT) 20. Hence, the output voltage V.sub.OUT of the push-pull source follower circuit 600 is received at an input node of the next-stage circuit 20, an internal-node voltage V.sub.INT1 is generated at an internal node of the next-stage circuit 20, and an output voltage V.sub.OUT2 is generated at an output node of the next-stage circuit 20. It should be noted that the next-stage circuit 20 may be any arbitrary circuit depending upon actual design considerations. For example, the next-stage circuit 20 may be an RLC network, a buffer circuit, or an amplifier circuit.

[0084] In addition, a reference voltage V.sub.REF used by an error amplifier AMP1 is supplied to a replica next-stage circuit (denoted by replica CKT_NXT) 616. Hence, the reference voltage V.sub.REF is received at an input node of the replica next-stage circuit 616, an internal-node voltage V.sub.REF_INT1 is generated at an internal node of the replica next-stage circuit 616, and an output voltage V.sub.REF_OUT2 is generated at an output node of the replica next-stage circuit 616. It should be noted that the V-V characteristic between V.sub.OUT and V.sub.OUT2 is the same as that between V.sub.REF and V.sub.REF_OUT2, and the V-V characteristic between V.sub.OUT and V.sub.INT1 is the same as that between V.sub.REF and V.sub.REF_INT1.

[0085] In this embodiment, the bias current and the output mean voltage are programmed independently. Regarding the biasing circuit 606, it includes an error amplifier AMP2, a low-pass filter 614, the replica next-stage circuit 616, and a capacitor C2. The replica next-stage circuit 616 corresponds to the next-stage circuit 20. Specifically, the replica next-stage circuit 616 is a replica of the next-stage circuit 20, where the V-V characteristic of the replica next-stage circuit 616 may be the same as that of the next-stage circuit 20. The error amplifier AMP2 has a first input terminal, a second input terminal, and an output terminal, where the first input terminal is configured to receive an input voltage V.sub.DC2 indicative of a mean voltage, the second input terminal is configured to receive a reference voltage V.sub.REF2, and the bias voltage V.sub.CM_P is generated at the output terminal. The major difference between the biasing circuits 406 and 606 is that the reference voltage V.sub.REF2 is provided from the replica next-stage circuit 616.

[0086] In a first exemplary design of the biasing circuit 606, the reference voltage V.sub.REF2 is set by the output voltage V.sub.REF_OUT2 generated at the output node of the replica next-stage circuit 616; and the low-pass filter 614 is coupled between the first input terminal of the error amplifier AMP2 and the output node of the next-stage circuit 20, and is configured to apply low-pass filtering to the output voltage V.sub.OUT2 for generating the input voltage V.sub.DC2. Specifically, the input voltage V.sub.DC2 is indicative of an output mean voltage of the next-stage circuit 20 due to the low-pass filter output being a DC component of the output voltage V.sub.OUT2.

[0087] In a second exemplary design of the biasing circuit 606, the reference voltage V.sub.REF2 is set by the internal-node voltage V.sub.REF_INT1 generated at the internal node of the replica next-stage circuit 616; and the low-pass filter 614 is coupled between the first input terminal of the error amplifier AMP2 and the internal node of the next-stage circuit 20, and is configured to apply low-pass filtering to the internal-node voltage V.sub.INT1 for generating the input voltage V.sub.DC2. Specifically, the input voltage V.sub.DC2 is indicative of an internal mean voltage of the next-stage circuit 20 due to the low-pass filter output being a DC component of the internal-node voltage V.sub.INT1.

[0088] The error amplifier AMP2 adaptively adjusts the bias voltage V.sub.CM_P according to an error between the reference voltage V.sub.REF2 and the input voltage V.sub.DC2. The bias voltage V.sub.CM_P is held by the capacitor C2. Since the drain terminal of the transistor MP2 is coupled to a fixed voltage (i.e., ground voltage GND), the input voltage V.sub.DC2 (e.g., mean voltage of V.sub.OUT2 Or V.sub.INT1) changes in response to a change of the bias voltage (i.e., gate voltage of transistor MP2) V.sub.CM_P. In other words, the error amplifier AMP2 adaptively adjusts the bias voltage V.sub.CM_P to minimize the error between the reference voltage V.sub.REF2 and the input voltage V.sub.DC2. Hence, the error amplifier AMP2 will make the input voltage V.sub.DC2 (e.g., mean voltage of V.sub.OUT2 or V.sub.INT1) same as or close to the reference voltage V.sub.REF2 (e. g., V.sub.REF_OUT2 OF V.sub.REF_INT1). Since the next-stage circuit 20 and the replica next-stage circuit 616 have the same V-V characteristic, the mean of the output voltage V.sub.OUT is the same as or close to the reference voltage V.sub.REF when the input voltage V.sub.DC2 (e. g., mean voltage of V.sub.OUT2 or V.sub.INT1) is the same as or close to the reference voltage V.sub.REF2 (e.g., V.sub.REF_OUT2 or V.sub.REF_INT1). In other words, the bias voltage V.sub.CM_P is adaptively adjusted to make the output mean voltage of the push-pull source follower circuit 600 equal to the reference voltage V.sub.REF. In this embodiment, the reference voltage V.sub.REF is programmable, and the output mean voltage of the push-pull source follower circuit 600 is set by programming the reference voltage V.sub.REF provided by a voltage generator (not shown). To put it simply, the reference voltage V.sub.REF is one programmable parameter of the push-pull source follower circuit 600.

[0089] Regarding the biasing circuit 604, it includes a replica source follower 611, a current source 612, the error amplifier AMP1, and a capacitor C1. The replica source follower 611 corresponds to the transistor MN2 of the main source follower 602, and includes a transistor MN1, where the transistor MN1 is an NMOS transistor acting as an N-type source follower. The transistor MN1 has a gate terminal (which acts as a control terminal), a source terminal (which acts as a first connection terminal), and a drain terminal (which acts as a second connection terminal), where the bias voltage V.sub.CM_N is generated at the gate terminal, and the drain terminal is coupled to the power rail on which the supply voltage VDD is delivered. Specifically, the replica source follower 611 is a replica of the N-type source follower (i.e., transistor MN2) included in the main source follower 602, where the I-V characteristic of the replica source follower 611 may be the same as that of the N-type source follower included in the main source follower 602. In some embodiments of the present invention, the replica source follower 611 (particularly, transistor MN1 of replica source follower 611) may be a scaled version of the N-type source follower in the main source follower 602 (particularly, transistor MN2 of main source follower 602). For example, the transistor MN1 may be a scaled-down version of the transistor MN2 for power saving and area saving. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention.

[0090] The error amplifier AMP1 has a first input terminal, a second input terminal, and an output terminal, where the first input terminal is coupled to the source terminal of the transistor MN1, the second input terminal is configured to receive the reference voltage V.sub.REF (which is a target level of the output mean voltage), and the output terminal is coupled to the gate terminal of the transistor MN1.

[0091] The current source 612 is coupled between the first input terminal of the error amplifier AMP1 and the power rail on which the ground voltage GND is delivered, and is configured to provide a reference current I.sub.bias. The reference current I.sub.bias acts as a bias current flowing through the transistor MN1, such that an output voltage V.sub.REP_O of the replica source follower 611 is established at the source terminal of the transistor MN1 under a condition that the bias voltage V.sub.CM_N is applied to the gate terminal of the transistor MN1. The error amplifier AMP1 adaptively adjusts the bias voltage V.sub.CM_N according to an error between the output voltage V.sub.REP_O and the reference voltage V.sub.REF. The bias voltage V.sub.CM_N is held by the capacitor C1. Since the reference current I.sub.bias flowing through the transistor MN1 has a constant current value, the output voltage (i.e., source voltage of transistor MN1) V.sub.REP_O changes in response to a change of the bias voltage (i.e., gate voltage of transistor MN1) V.sub.CM_N. In other words, the error amplifier AMP1 adaptively adjusts the bias voltage V.sub.CM_N to minimize the error between the output voltage V.sub.REP_O and the reference voltage V.sub.REF. Hence, the error amplifier AMP1 will make the output voltage V.sub.REP_O same as or close to the reference voltage V.sub.REF.

[0092] Since the replica source follower 611 is a replica (e.g., scaled version) of the N-type source follower of the main source follower 602, a bias current of the main source follower 602 is also a replica (e.g., scaled version) of the reference current I.sub.bias under a condition that gate terminals of transistors MN1 and MN2 are biased by the same bias voltage V.sub.CM_N, drain terminals of transistors MN1 and MN2 are set by the same supply voltage VDD, and source terminals of transistors MN1 and MN2 have the same DC voltage V.sub.REP_O=V.sub.REF=mean of V.sub.OUT. In this embodiment, the reference current I.sub.bias is programmable, and the bias current of the main source follower 602 is set by programming the reference current I.sub.bias provided by the current source 612. To put it simply, the reference current I.sub.bias is another programmable parameter of the push-pull source follower circuit 600.

[0093] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.