SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT, AND DISPLAY DEVICE

Abstract

A shift register unit, a gate driving circuit and a display device are disclosed. The shift register unit includes a shift register and a voltage adjusting circuit. The voltage adjusting circuit is coupled to a set node of the shift register. In a working process, the voltage adjusting circuit is configured to adjust a voltage of the set node in response to a signal of a first clock signal terminal.

Claims

1. A shift register unit, comprising: a shift register; and a voltage adjusting circuit, coupled to a set node of the shift register, and configured to adjust a voltage of the set node in response to a signal of a first clock signal terminal.

2. The shift register unit according to claim 1, wherein the set node comprises a pull-up node, the voltage adjusting circuit comprises a first capacitor; a first terminal of the first capacitor is coupled to the first clock signal terminal, and a second terminal of the first capacitor is coupled to the pull-up node.

3. The shift register unit according to claim 1, wherein the set node comprises a pull-down node, the voltage adjusting circuit comprises a second capacitor; a first terminal of the second capacitor is coupled to the first clock signal terminal, and a second terminal of the second capacitor is coupled to the pull-down node.

4. The shift register unit according to claim 1, wherein the shift register comprises: an input circuit, configured to provide a signal of an input signal terminal to a pull-down node in response to the signal of the first clock signal terminal; a node control circuit, configured to control a signal of a pull-up node and a signal of the pull-down node; an output circuit, configured to provide a signal of a first reference signal terminal to an output terminal in response to the signal of the pull-up node, and provide a signal of a second clock signal terminal to the output terminal in response to the signal of the pull-down node.

5. The shift register unit according to claim 4, wherein the input circuit comprises: a first transistor; a control terminal of the first transistor is coupled to the first clock signal terminal, a first terminal of the first transistor is coupled to the input signal terminal, and a second terminal of the first transistor is coupled to the pull-down node.

6. The shift register unit according to claim 4, wherein the node control circuit comprises a second transistor, a third transistor, a fourth transistor, and a fifth transistor; a control terminal of the second transistor is coupled to the first clock signal terminal, a first terminal of the second transistor is coupled to a second reference signal terminal, and a second terminal of the second transistor is coupled to the pull-up node; a control terminal of the third transistor is coupled to a second terminal of a first transistor, a first terminal of the third transistor is coupled to the pull-up node, and a second terminal of the third transistor is coupled to the first clock signal terminal; a control terminal of the fourth transistor is coupled to the pull-up node, a first terminal of the fourth transistor is coupled to the first reference signal terminal, and a second terminal of the fourth transistor is coupled to a first terminal of the fifth transistor; a control terminal of the fifth transistor is coupled to the second clock signal terminal, and a second terminal of the fifth transistor is coupled to the pull-down node.

7. The shift register unit according to claim 4, wherein the output circuit comprises a sixth transistor and a seventh transistor; a control terminal of the sixth transistor is coupled to the pull-down node, a first terminal of the sixth transistor is coupled to the output terminal, and a second terminal of the sixth transistor is coupled to the second clock signal terminal; a control terminal of the seventh transistor is coupled to the pull-up node, a first terminal of the seventh transistor is coupled to the first reference signal terminal, and a second terminal of the seventh transistor is coupled to the output terminal.

8. The shift register unit according to claim 4, wherein the output circuit comprises a third capacitor; a first terminal of the third capacitor is coupled to the first reference signal terminal, and a second terminal of the third capacitor is coupled to the pull-up node.

9. The shift register unit according to claim 4, wherein the output circuit comprises a fourth capacitor; a first terminal of the fourth capacitor is coupled to the output terminal, and a second terminal of the fourth capacitor is coupled to the pull-down node.

10. A gate driving circuit, comprising: a plurality of cascaded shift register units each according to claim 1; wherein: an input signal terminal of a shift register unit of a first stage is configured to be coupled to a frame start signal terminal; and in every two adjacent shift register units, an input signal terminal of a shift register unit of a next stage is configured to be coupled to an output terminal of a shift register unit of a previous stage.

11. A display device, comprising the gate driving circuit according to claim 10.

12. A driving method of a shift register, comprising: outputting, by the shift register, a driving signal; adjusting, by a voltage adjusting circuit, a voltage of a set node of the shift register in response to a signal of a first clock signal terminal.

Description

BRIEF DESCRIPTION OF FIGURES

[0041] The accompanying drawings described herein are intended to provide further understanding of the present disclosure and form a part of the present disclosure. The illustrative embodiments and their descriptions of the present disclosure are used to explain the present disclosure and do not constitute undue limitations on the present disclosure.

[0042] FIG. 1 is a schematic diagram of a shift register unit in related art;

[0043] FIG. 2 is a schematic diagram of an internal connection of a shift register unit according to an embodiment of the present disclosure;

[0044] FIG. 3 is a schematic diagram of internal connections of a shift register according to an embodiment of the present disclosure;

[0045] FIG. 4 is a circuit connection diagram of a first shift register unit according to an embodiment of the present disclosure;

[0046] FIG. 5 is a circuit connection diagram of a second shift register unit according to an embodiment of the present disclosure;

[0047] FIG. 6 is a circuit connection diagram of a third shift register unit according to an embodiment of the present disclosure;

[0048] FIG. 7 is a circuit connection diagram of a fourth shift register unit according to an embodiment of the present disclosure;

[0049] FIG. 8 is a timing diagram of a shift register unit according to an embodiment of the present disclosure;

[0050] FIG. 9 is a schematic diagram of cascaded gate driving circuits according to an embodiment of the present disclosure;

[0051] FIG. 10 is a flowchart of a method for driving a shift register according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

[0052] For making objectives, technical solutions and advantages of embodiments of the present disclosure clearer, technical solutions of embodiments of the present disclosure will be clearly and completely described below in combination with accompanying drawings in embodiments of the present disclosure. Apparently, embodiments described are some rather than all of embodiments of the present disclosure. Based on embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present disclosure.

[0053] The terms first, second, etc. in the specification and claims of the present disclosure and the accompanying drawings are used to distinguish similar objects and do not necessarily need to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged in appropriate circumstances, so that embodiments of the present disclosure described herein can be implemented in a sequence other than those illustrated or described herein.

[0054] In the related art, in the working process of the shift register unit, the related transistor is subjected to a large voltage impact, that is, the negative drift of the related transistor in the working process is large, resulting in an impact on service life of the related transistor.

[0055] Referring to FIG. 1, after a voltage of a second reference signal terminal VGL is provided to a node N3 through a M3 transistor turned on, gate-source voltages of a M5 transistor and a M6 transistor are Vgs=VGL-VGH=5V-10V=15V. In this case, related transistors of the M5 transistor and the M6 transistor connected with the pull-up node N3 are subjected to a large voltage impact, negative drifts of the M5 transistor and the M6 transistor are large, resulting in an impact on service life of the M5 transistor and the M6 transistor.

[0056] Embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0057] Referring to FIG. 2, in an embodiment of the present disclosure, a shift register unit includes a shift register 10 and a voltage adjusting circuit 20.

[0058] Referring to FIG. 3, the shift register 10 includes an input circuit 101, a node control circuit 102, and an output circuit 103.

[0059] During implementation, the input circuit 101 is configured to provide a signal of an input signal terminal STV to a pull-down node N1 in response to a signal of a first clock signal terminal CK.

[0060] During implementation, the node control circuit 102 is configured to control a signal of a pull-up node N3 and a signal of the pull-down node N1.

[0061] During implementation, the output circuit 103 is configured to provide a signal of a first reference signal terminal VGH to an output terminal OUT in response to the signal of the pull-up node N3, and provide a signal of a second clock signal terminal CB to the output terminal OUT in response to the signal of the pull-down node N1.

[0062] The shift register 10 is described in detail below in combination with a circuit diagram.

[0063] Referring to FIG. 4, the input circuit includes a first transistor T1.

[0064] Connection relationships between the first transistor T1 and other components in FIG. 4 are: a control terminal of the first transistor T1 is coupled to the first clock signal terminal CK, a first terminal of the first transistor T1 is coupled to the input signal terminal STV, and a second terminal of the first transistor T1 is coupled to the pull-down node N1.

[0065] During implementation, when the first clock signal terminal CK is at a low voltage, the first transistor T1 is turned on, a low voltage at the input signal terminal STV is output to the pull-down node N1 through the first transistor T1, so that the pull-down node N1 is at the low voltage.

[0066] When the first clock signal terminal CK is at a low voltage, the first transistor T1 is turned on, a high voltage at the input signal terminal STV is output to the pull-down node N1 through the first transistor T1, so that the pull-down node N1 is at the high voltage.

[0067] Referring to FIG. 4, optionally, the node control circuit includes a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5.

[0068] Connection relationships between the second transistor T2 and other components in FIG. 4 are: a control terminal of the second transistor T2 is coupled to the first clock signal terminal CK, a first terminal of the second transistor T2 is coupled to a second reference signal terminal VGL, and a second terminal of the second transistor T2 is coupled to the pull-up node N3.

[0069] Connection relationships between the third transistor T3 and other components in FIG. 4 are: a control terminal of the third transistor T3 is connected to the second terminal of the first transistor T1, a first terminal of the third transistor T3 is coupled to the pull-up node N3, and a second terminal of the third transistor T3 is coupled to the first clock signal terminal CK.

[0070] Connection relationships between the fourth transistor T4 and other components in FIG. 4 are: a control terminal of the fourth transistor T4 is coupled to the pull-up node N3, a first terminal of the fourth transistor T4 is coupled to the first reference signal terminal VGH, and a second terminal of the fourth transistor T4 is coupled to a first terminal of the fifth transistor T5.

[0071] Connection relationships between the fifth transistor T5 and other components in FIG. 4 are: a control terminal of the fifth transistor T5 is coupled to the second clock signal terminal CB, and a second terminal of the fifth transistor T5 is coupled to the pull-down node N1.

[0072] During implementation, when the pull-down node N1 is at a low voltage, the third transistor T3 is turned on, a high voltage at the first clock signal terminal CK flows to the pull-up node N3 through the third transistor T3 turned on, so that the pull-up node N3 is at a high voltage.

[0073] When the first clock signal terminal CK is at a low voltage, the second transistor T2 is turned on, a low voltage at the second reference signal terminal VGL flows to the pull-up node N3 through the second transistor T2 turned on, a low voltage at the second reference signal terminal VGL achieves a reset of the pull-up node N3.

[0074] During implementation, when the pull-up node N3 is at a low voltage, the fourth transistor T4 is turned on, a high voltage at the first reference signal terminal VGH reaches the node N2 through the fourth transistor T4 turned on. Furthermore, when the second clock signal terminal CB is at a low voltage, the fifth transistor T5 is turned on, a high voltage at the node N2 reaches the pull-down node N1 through the fifth transistor T5 turned on, causing the pull-down node N1 to be at a high voltage.

[0075] Furthermore, when the second clock signal terminal CB is at a low voltage, the fifth transistor T5 is turned on, a high voltage of the first reference signal terminal VGH reaches the pull-down node N1 through the fourth transistor T4 turned on and the fifth transistor T5 turned on, causing the pull-down node N1 to be at a high voltage.

[0076] Optionally, the output circuit includes a sixth transistor T6 and a seventh transistor T7.

[0077] Connection relationships between the sixth transistor T6 and other components in FIG. 4 are: a control terminal of the sixth transistor T6 is coupled to the pull-down node N1, a first terminal of the sixth transistor T6 is coupled to the output terminal OUT, and a second terminal of the sixth transistor T6 is coupled to the second clock signal terminal CB.

[0078] During implementation, when the pull-down node N1 is at a low voltage, the sixth transistor T6 is turned on, a signal of the second clock signal terminal CB reaches the output terminal OUT through the sixth transistor T6 turned on.

[0079] It should be noted that in order to control the pull-down node N1, the shift register is further provided with an eighth transistor T8. A gate of the eighth transistor T8 is coupled to the second reference signal terminal VGL, a first terminal of the eighth transistor T8 is coupled to the second terminal of the first transistor T1, and a second terminal of the eighth transistor T8 is coupled to a gate of the sixth transistor T6.

[0080] During implementation, when the second reference signal terminal VGL is at a low voltage, the eighth transistor T8 is turned on, a signal of the input signal terminal STV reaches the sixth transistor T6 through the eighth transistor T8 turned on, ensuring normal turn-on of the sixth transistor T6.

[0081] Connection relationships between the seventh transistor T7 and other components in FIG. 4 are: a control terminal of the seventh transistor T7 is coupled to the pull-up node N3, a first terminal of the seventh transistor T7 is coupled to the first reference signal terminal VGH, and a second terminal of the seventh transistor T7 is coupled to the output terminal OUT.

[0082] During implementation, when the pull-up node N3 is at a low voltage, the seventh transistor T7 is turned on, a high voltage signal of the first reference signal terminal VGH reaches the output terminal OUT through the seventh transistor T7 turned on, and is output.

[0083] Referring to FIG. 4, the output circuit further includes a third capacitor C3.

[0084] Connection relationships between the third capacitor C3 and other components in FIG. 4 are: a first terminal of the third capacitor C3 is coupled to the first reference signal terminal VGH, and a second terminal of the third capacitor C3 is coupled to the pull-up node N3.

[0085] During implementation, the third capacitor C3 is mainly configured to store a low voltage signal of the pull-up node N3, to ensure that the seventh transistor T7 is normally turned on in a next time sequence.

[0086] Similarly, referring to FIG. 4, the output circuit further includes a fourth capacitor C4.

[0087] Connection relationships between the fourth capacitor C4 and other components in FIG. 4 are: a first terminal of the fourth capacitor C4 is coupled to the output terminal OUT, and a second terminal of the fourth capacitor C4 is coupled to the pull-down node N1.

[0088] During implementation, the fourth capacitor C4 is mainly configured to store a low voltage signal of the pull-down node N1, to ensure that the sixth transistor T6 is normally turned on in a next time sequence.

[0089] The voltage adjusting circuit 20 is described in detail below in combination with a circuit diagram.

[0090] The voltage adjusting circuit 20 is coupled to a set node of the shift register, and configured to adjust a voltage of the set node in response to a signal of a first clock signal terminal CK.

[0091] Considering that the set node of the shift register includes two types of nodes of a pull-up node N3 and a pull-down node N1, in an embodiment of the present disclosure, correspondingly, the voltage adjusting circuit 20 is described in two cases according to a specific type of the set node connected. In a first case, when the set node includes the pull-up node N3, the voltage adjusting circuit 20 includes a first capacitor C1. In a second case, when the set node includes the pull-down node N1, the voltage adjusting circuit 20 includes a second capacitor C2. The following is a detailed introduction.

[0092] Referring to FIG. 5, in the first case, the set node includes the pull-up node N3, and the voltage adjusting circuit 20 includes the first capacitor C1.

[0093] A first terminal of the first capacitor C1 is coupled to the first clock signal terminal CK, and a second terminal of the first capacitor C1 is coupled to the pull-up node N3.

[0094] During implementation, when a signal at the first clock signal terminal CK changes from low to high, that is, during a turn-off process of the second transistor T2, a voltage of the pull-up node N3 is raised by the first capacitor C1, and in general, the voltage of the pull-up node N3 can be raised by 2 V to 3 V. In this way, the voltage impact on the voltage of the pull-up node N3 can be effectively alleviated, and gate-source voltages of the fourth transistor T4 and the seventh transistor T7 are Vgs=VGL-VGH=2V-10V=12V. Negative drifts of the fourth transistor T4 and the seventh transistor T7 are reduced, effectively ensuring the service life of the fourth transistor T4 and the seventh transistor T7.

[0095] Referring to FIG. 6, in another embodiment, after the first capacitor C1 is provided, the first capacitor C1 can be used to store the voltage of the pull-up node N3, so that the third capacitor C3 connected to the seventh transistor T7 can be omitted, and the normal output of the shift register unit can also be ensured.

[0096] Referring to FIG. 7, in the second case, the set node includes the pull-down node N1, and the voltage adjusting circuit 20 further includes a second capacitor C2.

[0097] A first terminal of the second capacitor C2 is coupled to the first clock signal terminal CK, and a second terminal of the second capacitor C2 is coupled to the pull-down node N1.

[0098] During implementation, when a signal at the first clock signal terminal CK changes from low to high, that is, during a turn-off process of the second transistor T2, a voltage of the pull-down node N1 is raised by the second capacitor C2, and in general, the voltage of the pull-down node N1 can be raised by 2 V to 3 V. In this way, the voltage impact on the voltage of the pull-down node N1 can be effectively alleviated, and gate-source voltages of the fifth transistor T5 and the sixth transistor T6 are Vgs=VGL-VGH=2V-10V=12V. Negative drifts of the fifth transistor T5 and the sixth transistor T6 are reduced, effectively ensuring the service life of the fifth transistor T5 and the sixth transistor T6.

[0099] Similarly, in another embodiment, after the second capacitor C2 is provided, the second capacitor C2 can be used to store the voltage of the pull-down node N1, so that the fourth capacitor C4 connected to the sixth transistor T6 can be omitted, and the normal output of the shift register unit can also be ensured.

[0100] Referring to FIG. 8, a main working process of the shift register unit is described below in combination with a timing diagram.

[0101] In a timing T1 phase: STV=0, CK=0, N1=0, N4=0, N3=1.

[0102] When the first clock signal terminal CK is at a low voltage, the first transistor T1 is turned on, and the input signal terminal STV is at a low voltage. In this case, the voltage of the pull-down node N1 is low, the voltage of the corresponding node N4 is also low, and the sixth transistor is turned on. The output terminal OUT outputs a waveform of the second clock signal terminal CB.

[0103] In a timing T2 phase: STV=1, CK=1, N1=0, N4=0, N3=1.

[0104] When the first clock signal terminal CK is at a high voltage, the first transistor T1 is turned off, and the input signal terminal STV is at a high voltage. In this case, the voltage of the pull-down node N1 is low, the voltage of the corresponding node N4 is also low, and the sixth transistor is turned on. The output terminal OUT still outputs the waveform of the second clock signal terminal CB.

[0105] In a timing T3 phase: STV=1, CK=0, N1=1, N4=1, N3=0.

[0106] When the first clock signal terminal CK is at a low voltage, the first transistor T1 is turned on, and the input signal terminal STV is at a high voltage. The voltage of the pull-down node N1 is high, the voltage of the corresponding node N4 is also high, and the sixth transistor is turned off. When the first clock signal terminal CK is at a low voltage, the second transistor T2 is turned on, the low voltage of the second reference signal terminal VGL causes the pull-up node N3 to be low, the corresponding seventh transistor is turned on. The high voltage of the first reference signal terminal VGH is output through the output terminal OUT.

[0107] In a phase after timing T3: STV=1, CK changes from low to high, N1=1, N4=1, N3=0.

[0108] When the first clock signal terminal CK changes from low to high, the first transistor and the second transistor change from on to off, the first capacitor C1 may raise the voltage at the pull-up node N3 due to CK coupling, reducing the negative drifts of the fourth transistor and the seventh transistor and ensuring the service life of the fourth transistor and the seventh transistor. Similarly, the second capacitor C2 raises the voltage at the pull-down node N1 due to the CK coupling, reducing the negative drifts of the fifth transistor and the sixth transistor and ensuring the service life of the fifth transistor and the sixth transistor.

[0109] Base on that same inventive concept, referring to FIG. 9, a gate driving circuit including a plurality of cascaded shift register units is provided according to embodiments of the present disclosure, and each of the cascaded shift register units includes the above shift register unit.

[0110] An input signal terminal of a shift register unit of a first stage is configured to be coupled to a frame start signal terminal.

[0111] In every two adjacent shift register units, an input signal terminal of a shift register unit of a next stage is configured to be coupled to an output terminal of a shift register unit of a previous stage.

[0112] Based on the same inventive concept, embodiments of the present disclosure provide a display device including the gate driving circuit described above.

[0113] The display device according to embodiments of the present disclosure may be any product or component with display function such as a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator. Other essential components of the display device should be understood by those skilled in the art and should not be repeated here, nor should they be taken as limitations on this disclosure.

[0114] Based on the same inventive concept, referring to FIG. 10, a driving method for a shift register is provided according to an embodiment of the present disclosure, and includes following steps.

[0115] Step 201: the shift register outputs a driving signal.

[0116] Referring to FIG. 4, when the seventh transistor is turned on, the signal of the first reference signal terminal reaches the output terminal of the shift register through the seventh transistor turned on. When the sixth transistor is turned on, the signal of the second clock signal terminal reaches the output terminal of the shift register through the sixth transistor turned on.

[0117] Step 202: a voltage adjusting circuit adjusts a voltage of a set node in response to a signal of a first clock signal terminal.

[0118] In the process of outputting the driving signal by the shift register, the voltage adjusting circuit adjusts the voltage at the set node in response to the signal of the first clock signal terminal CK. During specific implementation, the first capacitor adjusts the voltage of the pull-up node in response to the signal of the first clock signal terminal CK. The second capacitor adjusts the voltage of the pull-down node in response to the signal of the first clock signal terminal CK.

[0119] In summary, embodiments of the present disclosure provide a shift register unit, a gate driving circuit and a display device. The shift register unit includes a shift register and an anti-leakage circuit. The anti-leakage circuit is coupled to a set node of the shift register, and is configured to stabilize a voltage of the set node according to a signal of a leakage control signal terminal in a touch phase. That is, the aim of stabilizing the voltage is achieved at the set node by means of making up the leakage and inhibiting the leakage. Therefore, the leakage of the pull-up node of the shift register is effectively reduced, and the display effect is improved.

[0120] Those skilled in the art should understand that embodiments of the present disclosure can be provided as methods, systems or computer program product systems. Therefore, the present disclosure can adopt forms of full hardware embodiments, full software embodiments, or embodiments combining software and hardware aspects. Moreover, the present disclosure can adopt a form of the computer program product systems implemented on one or more computer available storage mediums (including but not limited to a disk memory, a CD-ROM, an optical memory and the like) containing computer available program codes.

[0121] The present disclosure is described with reference to flow charts and/or block diagrams of the methods, the devices (systems), and the computer program product systems according to embodiments of the present disclosure. It should be understood that each flow and/or block in the flow charts and/or the block diagrams and combinations of the flows and/or the blocks in the flow charts and/or the block diagrams can be implemented by computer program instructions. The computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processing machine or other programmable data processing equipment, to generate a machine, such that the instructions, when executed by the processor of the computers or other programmable data processing equipment, generate devices for implementing functions specified in one or more flows in the flow charts and/or one or more blocks in the block diagrams.

[0122] The computer program instructions may also be stored in a computer readable memory which can guide the computers or other programmable data processing equipment to work in a specific mode, thus the instructions stored in the computer readable memory generates an article of manufacture that includes a commander device that implement the functions specified in one or more flows in the flow charts and/or one or more blocks in the block diagrams.

[0123] The computer program instructions may also be loaded to the computers or other programmable data processing equipment, so that a series of operating steps may be executed on the computers or other programmable equipment to generate computer-implemented processing, such that the instructions executed on the computers or other programmable equipment provide steps for implementing the functions specified in one or more flows in the flow charts and/or one or more blocks in the block diagrams.

[0124] Obviously, those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. In this way, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent art, the present disclosure also intends to include these modifications and variations.

[0125] The computer program instructions may also be stored in a computer readable memory which can guide the computers or other programmable data processing equipment to work in a specific mode, thus the instructions stored in the computer readable memory generates an article of manufacture that includes a commander device that implement the functions specified in one or more flows in the flow charts and/or one or more blocks in the block diagrams.

[0126] The computer program instructions may also be loaded to the computers or other programmable data processing equipment, so that a series of operating steps may be executed on the computers or other programmable equipment to generate computer-implemented processing, such that the instructions executed on the computers or other programmable equipment provide steps for implementing the functions specified in one or more flows in the flow charts and/or one or more blocks in the block diagrams.

[0127] Obviously, those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. In this way, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent art, the present disclosure also intends to include these modifications and variations.