APPARATUS AND SYSTEMS FOR A DETECTOR CELL IN A SUCCESSIVE DETECTION LOGARITHMIC AMPLIFIER

Abstract

An example detector cell includes a first current source circuit having a terminal. The detector cell includes a first transistor having a control terminal, a first terminal, and a second terminal coupled to the terminal of the first current source circuit. The detector cell includes a second current source circuit having a terminal coupled to the first terminal of the first transistor. The detector cell includes a first current mirror having a first terminal and a second terminal, the first terminal coupled to the terminal of the second current source circuit and the first terminal of the first transistor. The detector cell includes a second transistor having a control terminal, a first terminal, and a second terminal coupled to the terminal of the first current source circuit. The detector cell includes a third current source circuit having a terminal coupled to the first terminal of the second transistor. The detector cell includes a second current mirror having a first terminal coupled to the terminal of the third current source circuit and the first terminal of the second transistor and a second terminal coupled to the second terminal of the first current mirror.

Claims

1. A detector cell comprising: a first current source circuit having a terminal; a first transistor having a control terminal, a first terminal, and a second terminal coupled to the terminal of the first current source circuit; a second current source circuit having a terminal coupled to the first terminal of the first transistor; a first current mirror having a first terminal and a second terminal, the first terminal coupled to the terminal of the second current source circuit and the first terminal of the first transistor; a second transistor having a control terminal, a first terminal, and a second terminal coupled to the terminal of the first current source circuit; a third current source circuit having a terminal coupled to the first terminal of the second transistor; and a second current mirror having a first terminal coupled to the terminal of the third current source circuit and the first terminal of the second transistor and a second terminal coupled to the second terminal of the first current mirror.

2. The detector cell of claim 1, further including a resistor having a terminal coupled to the second terminal of the first current mirror and the second terminal of the second current mirror.

3. The detector cell of claim 1, wherein respective ones of the first current mirror and the second current mirror include: a first resistor having a first terminal and a second terminal; a third transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal, the first terminal to operate as the first terminal of the respective ones of the first current mirror and the second current mirror, the second terminal coupled to the second terminal of the first resistor; a fourth transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the control terminal of the third transistor, the first terminal to operate as the second terminal of the respective ones of the first current mirror and the second current mirror; and a second resistor having a first terminal coupled to the first terminal of the first resistor and a second terminal coupled to the second terminal of the fourth transistor.

4. The detector cell of claim 1, wherein: at least one of the second current source circuit or the third current source circuit is implemented by a positive-negative-positive bipolar junction transistor (BJT); and the first current source circuit is implemented by a negative-positive-negative BJT.

5. The detector cell of claim 1, wherein: at least one of the second current source circuit or the third current source circuit is implemented by a positive-channel metal-oxide-semiconductor field-effect transistor (MOSFET); and the first current source circuit is implemented by a negative-channel MOSFET.

6. The detector cell of claim 1, wherein at least one of the first transistor or the second transistor is implemented by a negative-positive-negative bipolar junction transistor.

7. The detector cell of claim 1, wherein at least one of the first transistor or the second transistor is implemented by a negative-channel metal-oxide-semiconductor field-effect transistor.

8. A logarithmic amplifier comprising: a first detector cell having a first terminal, a second terminal, and a third terminal; an amplifier having a first terminal, a second terminal, a third terminal coupled to the second terminal of the first detector cell, and a fourth terminal coupled to the third terminal of the first detector cell; a second detector cell having a first terminal, a second terminal coupled to the first terminal of the amplifier, and a third terminal coupled to the second terminal of the amplifier; an adder having a first terminal, a second terminal coupled to the first terminal of the first detector cell, and a third terminal coupled to the first terminal of the second detector cell, respective ones of the first detector cell and the second detector cell including: a first current source circuit having a terminal; a first transistor having a control terminal, a first terminal, and a second terminal, the control terminal to operate as the second terminal of the respective ones of the first detector cell and the second detector cell, the second terminal coupled to the terminal of the first current source circuit; a second current source circuit having a terminal coupled to the first terminal of the first transistor; a first current mirror having a first terminal coupled to the terminal of the second current source circuit and the first terminal of the first transistor and a second terminal to operate as the first terminal of the respective ones of the first detector cell and the second detector cell; a second transistor having a control terminal, a first terminal, and a second terminal, the control terminal to operate as the third terminal of the respective ones of the first detector cell and the second detector cell, the second terminal coupled to the terminal of the first current source circuit; a third current source circuit having a terminal coupled to the first terminal of the second transistor; and a second current mirror having a first terminal coupled to the terminal of the third current source circuit and the first terminal of the second transistor and a second terminal coupled to the second terminal of the first current mirror and to operate as the first terminal of the respective ones of the first detector cell and the second detector cell.

9. The logarithmic amplifier of claim 8, wherein the amplifier is a first amplifier, the adder is a first adder, and the logarithmic amplifier includes: a second amplifier having a first terminal, a second terminal, a third terminal coupled to the first terminal of the first amplifier, and a fourth terminal coupled to the second terminal of the first amplifier; a third detector cell having a first terminal, a second terminal coupled to the first terminal of the second amplifier, and a third terminal coupled to the second terminal of the second amplifier; a third amplifier having a first terminal, a second terminal, a third terminal coupled to the first terminal of the second amplifier, and a fourth terminal coupled to the second terminal of the second amplifier; a fourth detector cell having a first terminal, a second terminal coupled to the first terminal of the third amplifier, and a third terminal coupled to the second terminal of the third amplifier; a second adder having a first terminal, a second terminal coupled to the first terminal of the third detector cell, and a third terminal coupled to the first terminal of the fourth detector cell; a third adder having a first terminal, a second terminal coupled to the first terminal of the first adder, and a third terminal coupled to the first terminal of the second adder; and a filter having a first terminal and a second terminal coupled to the first terminal of the third adder, respective ones of the third detector cell and the fourth detector cell including: a fourth current source circuit having a terminal; a third transistor having a control terminal, a first terminal, and a second terminal, the control terminal to operate as the second terminal of the respective ones of the third detector cell and the fourth detector cell, the second terminal coupled to the terminal of the fourth current source circuit; a fifth current source circuit having a terminal coupled to the first terminal of the third transistor; a third current mirror having a first terminal coupled to the terminal of the fifth current source circuit and the first terminal of the third transistor, and a second terminal to operate as the first terminal of the respective ones of the third detector cell and the fourth detector cell; a fourth transistor having a control terminal, a first terminal, and a second terminal, the control terminal to operate as the third terminal of the respective ones of the third detector cell and the fourth detector cell, the second terminal coupled to the terminal of the fourth current source circuit; a sixth current source circuit having a terminal coupled to the first terminal of the fourth transistor; and a fourth current mirror having a first terminal coupled to the terminal of the sixth current source circuit and the first terminal of the fourth transistor and a second terminal coupled to the second terminal of the third current mirror and to operate as the first terminal of the respective ones of the third detector cell and the fourth detector cell.

10. The logarithmic amplifier of claim 8, wherein the respective ones of the first detector cell and the second detector cell further include a resistor having a first terminal coupled to the second terminal of the first current mirror and the second terminal of the second current mirror, the first terminal to operate as the first terminal of the respective ones of the first detector cell and the second detector cell.

11. The logarithmic amplifier of claim 8, wherein respective ones of the first current mirror and the second current mirror include: a first resistor having a first terminal and a second terminal; a third transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal, the first terminal to operate as the first terminal of the respective ones of the first current mirror and the second current mirror, the second terminal coupled to the second terminal of the first resistor; a fourth transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the control terminal of the third transistor, the first terminal to operate as the second terminal of the respective ones of the first current mirror and the second current mirror; and a second resistor having a first terminal coupled to the first terminal of the first resistor and a second terminal coupled to the second terminal of the fourth transistor.

12. The logarithmic amplifier of claim 8, wherein: at least one of the second current source circuit or the third current source circuit is implemented by a positive-negative-positive bipolar junction transistor (BJT); and the first current source circuit is implemented by a negative-positive-negative BJT.

13. The logarithmic amplifier of claim 8, wherein: at least one of the second current source circuit or the third current source circuit is implemented by a positive-channel metal-oxide-semiconductor field-effect transistor (MOSFET); and the first current source circuit is implemented by a negative-channel MOSFET.

14. The logarithmic amplifier of claim 8, wherein at least one of the first transistor or the second transistor is implemented by a negative-positive-negative bipolar junction transistor.

15. The logarithmic amplifier of claim 8, wherein at least one of the first transistor or the second transistor is implemented by a negative-channel metal-oxide-semiconductor field-effect transistor.

16. A logarithmic amplifier having a non-linear transfer function, the logarithmic amplifier comprising: a first detector cell having a first terminal, a second terminal, and a third terminal, the first detector cell having a first linear transfer function; an amplifier having a first terminal, a second terminal, a third terminal coupled to the second terminal of the first detector cell, and a fourth terminal coupled to the third terminal of the first detector cell; a second detector cell having a first terminal, a second terminal coupled to the first terminal of the amplifier, and a third terminal coupled to the second terminal of the amplifier, the second detector cell having a second linear transfer function; and an adder having a first terminal, a second terminal coupled to the first terminal of the first detector cell, and a third terminal coupled to the first terminal of the second detector cell.

17. The logarithmic amplifier of claim 16, wherein the amplifier is a first amplifier, the adder is a first adder, and the logarithmic amplifier includes: a second amplifier having a first terminal, a second terminal, a third terminal coupled to the first terminal of the first amplifier, and a fourth terminal coupled to the second terminal of the first amplifier; a third detector cell having a first terminal, a second terminal coupled to the first terminal of the second amplifier, and a third terminal coupled to the second terminal of the second amplifier, the third detector cell having a third linear transfer function; a third amplifier having a first terminal, a second terminal, a third terminal coupled to the first terminal of the second amplifier, and a fourth terminal coupled to the second terminal of the second amplifier; a fourth detector cell having a first terminal, a second terminal coupled to the first terminal of the third amplifier, and a third terminal coupled to the second terminal of the third amplifier, the fourth detector cell having a fourth linear transfer function; a second adder having a first terminal, a second terminal coupled to the first terminal of the third detector cell, and a third terminal coupled to the first terminal of the fourth detector cell; a third adder having a first terminal, a second terminal coupled to the first terminal of the first adder, and a third terminal coupled to the first terminal of the second adder; and a filter having a first terminal and a second terminal coupled to the first terminal of the third adder.

18. The logarithmic amplifier of claim 16, wherein respective ones of the first detector cell and the second detector cell are to rectify respective input voltage signals.

19. The logarithmic amplifier of claim 16, wherein respective output voltage signals from respective ones of the first detector cell and the second detector cell are to saturate after respective input voltage signals to the respective ones of the first detector cell and the second detector cell reach a saturation voltage.

20. The logarithmic amplifier of claim 16, wherein respective ones of the first detector cell and the second detector cell are to improve a logarithmic conformance error and a dynamic range of the logarithmic amplifier.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1A is a block diagram of an example successive detection logarithmic amplifier (SDLA) with differential inputs and differential outputs.

[0008] FIG. 1B is a block diagram of the SDLA of FIG. 1A with differential inputs and a single ended output.

[0009] FIG. 2A is a graphical illustration of an example graph depicting a relationship between dynamic range (DR) of an SDLA and the gain, A, of each amplifier stage of the SDLA.

[0010] FIG. 2B is a graphical illustration of an example graph depicting a relationship between logarithmic conformance error (LCE) of an SDLA and the gain, A, of each amplifier stage of the SDLA.

[0011] FIG. 3 is a schematic of an example detector cell in conjunction with examples described herein.

[0012] FIG. 4 is a graphical illustration of an example graph depicting a transfer function of the detector cell of FIG. 3.

[0013] FIG. 5A is a graphical illustration of an example graph depicting a relationship between a degree of a detector cell and LCE of an SDLA.

[0014] FIG. 5B is a graphical illustration of an example graph depicting a relationship between a degree of a detector cell and DR of an SDLA.

[0015] FIG. 5C is a graphical illustration of an example graph depicting a relationship between the transfer function of a detector cell and a degree of the detector cell.

[0016] The drawings are not necessarily to scale. Generally, the same reference numbers in the drawing(s) and this description refer to the same or similar (at least one of functional or structural) features or parts. Although the drawings show regions with clean lines and boundaries, some or all of these lines and boundaries may be idealized. In reality, the boundaries or lines may be unobservable, blended or irregular.

DETAILED DESCRIPTION

[0017] Logarithmic amplifiers, sometimes referred to as log amplifiers, produce an output signal that is logarithmically related to an input signal. One type of logarithmic amplifier is a successive detection logarithmic amplifier (SDLA). SDLAs are widely used to measure signal strength in different received signal strength indicator (RSSI) applications such as ultrasound front-end circuits, energy or power monitoring circuits, or transmit power control circuits. SDLAs are widely used because SDLAs can achieve a wide dynamic range of operation as well as high-speed operation. The architecture of an SDLA includes a cascaded chain of amplifier stages shunted by corresponding detector cells. For example, FIG. 1A is a block diagram of an example SDLA 100 with differential inputs and differential outputs.

[0018] In the illustrated example of FIG. 1A, the SDLA 100 includes at least a first example stage 102.sub.A, a second example stage 102.sub.B, and an example filter 104. In some examples, the SDLA 100 also includes a third example stage 102.sub.C and a fourth example stage 102.sub.D. As such, the components of the stage 102.sub.C and the stage 102.sub.D are illustrated with dashed lines. In the example of FIG. 1A, the stage 102.sub.A includes a first example detector cell 106.sub.A. Also, the stage 102.sub.B includes a second example detector cell 106.sub.B and a first example amplifier 108.sub.B. In the example of FIG. 1A, the stage 102.sub.C includes a third example detector cell 106.sub.C and a second example amplifier 108.sub.C. Also, the stage 102.sub.D includes a fourth example detector cell 106.sub.D and a third example amplifier 108.sub.D. In the example of FIG. 1A, the SDLA 100 also includes a first example adder 110.sub.A and a second example adder 110.sub.B. In some examples, the SDLA 100 also includes a third example adder 112.sub.A, a fourth example adder 112.sub.B, a fifth example adder 114.sub.A, and a sixth example adder 114.sub.B. As such, the adder 112.sub.A, the adder 112.sub.B, the adder 114.sub.A, and the adder 114.sub.B are illustrated with dashed lines.

[0019] In the illustrated example of FIG. 1A, each of the filter 104, the detector cell 106.sub.A, the detector cell 106.sub.B, the detector cell 106.sub.C, the detector cell 106.sub.D, the amplifier 108.sub.B, the amplifier 108.sub.C, and the amplifier 108.sub.D has a first input, a second input, a first output, and a second output. Also, each of the adder 110.sub.A, the adder 110.sub.B, the adder 112.sub.A, the adder 112.sub.B, the adder 114.sub.A, and the adder 114.sub.B has a first input, a second input, and an output. In the example of FIG. 1A, the SDLA 100 has a first example input 116.sub.A, a second example input 116.sub.B, a first example output 118.sub.A, and a second example output 118.sub.B.

[0020] In the illustrated example of FIG. 1A, the filter 104 is implemented by at least one of analog or digital circuitry. In the example of FIG. 1A, each of the detector cell 106.sub.A, the detector cell 106.sub.B, the detector cell 106.sub.C, and the detector cell 106.sub.D is implemented as described in connection with FIG. 3 further herein. Also, each of the amplifier 108.sub.B, the amplifier 108.sub.C, and the amplifier 108.sub.D is implemented by at least analog circuitry. In the example of FIG. 1A, each of the adder 110.sub.A, the adder 110.sub.B, the adder 112.sub.A, the adder 112.sub.B, the adder 114.sub.A, and the adder 114.sub.B is implemented by at least one of analog or digital circuitry.

[0021] In the illustrated example of FIG. 1A, the first input of the detector cell 106.sub.A is coupled to the input 116.sub.A, the second input of the detector cell 106.sub.A is coupled to the input 116.sub.B, the first output of the detector cell 106.sub.A is coupled to the first input of the adder 110.sub.A, and the second output of the detector cell 106.sub.A is coupled to the first input of the adder 110.sub.B. Also, the first input of the detector cell 106.sub.B is coupled to the first output of the amplifier 108.sub.B, the second input of the detector cell 106.sub.B is coupled to the second output of the amplifier 108.sub.B, the first output of the detector cell 106.sub.B is coupled to the second input of the adder 110.sub.A, and the second output of the detector cell 106.sub.B is coupled to the second input of the adder 110.sub.B. In the example of FIG. 1A, the first input of the amplifier 108.sub.B is coupled to the input 116.sub.A, the second input of the amplifier 108.sub.B is coupled to the input 116.sub.B, the first output of the amplifier 108.sub.B is coupled to the first input of the amplifier 108.sub.C, and the second output of the amplifier 108.sub.B is coupled to the second input of the amplifier 108.sub.C.

[0022] In the illustrated example of FIG. 1A, the first input of the detector cell 106.sub.C is coupled to the first output of the amplifier 108.sub.C and the second input of the detector cell 106.sub.C is coupled to the second output of the amplifier 108.sub.C. In the example of FIG. 1A, the first output of the detector cell 106.sub.C is coupled to the first input of the adder 112.sub.A and the second output of the detector cell 106.sub.C is coupled to the first input of the adder 112.sub.B. In the example of FIG. 1A, the first input of the amplifier 108.sub.C is coupled to the first output of the amplifier 108.sub.B and the second input of the amplifier 108.sub.C is coupled to the second output of the amplifier 108.sub.B. Also, the first output of the amplifier 108.sub.C is coupled to the first input of the amplifier 108.sub.D and the second output of the amplifier 108.sub.C is coupled to the second input of the amplifier 108.sub.D.

[0023] In the illustrated example of FIG. 1A, the first input of the detector cell 106.sub.D is coupled to the first output of the amplifier 108.sub.D and the second input of the detector cell 106.sub.D is coupled to the second output of the amplifier 108.sub.D. In the example of FIG. 1A, the first output of the detector cell 106.sub.D is coupled to the second input of the adder 112.sub.A and the second output of the detector cell 106.sub.D is coupled to the second input of the adder 112.sub.B. Also, the first input of the amplifier 108.sub.D is coupled to the first output of the amplifier 108.sub.C and the second input of the amplifier 108.sub.D is coupled to the second output of the amplifier 108.sub.C. In the example of FIG. 1A, the first output of the amplifier 108.sub.D is coupled to the first input of the detector cell 106.sub.D and the second output of the amplifier 108.sub.D is coupled to the second input of the detector cell 106.sub.D.

[0024] In the illustrated example of FIG. 1A, the first input of the adder 110.sub.A is coupled to the first output of the detector cell 106.sub.A and the second input of the adder 110.sub.A is coupled to the first output of the detector cell 106.sub.B. In the example of FIG. 1A, the output of the adder 110.sub.A is coupled to the first input of the adder 114.sub.A. Also, the first input of the adder 110.sub.B is coupled to the second output of the detector cell 106.sub.A and the second input of the adder 110.sub.B is coupled to the second output of the detector cell 106.sub.B. In the example of FIG. 1A, the output of the adder 110.sub.B is coupled to the first input of the adder 114.sub.B. In examples where the SDLA 100 does not include the stage 102.sub.C, the stage 102.sub.D, the adder 112.sub.A, the adder 112.sub.B, the adder 114.sub.A, and the adder 114.sub.B, the output of the adder 110.sub.A is coupled to the first input of the filter 104 and the output of the adder 110.sub.B is coupled to the second input of the filter 104.

[0025] In the illustrated example of FIG. 1A, the first input of the adder 112.sub.A is coupled to the first output of the detector cell 106.sub.C and the second input of the adder 112.sub.A is coupled to the first output of the detector cell 106.sub.D. In the example of FIG. 1A, the output of the adder 112.sub.A is coupled to the second input of the adder 114.sub.A. Also, the first input of the adder 112.sub.B is coupled to the second output of the detector cell 106.sub.C and the second input of the adder 112.sub.B is coupled to the second output of the detector cell 106.sub.D. In the example of FIG. 1A, the output of the adder 112.sub.B is coupled to the second input of the adder 114.sub.B.

[0026] In the illustrated example of FIG. 1A, the first input of the adder 114.sub.A is coupled to the output of the adder 110.sub.A and the second input of the adder 114.sub.A is coupled to the output of the adder 112.sub.A. In the example of FIG. 1A, the output of the adder 114.sub.A is coupled to the first input of the filter 104. Also, the first input of the adder 114.sub.B is coupled to the output of the adder 110.sub.B and the second input of the adder 114.sub.B is coupled to the output of the adder 112.sub.B. In the example of FIG. 1A, the output of the adder 114.sub.B is coupled to the second input of the filter 104.

[0027] In the illustrated example of FIG. 1A, the first input of the filter 104 is coupled to the output of the adder 114.sub.A and the second input of the filter 104 is coupled to the output of the adder 114.sub.B. As described above, in examples where the SDLA 100 does not include the stage 102.sub.C, the stage 102.sub.D, the adder 112.sub.A, the adder 112.sub.B, the adder 114.sub.A, and the adder 114.sub.B, the first input of the filter 104 is coupled to the output of the adder 110.sub.A and the second input of the filter 104 is coupled to the output of the adder 110.sub.B. In the example of FIG. 1A, the first output of the filter 104 is coupled to the output 118.sub.A. In the example of FIG. 1A, the second output of the filter 104 is coupled to the output 118.sub.B.

[0028] In the illustrated example of FIG. 1A, the SDLA 100 receives an input signal V.sub.IN at the input 116.sub.A and the input 116.sub.B and produces an output signal V.sub.OUT at the output 118.sub.A and the output 118.sub.B. For example, the input signal V.sub.IN is measured between the input 116.sub.A, which receives a positive input signal V.sub.IN+, and the input 116.sub.B, which receives a negative input signal V.sub.IN. Also, for example, the output signal V.sub.OUT is measured between the output 118.sub.A and the output 118.sub.B.

[0029] In the illustrated example of FIG. 1A, the stage 102.sub.A does not apply a gain to the input signal V.sub.IN. In the example of FIG. 1A, each of the stage 102.sub.B, the stage 102.sub.C, and the stage 102.sub.D applies a gain of A to an input signal. As such, the output signal from the stage 102.sub.B has an amplitude of A*V.sub.IN, the output signal from the stage 102.sub.C has an amplitude of A.sup.2*V.sub.IN, and the output signal from the stage 102.sub.D has an amplitude of A.sup.3*V.sub.IN.

[0030] In the illustrated example of FIG. 1A, each of the detector cell 106.sub.A, the detector cell 106.sub.B, the detector cell 106.sub.C, and the detector cell 106.sub.D rectifies an input signal. For example, if the input signal V.sub.IN is an alternating current (AC) signal, then the detector cell 106.sub.A rectifies the negative portion of the AC signal to positive values effectively converting the AC signal to a direct current (DC) signal. Also, each of the detector cell 106.sub.A, the detector cell 106.sub.B, the detector cell 106.sub.C, and the detector cell 106.sub.D saturates at a saturated voltage V.sub.L depending on the voltage of an input signal.

[0031] In the illustrated example of FIG. 1A, the adder 110.sub.A and the adder 110.sub.B sum the differential output signal from the detector cell 106.sub.A and the differential output signal from the detector cell 106.sub.B. In the example of FIG. 1A, the adder 112.sub.A and the adder 112.sub.B sum the differential output signal from the detector cell 106.sub.C and the differential output signal from the detector cell 106.sub.D. Also, the adder 114.sub.A sums the output signals from the adder 110.sub.A and the adder 112.sub.A and the adder 114.sub.B sums the output signals from the adder 110.sub.B and the adder 112.sub.B.

[0032] In the illustrated example of FIG. 1A, depending on the amplitude of the input signal V.sub.IN, the SDLA 100 amplifies the input signal V.sub.IN differently. For example, if the input signal V.sub.IN has a small amplitude, then each of the stage 102.sub.B, the stage 102.sub.C, and the stage 102.sub.D are active and the gain, A.sup.3, of the stage 102.sub.D dominates the overall transfer function of the SDLA 100. Accordingly, if the input signal V.sub.IN has a small amplitude, then each of the detector cell 106.sub.A, the detector cell 106.sub.B, the detector cell 106.sub.C, and the detector cell 106.sub.D may not saturate.

[0033] In the illustrated example of FIG. 1A, if the input signal V.sub.IN has a large amplitude, one or more detector cells of the SDLA 100 may saturate at the saturated voltage V.sub.L. Accordingly, if the input signal V.sub.IN has a large amplitude, then one or more of the detector cell 106.sub.A, the detector cell 106.sub.B, the detector cell 106.sub.C, or the detector cell 106.sub.D may saturate one after another. Saturation of one or more of the detector cell 106.sub.A, the detector cell 106.sub.B, the detector cell 106.sub.C, or the detector cell 106.sub.D would reduce the gain of the SDLA 100 by a factor of A after each saturation.

[0034] For example, assuming the last stage of the SDLA 100, for example, the stage 102.sub.D, is saturated, then the output voltage signal V.sub.OUT of the SDLA 100 is defined in Equation 1 below.

[00001]$\begin{array}{cc}{V}_{\mathrm{OUT}}=V_L+\frac{V_L}{A}+\frac{V_L}{A^2}+\frac{V_L}{A^3}& \mathrm{Equation}1\end{array}$

[0035] As such, for a factor of A increase in the magnitude of the input signal V.sub.IN, the magnitude of the output signal V.sub.OUT increases by the saturated voltage V.sub.L. For example, for a factor of A increase in the magnitude of the input signal V.sub.IN, then the output voltage signal V.sub.OUT of the SDLA 100 is defined in Equation 2 below.

[00002]$\begin{array}{cc}{V}_{\mathrm{OUT}}=2*V_L+\frac{V_L}{A}+\frac{V_L}{A^2}& \mathrm{Equation}2\end{array}$

[0036] As such, for a constant increase, for example by A, in the input signal V.sub.IN, the SDLA 100 has a constant increment, for example by V.sub.L, in the output signal V.sub.OUT, or, in other words, there is a logarithmic relationship between the input signal V.sub.IN and the output signal V.sub.OUT. In the example of FIG. 1A, the filter 104 is a low-pass filter that receives the differential output signal from the adder 114.sub.A and the adder 114.sub.B. As such, the filter 104 produces an average signal of the logarithm of the input signal V.sub.IN. For example, the average signal of the logarithm of the input signal V.sub.IN may be referred to as a DC signal of the logarithm of the input signal V.sub.IN.

[0037] While SDLAs are widely used to measure signal strength in different applications, one drawback of SDLAs is the tradeoff between logarithmic conformance error (LCE), minimum input detectability, dynamic range (DR), and the power consumption. LCE is a measure of how closely the transfer function of an SDLA conforms to a logarithmic function. A lower LCE indicates that the transfer function of an SDLA closely conforms to a logarithmic function. Minimum input detectability refers to the smallest signal that an SDLA can detect. The minimum input detectability of an SDLA is defined with respect to an LCE threshold. For example, the LCE of an SDLA being below the LCE threshold ensures that a target input detectability is achieved. DR refers to the range of input signal magnitudes over which an SDLA can accurately produce an output signal that is proportional to the logarithm of the input signal.

[0038] For an SDLA having N amplifier stages each with gain A, the DR of the SDLA is A.sup.N. As such, for a given number of amplifier stages, N, in an SDLA, the DR is proportional to the gain, A, per amplifier stage of the SDLA. Also, for a given number of amplifier stages, N, in an SDLA, the LCE of the SDLA is proportional to the gain, A, per amplifier stage of the SDLA.

[0039] FIG. 1B is a block diagram of the SDLA 100 of FIG. 1A with differential inputs and a single ended output. In the example of FIG. 1B, the detector cell 106.sub.A, the detector cell 106.sub.B, the detector cell 106.sub.C, the detector cell 106.sub.D, the amplifier 108.sub.B, the amplifier 108.sub.C, and the amplifier 108.sub.D are implemented and operate similarly as described in FIG. 1A but that the detector cell 106.sub.A, the detector cell 106.sub.B, the detector cell 106.sub.C, and the detector cell 106.sub.D have one output instead of two outputs. For example, in FIG. 1B, the output signals provided the detector cell 106.sub.A, the detector cell 106.sub.B, the detector cell 106.sub.C, and the detector cell 106.sub.D are measured with respect to a ground terminal instead of between the first outputs and the second outputs of the detector cell 106.sub.A, the detector cell 106.sub.B, the detector cell 106.sub.C, and the detector cell 106.sub.D.

[0040] As such, the adder 110.sub.B, the adder 112.sub.B, and the adder 114.sub.B can be omitted, which can save space when the SDLA 100 is implemented in silicon. In the example of FIG. 1B, the adder 110.sub.A, the adder 112.sub.A, the adder 114.sub.A, and the filter 104 are implemented and operate similarly as described in FIG. 1A but that the filter 104 has one input and one output instead of two inputs and two outputs. For example, in FIG. 1B, the output signal provided the filter 104 is measured with respect to a ground terminal instead of between the first output and the second output of the filter 104.

[0041] FIG. 2A is a graphical illustration of an example graph 200 depicting a relationship between DR of an SDLA and the gain, A, of each amplifier stage of the SDLA. In the example of FIG. 2A, the graph 200 depicts output voltage signal, also referred to as V.sub.OUT, in volts (V) versus input voltage signal, also referred to as V.sub.IN, in decibel (dB) voltage scale (dBV). FIG. 2B is a graphical illustration of an example graph 202 depicting a relationship between LCE of an SDLA and the gain, A, of each amplifier stage of the SDLA. In the example of FIG. 2B, the graph 202 depicts output voltage signal, also referred to as V.sub.OUT, in volts versus input voltage signal, also referred to as V.sub.IN, in dBV.

[0042] In the illustrated example of FIG. 2A, the graph 200 includes a first example plot 204.sub.A depicting input voltage signal versus output voltage signal of an SDLA with a gain, A, of five in each amplifier stage of the SDLA. In the example of FIG. 2A, the graph 200 includes a second example plot 204.sub.B depicting input voltage signal versus output voltage signal of an ideal SDLA with a gain, A, of five in each amplifier stage of the ideal SDLA. Also, the graph 200 includes a third example plot 206.sub.A depicting input voltage signal versus output voltage signal of an SDLA with a gain, A, of 10 in each amplifier stage of the SDLA. In the example of FIG. 2A, the graph 200 includes a fourth example plot 206.sub.B depicting input voltage signal versus output voltage signal of an ideal SDLA with a gain, A, of 10 in each amplifier stage of the ideal SDLA. As illustrated in FIG. 2A, by increasing the gain per amplifier stage from 5 to 10, the DR of an SDLA can be increased by about 22 dB.

[0043] In the illustrated example of FIG. 2B, the graph 202 includes a first example plot 208 depicting input voltage signal versus LCE of an SDLA with a gain, A, of five in each amplifier stage of the SDLA. In the example of FIG. 2B, the graph 202 includes a second example plot 210 depicting input voltage signal versus LCE of an SDLA with a gain, A, of 10 in each amplifier stage of the SDLA. In the example of FIG. 2B, the graph 202 includes a first example LCE threshold 212 within which the SDLA of the plot 208 operates and a second example LCE threshold 214 within which the SDLA of the plot 210 operates. For example, the LCE threshold 212 is 1 dB and the LCE threshold 214 is 3 dB.

[0044] In the illustrated example of FIG. 2B, the width and height of the lobes of the plot 208 and the plot 210 are indicative of the LCE of the respective SDLAs. For example, a thinner and shorter lobe indicates a lower LCE which indicates that an SDLA can achieve reduced granularity of logarithmic approximation. As illustrated in FIG. 2B, the width and height of a first example lobe 216 of the plot 208 are lower than the width and height of a second example lobe 218 of the plot 210. As such, by decreasing the gain per amplifier stage from 10 to 5, the LCE of an SDLA can be decreased. Thus, if a designer desires to reduce the LCE of an SDLA, one way would be to reduce the gain, A, of each amplifier stage of the SDLA. However, as illustrated in FIG. 2A, reducing the gain, A, of each amplifier stage of an SDLA also reduces the DR of the SDLA. As such, a designer can achieve better LCE at the cost of DR.

[0045] Also, if a designer desires to increase the minimum input detectability of an SDLA, one way would be to reduce the LCE of the SDLA around the target minimum input signal. However, if the LCE of an SDLA is reduced by reducing the gain, A, of each amplifier stage of the SDLA, the DR of the SDLA will also be reduced as illustrated in FIGS. 2A and 2B. As such, if a designer wants to maintain the same DR of an SDLA while also reducing the LCE of the SDLA, one way would be to increase the number of amplifier stages, N, of the SDLA. However, increasing the number of amplifier stages, N, of an SDLA would consume more area on a chip and consume more power. Some approaches to improve SDLAs have focused on improving the amplifier stages of an SDLA. For example, if each amplifier stage has a lower noise floor, then an SDLA can include a greater number of amplifier stages to achieve a targeted dynamic range while also achieving detectability of a target minimum input signal.

[0046] Examples described herein include a detector cell architecture that improves detector cell non-linearity to improve the LCE of an SDLA for a given gain, A, per amplifier stage of the SDLA without compromising on DR, area consumption on chip, power consumption, or minimum input detectability. Described examples include a detector cell architecture with a linear transfer function that results in the overall piecewise transfer function of an SDLA very closely conforming to a non-linear, logarithmic function. As such, described examples reduce LCE of an SDLA.

[0047] FIG. 3 is a schematic of an example detector cell 300 in conjunction with examples described herein. In the example of FIG. 3, the detector cell 300 includes a first example current source 302, a first example transistor 304 (Q.sub.1), a second example current source 306, a first example current mirror 308, a second example transistor 310 (Q.sub.2), a third example current source 312, a second example current mirror 314, and an example load resistor 316. Also, the detector cell 300 of FIG. 3 has a first example voltage terminal 318, a second example voltage terminal 320, a first example input 322, a second example input 324, a first example output 326, and a second example output 328. In some examples, the voltage terminal 318 is referred to as a ground terminal and the voltage terminal 320 is referred to as a supply terminal.

[0048] In the illustrated example of FIG. 3, the input 322 receives a positive input signal V.sub.IN+, the input 324 receives a negative input signal V.sub.IN, the output 326 provides a positive output signal V.sub.OUT+, and the output 328 provides a negative output signal V.sub.OUT. In the example of FIG. 3, the current mirror 308 includes a first example resistor 330, a second example resistor 332, a third example transistor 334 (Q.sub.3), and a fourth example transistor 336 (Q.sub.4). Also, the current mirror 314 includes a third example resistor 340, a fourth example resistor 342, a fifth example transistor 344 (Q.sub.5), and a sixth example transistor 346 (Q.sub.6).

[0049] In the illustrated example of FIG. 3, each of the current source 302, the current source 306, and the current source 312 has an input and an output. In some examples, one or more of the current source 302, the current source 306, or the current source 312 is referred to as a current source circuit. In the example of FIG. 3, each of the transistor 304, the transistor 310, the transistor 334, the transistor 336, the transistor 344, and the transistor 346 has a control terminal, a first terminal, and a second terminal. In some examples, the control terminal, the first terminal, and the second terminal of a transistor are referred to as a base terminal, a collector terminal, and an emitter terminal. Also, each of the load resistor 316, the resistor 330, the resistor 332, the resistor 340, and the resistor 342 has a first terminal and a second terminal. In the example of FIG. 3, each of the current mirror 308 and the current mirror 314 has a first output, a second output, and a supply input.

[0050] In the illustrated example of FIG. 3, the current source 302 is implemented by at least analog circuitry. For example, the current source 302 is implemented by a bipolar junction transistor (BJT) such as a negative-positive-negative (NPN) BJT. In some examples, the current source 302 is implemented by a field-effect transistor (FET) such as an n-channel metal-oxide-semiconductor (NMOS) FET, also referred to as a negative-channel metal-oxide-semiconductor field-effect transistor. In the example of FIG. 3, the input of the current source 302 is coupled to the second terminal of the transistor 304 and the second terminal of the transistor 310. Also, the output of the current source 302 is coupled to the voltage terminal 318.

[0051] In the illustrated example of FIG. 3, the transistor 304 is implemented by a BJT such as an NPN BJT, also referred to as a negative-positive-negative bipolar junction transistor. In some examples, the transistor 304 is implemented by a FET such as an NMOS FET, also referred to as a negative-channel MOSFET. In the example of FIG. 3, the control terminal of the transistor 304 is coupled to the input 322. Also, the first terminal of the transistor 304 is coupled to the output of the current source 306 and the first terminal of the transistor 334, which operates as the first output of the current mirror 308. In the example of FIG. 3, the second terminal of the transistor 304 is coupled to the input of the current source 302.

[0052] In the illustrated example of FIG. 3, the current source 306 is implemented by at least analog circuitry. For example, the current source 306 is implemented by a BJT such as a positive-negative-positive (PNP) BJT with a saturation protection clamp. In some examples, the current source 306 is implemented by a FET such as a p-channel metal-oxide-semiconductor (PMOS) FET, also referred to as a positive-channel metal-oxide-semiconductor field-effect transistor. In the example of FIG. 3, the input of the current source 306 is coupled to the voltage terminal 320. Also, the output of the current source 306 is coupled to the first terminal of the transistor 304 and the first terminal of the transistor 334, which operates as the first output of the current mirror 308.

[0053] In the illustrated example of FIG. 3, the supply input of the current mirror 308, for example, the first terminal of the resistor 330 and the first terminal of the resistor 332, is coupled to the voltage terminal 320. In the example of FIG. 3, the first output of the current mirror 308, for example, the first terminal of the transistor 334, is coupled to the first terminal of the transistor 304 and the output of the current source 306. Also, the second output of the current mirror 308, for example, the first terminal of the transistor 336, is coupled to the first terminal of the load resistor 316 and the output 326.

[0054] In the illustrated example of FIG. 3, the first terminal of the resistor 330, which operates as the supply input of the current mirror 308, is coupled to the voltage terminal 320. In the example of FIG. 3, the second terminal of the resistor 330 is coupled to the second terminal of the transistor 334. Also, the first terminal of the resistor 332, which operates as the supply input of the current mirror 308, is coupled to the voltage terminal 320. In the example of FIG. 3, the second terminal of the resistor 332 is coupled to the second terminal of the transistor 336.

[0055] In the illustrated example of FIG. 3, the transistor 334 is implemented by a BJT such as a PNP BJT, also referred to as a positive-negative-positive bipolar junction transistor. In some examples, the transistor 334 is implemented by a FET such as a PMOS FET, also referred to as a positive-channel MOSFET. In the example of FIG. 3, the control terminal of the transistor 334 is coupled to the first terminal of the transistor 334, the first terminal of the transistor 304, the output of the current source 306, and the control terminal of the transistor 336. Also, the first terminal of the transistor 334, which operates as the first output of the current mirror 308, is coupled to the control terminal of the transistor 334, the first terminal of the transistor 304, the output of the current source 306, and the control terminal of the transistor 336. In the example of FIG. 3, the second terminal of the transistor 334 is coupled to the second terminal of the resistor 330.

[0056] In the illustrated example of FIG. 3, the transistor 336 is implemented by a BJT such as a PNP BJT, also referred to as a positive-negative-positive BJT. In some examples, the transistor 336 is implemented by a FET such as a PMOS FET. In the example of FIG. 3, the control terminal of the transistor 336 is coupled to the control terminal of the transistor 334, the first terminal of the transistor 334, the first terminal of the transistor 304, and the output of the current source 306. Also, the first terminal of the transistor 336, which operates as the second output of the current mirror 308, is coupled to the first terminal of the load resistor 316 and the output 326. In the example of FIG. 3, the second terminal of the transistor 336 is coupled to the second terminal of the resistor 332.

[0057] In the illustrated example of FIG. 3, the transistor 310 is implemented by a BJT such as an NPN BJT, also referred to as a negative-positive-negative BJT. In some examples, the transistor 310 is implemented by a FET such as an NMOS FET. In the example of FIG. 3, the control terminal of the transistor 310 is coupled to the input 324. Also, the first terminal of the transistor 310 is coupled to the output of the current source 312 and the first terminal of the transistor 346, which operates as the first output of the current mirror 314. In the example of FIG. 3, the second terminal of the transistor 310 is coupled to the input of the current source 302.

[0058] In the illustrated example of FIG. 3, the current source 312 is implemented by at least analog circuitry. For example, the current source 312 is implemented by a BJT such as a PNP BJT with a saturation protection clamp. In some examples, the current source 312 is implemented by a FET such as a PMOS FET. In the example of FIG. 3, the input of the current source 312 is coupled to the voltage terminal 320. Also, the output of the current source 312 is coupled to the first terminal of the transistor 310 and the first terminal of the transistor 346, which operates as the first output of the current mirror 314.

[0059] In the illustrated example of FIG. 3, the supply input of the current mirror 314, for example, the first terminal of the resistor 340 and the first terminal of the resistor 342, is coupled to the voltage terminal 320. In the example of FIG. 3, the first output of the current mirror 314, for example, the first terminal of the transistor 346, is coupled to the first terminal of the transistor 310 and the output of the current source 312. Also, the second output of the current mirror 314, for example, the first terminal of the transistor 344, is coupled to the first terminal of the load resistor 316 and the output 326.

[0060] In the illustrated example of FIG. 3, the first terminal of the resistor 342, which operates as the supply input of the current mirror 314, is coupled to the voltage terminal 320. In the example of FIG. 3, the second terminal of the resistor 342 is coupled to the second terminal of the transistor 346. Also, the first terminal of the resistor 340, which operates as the supply input of the current mirror 314, is coupled to the voltage terminal 320. In the example of FIG. 3, the second terminal of the resistor 340 is coupled to the second terminal of the transistor 344.

[0061] In the illustrated example of FIG. 3, the transistor 346 is implemented by a BJT such as a PNP BJT. In some examples, the transistor 346 is implemented by a FET such as a PMOS FET. In the example of FIG. 3, the control terminal of the transistor 346 is coupled to the first terminal of the transistor 346, the first terminal of the transistor 310, the output of the current source 312, and the control terminal of the transistor 344. Also, the first terminal of the transistor 346, which operates as the first output of the current mirror 314, is coupled to the control terminal of the transistor 346, the first terminal of the transistor 310, the output of the current source 312, and the control terminal of the transistor 344. In the example of FIG. 3, the second terminal of the transistor 346 is coupled to the second terminal of the resistor 342.

[0062] In the illustrated example of FIG. 3, the transistor 344 is implemented by a BJT such as a PNP BJT. In some examples, the transistor 344 is implemented by a FET such as a PMOS FET. In the example of FIG. 3, the control terminal of the transistor 344 is coupled to the control terminal of the transistor 346, the first terminal of the transistor 346, the first terminal of the transistor 310, and the output of the current source 312. Also, the first terminal of the transistor 344, which operates as the second output of the current mirror 314, is coupled to the first terminal of the load resistor 316 and the output 326. In the example of FIG. 3, the second terminal of the transistor 344 is coupled to the second terminal of the resistor 340.

[0063] In the illustrated example of FIG. 3, the load resistor 316 represents a load of the detector cell 300. For example, the load resistor 316 is a resistive load. In some examples, the load of the detector cell 300 is at least one of an inductive load, a capacitive load, or a resistive load. In the example of FIG. 3, the first terminal of the load resistor 316 is coupled to the first terminal of the transistor 336, which operates as the second output of the current mirror 308, the first terminal of the transistor 344, which operates as the second output of the current mirror 314, and the output 326. Also, the second terminal of the load resistor 316 is coupled to the output 328. In some examples, such as in an SDLA with a single ended output such as the SDLA 100 of FIG. 1B, the output 328 is coupled to the voltage terminal 318. As such, in such examples, the second terminal of the load resistor 316 is coupled to the voltage terminal 318.

[0064] In the illustrated example of FIG. 3, the output current signal I.sub.OUT from the detector cell 300 is defined in Equation 3 below.

[00003]$\begin{array}{cc}{I}_{\mathrm{OUT}}=l_O*\frac{1-e^{-\frac{V_{\mathrm{IN}}}{V_t}}}{2*\left(1+e^{\frac{V_{\mathrm{IN}}}{V_t}}\right)}& \mathrm{Equation}3\end{array}$

[0065] In Equation 3, I.sub.O represents the current set by the current source 302, V.sub.IN represents the voltage of an input signal V.sub.IN (measured between the input 322 and the input 324) to the detector cell 300, and V.sub.t represents the thermal voltage of the transistor 304 and the transistor 310. In the example of FIG. 3, the current through the transistor 304, I.sub.C1, is defined according to Equation 4 below and the current through the transistor 310, I.sub.C2, is defined according to Equation 5 below.

[00004]$\begin{array}{cc}{I}_{C1}=\frac{I_O}{1+e^{-\frac{V_{\mathrm{IN}}}{V_t}}}& \mathrm{Equation}4\end{array}$$\begin{array}{cc}{I}_{C2}=\frac{I_O}{1+e^{-\frac{V_{\mathrm{IN}}}{V_t}}}& \mathrm{Equation}5\end{array}$

[0066] Also, in the illustrated example of FIG. 3, the current through the transistor 334, I.sub.1, is defined according to Equation 6 below and the current through the transistor 346, I.sub.2, is defined according to Equation 7 below.

[00005]$\begin{array}{cc}{I}_1=I_{C1}-\frac{I_O}{2}& \mathrm{Equation}6\end{array}$$\begin{array}{cc}{I}_2=I_{C2}-\frac{I_O}{2}& \mathrm{Equation}7\end{array}$

[0067] As such, in example operation, when the voltage at the input 322, V.sub.IN+, and the voltage at the input 324, V.sub.IN, are equal, then the current through the transistor 304, I.sub.C1, and the current through the transistor 310, I.sub.C2, will be equal to half of the current set by the current source 302. For example, I.sub.C1=I.sub.C2=I.sub.O/2. Also, when the voltage at the input 322, V.sub.IN+, is greater than the voltage at the input 324, V.sub.IN, then (1) the current through the transistor 304, I.sub.C1, is equal to the sum of half of the current set by the current source 302 and a delta and (2) the current through the transistor 310, I.sub.C2, is equal to the difference between half of the current set by the current source 302 and the delta. I.sub.C1=I.sub.O/2+I and I.sub.C2=I.sub.O/2I. For example, there is a positive differential voltage between the input 322 and the input 324, in other words, V.sub.IN is positive, when the voltage at the input 322 is greater than the voltage at the input 324.

[0068] In example operation, when the voltage at the input 322, V.sub.IN+, is greater than the voltage at the input 324, V.sub.IN, then the current through the transistor 304 is greater than the current through the transistor 310, I.sub.C1>I.sub.C2). For example, there is a positive differential voltage between the input 322 and the input 324, in other words, V.sub.IN is positive, when the voltage at the input 322, V.sub.IN+, is greater than the voltage at the input 324, V.sub.IN. As such, if the voltage at the input 322, V.sub.IN+, is greater than the voltage at the input 324, V.sub.IN, then the voltage at the first terminal of the transistor 310 will move to the voltage at the voltage terminal 320 and the current mirror 314 will be disabled. As such, the current through the transistor 304, I.sub.C1, will be approximately equal to the current set by the current source 302, I.sub.C1=I.sub.O and I.sub.C2=0.

[0069] Equation 8 below defines the current through the transistor 334, I.sub.1, when the voltage at the input 322, V.sub.IN+, is greater than the voltage at the input 324, V.sub.IN.

[00006]$\begin{array}{cc}\begin{array}{c}{I}_1=\frac{I_O}{1+e^{\frac{V_{\mathrm{IN}}}{V_t}}}-\frac{I_O}{2}\\ I_1=\frac{I_O*\left(1-e^{-\frac{V_{\mathrm{IN}}}{V_t}}\right)}{2*\left(1+e^{-\frac{V_{\mathrm{IN}}}{V_t}}\right)}\end{array}& \mathrm{Equation}8\end{array}$

[0070] Equation 9 below defines the current through the transistor 334, I.sub.1, when the voltage at the input 322, V.sub.IN+, between the input 324, V.sub.IN, is much less than the thermal voltage V.sub.t of the transistor 304 and the transistor 310, V.sub.IN<<V.sub.t.

[00007]$\begin{array}{cc}{I}_1=\frac{I_O*\frac{V_{\mathrm{IN}}}{V_t}}{2*\left(2-\frac{V_{\mathrm{IN}}}{V_t}\right)}=\frac{I_O*\frac{V_{\mathrm{IN}}}{V_t}}{\frac{4*V_t-2*V_{\mathrm{IN}}}{V_t}}& \mathrm{Equation}9\end{array}$

[0071] As such, when the input voltage signal, V.sub.IN, becomes much less than the terminal voltage V.sub.t of the transistor 304 and the transistor 310, for example, for low magnitude input voltage signals, the current through the transistor 334, I.sub.1, is defined according to Equation 10 below. Also, when the input voltage signal, V.sub.IN, becomes much less than the terminal voltage V.sub.t of the transistor 304 and the transistor 310, for example, for low magnitude input voltage signals, the output current signal, I.sub.OUT, from the detector cell 300 is defined according to Equation 11 below. As illustrated in Equation 11, when the voltage at the input 322, V.sub.IN+, between the input 324, V.sub.IN, is much less than the thermal voltage V.sub.t of the transistor 304 and the transistor 310, V.sub.IN<<V.sub.t, the output current signal, I.sub.OUT, is proportional to the input voltage signal, V.sub.IN.

[00008]$\begin{array}{cc}{I}_1=I_O*\frac{V_{\mathrm{IN}}}{4*V_t}& \mathrm{Equation}10\end{array}$$\begin{array}{cc}{I}_{\mathrm{OUT}}=I_1=I_O*\frac{V_{\mathrm{IN}}}{4*V_t}& \mathrm{Equation}11\end{array}$

[0072] Equation 12 below defines the output current signal, I.sub.OUT, from the detector cell 300 when the voltage at the input 322, V.sub.IN+, between the input 324, V.sub.IN, is much greater than the thermal voltage V.sub.t of the transistor 304 and the transistor 310, V.sub.IN>>V.sub.t.

[00009]$\begin{array}{cc}{I}_{\mathrm{OUT}}=I_1=\frac{I_O}{2}& \mathrm{Equation}12\end{array}$

[0073] Thus, in example operation, when the voltage of the input signal V.sub.IN to the detector cell 300 is zero, V.sub.IN=0, the output current signal from the detector cell 300 is near zero, I.sub.OUT0. As such, the voltage of an output signal V.sub.OUT (measured between the output 326 and the output 328) from the detector cell 300 is approximately zero, V.sub.OUT0, when the voltage of the input signal V.sub.IN is zero. Also, in example operation, when the absolute value of the voltage of the input signal V.sub.IN to the detector cell 300 is greater than two times the thermal voltage V.sub.t, |V.sub.IN|>2*V.sub.t, then the current through the transistor 304, I.sub.C1, or the current through the transistor 310, I.sub.C2, will dominate and the voltage of the output signal V.sub.OUT from the detector cell 300 is equal to the product of half the current set by the current source 302 and the resistance of the load resistor 316, V.sub.OUT=I.sub.O/2*R.sub.L.

[0074] FIG. 4 is a graphical illustration of an example graph 400 depicting an example transfer function 402 of the detector cell 300 of FIG. 3. In the example of FIG. 4, the transfer function 402 represents the output voltage signal, V.sub.OUT, from the detector cell 300 in volts as a function of the input voltage signal, V.sub.IN, to the detector cell 300 in volts. Also, the transfer function 402 includes an example linear region 404 in which there is a linear dependence of the output voltage signal, V.sub.OUT, on the input voltage signal, V.sub.IN, for small input voltage signals, for example, V.sub.IN=[0.8, 0.8]. In the example of FIG. 4, the transfer function 402 includes an example saturation voltage 406, V.sub.K, at which the detector cell 300 saturates as described above.

[0075] As illustrated in FIG. 4, when the voltage at the input 322, V.sub.IN+, is less than the voltage at the input 324, V.sub.IN, then the current through the transistor 304 is less than the current through the transistor 310, I.sub.C1<I.sub.C2. For example, there is a negative differential voltage between the input 322 and the input 324, in other words, V.sub.IN is negative, when the voltage at the input 322, V.sub.IN+, is less than the voltage at the input 324, V.sub.IN. If the voltage at the input 322, V.sub.IN+, is less than the voltage at the input 324, V.sub.IN, then the voltage at the first terminal of the transistor 304 will move to the voltage at the voltage terminal 320 and the current mirror 308 will be disabled.

[0076] As such, the current through the transistor 310, I.sub.C2, will be approximately equal to the current set by the current source 302, I.sub.C2=I.sub.O and I.sub.C1=0. Because the direction of the output current signal, I.sub.OUT, remains consistent, regardless of whether the current mirror 308 or the current mirror 314 is active, whether the input voltage signal, V.sub.IN, is positive or negative), the output voltage signal, V.sub.OUT, remains positive, for example, rectifying the input voltage signal, V.sub.IN. As illustrated in FIG. 4, regardless of how large the absolute value of the input voltage signal, V.sub.IN, is, the output voltage signal, V.sub.OUT, does not exceed, in other words, the output voltage signal, V.sub.OUT, saturates at, the product of half the current set by the current source 302 and the resistance of the load resistor 316, V.sub.OUT=I.sub.O/2*R.sub.L.

[0077] Returning to FIG. 3, as described above, in some examples, the current source 302, the transistor 304, the current source 306, the transistor 310, the current source 312, the transistor 334, the transistor 336, the transistor 344, and the transistor 346 are implemented by BJTs. For example, if the current source 302 is implemented by an NPN BJT, then the current source 306 and the current source 312 are implemented by PNP BJTs with saturation protection clamps, the transistor 304 and the transistor 310 are implemented by NPN BJTs, and the transistor 334, the transistor 336, the transistor 344, and the transistor 346 are implemented by PNP BJTs. In such examples, the transfer function of the detector cell 300 is similar to that shown in FIG. 4.

[0078] Also, as described above, in some examples, the current source 302, the transistor 304, the current source 306, the transistor 310, the current source 312, the transistor 334, the transistor 336, the transistor 344, and the transistor 346 are implemented by FETs. For example, if the current source 302 is implemented by an NMOS FET, then the current source 306 and the current source 312 are implemented by PMOS FETs, the transistor 304 and the transistor 310 are implemented by NMOS FETs, and the transistor 334, the transistor 336, the transistor 344, and the transistor 346 are implemented by PMOS FETs. In such examples, the transfer function of the detector cell 300 is similar to that shown in FIG. 4, but the detector cell 300 saturates less abruptly than illustrated in FIG. 4. For example, the output voltage signal V.sub.OUT may still increase for a limited range of input voltage signals greater than the saturation voltage 406.

[0079] As such, implementing at least the transistor 304 and the transistor 310 as BJTs can reduce the LCE of an SDLA utilizing the detector cell 300 as compared to implementing at least the transistor 304 and the transistor 310 as FETs. Also, implementing at least the transistor 304 and the transistor 310 as BJTs can improve the minimum input detectability of an SDLA utilizing the detector cell 300 as compared to implementing at least the transistor 304 and the transistor 310 as FETs. However, as described above, implementing at least the transistor 304 and the transistor 310 as FETs provides a transfer function similar to that shown in FIG. 4, but the detector cell 300 saturates less abruptly than illustrated in FIG. 4.

[0080] In the illustrated example of FIG. 3, the transistor 304 and the transistor 310 are NPN BJTs. Alternatively, the transistor 304 and the transistor 310 may be n-channel FETs, n-channel metal-oxide semiconductor field-effect transistors (MOSFETs), n-channel insulated-gate bipolar transistors (IGBTs), n-channel junction field effect transistors (JFETs), or, with slight modifications, p-type equivalent devices. In the example of FIG. 3, the transistor 334, the transistor 336, the transistor 344, and the transistor 346 are PNP BJTs. Alternatively, the transistor 334, the transistor 336, the transistor 344, and the transistor 346 may be p-channel FETs, p-channel MOSFETs, p-channel IGBTs, p-channel JFETs, or, with slight modifications, N-type equivalent devices.

[0081] The transistor 304, the transistor 310, the transistor 334, the transistor 336, the transistor 344, and the transistor 346 may be depletion mode devices, drain-extended devices, enhancement mode devices, natural transistors, or other type of device structure transistors. Furthermore, the transistor 304, the transistor 310, the transistor 334, the transistor 336, the transistor 344, and the transistor 346 may be implemented in/over a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate or a gallium arsenide (GaAs) substrate. Also, in some examples, one or more of the components of any of FIG. 1A, 1B, or 3 is implemented by at least one of analog or digital circuitry.

[0082] FIG. 5A is a graphical illustration of an example graph 500 depicting a relationship between a degree of a detector cell and LCE of an SDLA. In the example of FIG. 5A, the graph 500 depicts output voltage signal, V.sub.OUT, in volts versus input voltage signal, V.sub.IN, in volts. FIG. 5B is a graphical illustration of an example graph 502 depicting a relationship between a degree of a detector cell and DR of an SDLA. In the example of FIG. 5B, the graph 502 depicts output voltage signal, V.sub.OUT, in volts versus input voltage signal, V.sub.IN, in dBV. FIG. 5C is a graphical illustration of an example graph 504 depicting a relationship between the transfer function of a detector cell and a degree of the detector cell. In the example of FIG. 5C, the graph 504 depicts output voltage signal, V.sub.OUT, in volts versus input voltage signal, V.sub.IN, in volts.

[0083] In the illustrated example of FIGS. 5A, 5B, and 5C, the degree of a detector cell refers to the mathematical relationship between the input voltage signal and the output voltage signal of the detector cell before saturation. In the example of FIG. 5A, the graph 500 includes a first example plot 506 depicting output voltage signal versus input voltage signal of an SDLA having an ideal logarithmic relationship between the input voltage signal and the output voltage signal. Also, the graph 500 includes a second example plot 508 depicting output voltage signal versus input voltage signal of an SDLA including a detector cell with a degree of two. In the example of FIG. 5A, the graph 500 includes a third example plot 510 depicting output voltage signal versus input voltage signal of an SDLA including a detector cell, for example, the detector cell 300 of FIG. 3, with a degree of one. Also, the graph 500 includes a fourth example plot 512 depicting output voltage signal versus input voltage signal of an SDLA including a detector cell with a degree of 0.5. In the example of FIG. 5A, as the degree of a detector cell decreases, the piecewise approximation of a logarithmic function by an SDLA having the detector cell improves. As such, as the degree of a detector cell decreases, the LCE of an SDLA having the detector cell decreases.

[0084] In the illustrated example of FIG. 5B, the graph 502 includes a first example plot 514 depicting output voltage signal versus input voltage signal of an SDLA having an ideal logarithmic relationship between the input voltage signal and the output voltage signal. Also, the graph 502 includes a second example plot 516 depicting output voltage signal versus input voltage signal of an SDLA including a detector cell with a degree of two. In the example of FIG. 5B, the graph 502 includes a third example plot 518 depicting output voltage signal versus input voltage signal of an SDLA including a detector cell, for example, the detector cell 300 of FIG. 3, with a degree of one. Also, the graph 502 includes a fourth example plot 520 depicting output voltage signal versus input voltage signal of an SDLA including a detector cell with a degree of 0.5. In the example of FIG. 5B, as the degree of a detector cell decreases, the detector cell can detect smaller signals above an example noise floor 522 of the detector cell. As such, as the degree of a detector cell decreases, the dynamic range of an SDLA having the detector cell increases.

[0085] In the illustrated example of FIG. 5C, the graph 504 includes a first example plot 524 depicting output voltage signal versus input voltage signal of an SDLA including a detector cell with a degree of three. Also, the graph 504 includes a second example plot 526 depicting output voltage signal versus input voltage signal of an SDLA including a detector cell with a degree of two. In the example of FIG. 5C, the graph 504 includes a third example plot 528 depicting output voltage signal versus input voltage signal of an SDLA including a detector cell, for example, the detector cell 300 of FIG. 3, with a degree of one. Also, the graph 504 includes a fourth example plot 530 depicting output voltage signal versus input voltage signal of an SDLA including a detector cell with a degree of 0.5.

[0086] In the illustrated example of FIG. 5C, the graph 504 includes an example non-saturation region 532 in which the detector cells of the plot 524, the plot 526, the plot 528, and the plot 530 are not saturated. In the example of FIG. 5C, the output voltage signal of a detector cell is defined as illustrated in Equation 13 below.

[00010]$\begin{array}{cc}{V}_{\mathrm{OUT}}=V_L*{\left(\frac{V_{\mathrm{IN}}}{V_K}\right)}^N& \mathrm{Equation}13\end{array}$

[0087] In Equation 13, V.sub.OUT represents the output voltage signal of a detector cell, V.sub.IN represents the input voltage signal to the detector cell, V.sub.K represents an example saturation voltage 534 at which the detector cell saturates, V.sub.L represents an example saturated voltage 536 for the detector cell, and N represents a degree of the detector cell. As illustrated in FIG. 5C, as the degree of a detector cell decreases, the gain of the detector cell increases for input voltage signals around the center of the non-saturation region 532 and the gain of the detector cell decreases at the edge of the non-saturation region 532. Table 1 below illustrates the LCE of an SDLA in dB and minimum detectable input signal of the SDLA in microvolts (V) at the LCE for a detector cell at different degrees. In Table 1, the values correspond to an SDLA where the gain, A, of each amplifier stage of the SDLA is 10, the saturation voltage V.sub.K is 200 millivolts (mV), and the saturated voltage V.sub.L is 200 mV.

TABLE-US-00001 TABLE 1 Minimum Input Signal N LCE (dB) Detectable 2 3.8 21 V (5 dB) 1 2 16 V (5 dB) 0.5 1.33 9 V (5 dB)

[0088] As illustrated in FIGS. 5A, 5B, and 5C, as the degree of a detector cell decreases, the LCE of an SDLA including the detector cell reduces and the DR of the SDLA including the detector cell increases. Thus, a detector cell, such as the detector cell 300 of FIG. 3, having a degree of one provides a linear transfer function in the non-saturation region 532 while also improving the LCE and DR of an SDLA including the detector cell.

[0089] Table 2 below illustrates the LCE and DR of an SDLA when utilizing the detector cell 300 of FIG. 3 and the LCE and DR of the SDLA when utilizing another detector cell. In Table 2, the other detector cell has a degree of two. As described above, the detector cell 300 of FIG. 3 has a degree of one. In Table 2, the values correspond to an SDLA with a fixed number of amplifier stages, the same gain, A, in each amplifier stage, a fixed noise floor, and a fixed quiescent current, I.sub.Q. As illustrated in Table 2, the minimum input detectability of the SDLA improves by 6 dB in peak voltage (V.sub.P) and the LCE of the SDLA reduces by 0.6 dB for the same quiescent current when utilizing the detector cell 300 of FIG. 3, with a degree of one, as compared to the other detector cell, with a degree of two.

TABLE-US-00002 TABLE 2 Specification Detector Cell 300 Other Detector Cell I.sub.Q 3.7 milliamps (mA) 3.7 mA LCE 0.5 dB 1.1 dB Input Signal Range 14 V.sub.P-2 V.sub.P (2 dB) 28 V.sub.P-2 V.sub.P (2 dB) Dynamic Range 100 dB (1 dB) 94 dB (1 dB) 103 dB (2 dB) 97 dB (2 dB)

[0090] Table 3 below illustrates the quiescent current of an SDLA when utilizing the detector cell 300 of FIG. 3 and the quiescent current of the SDLA when utilizing another detector cell. In Table 3, the other detector cell has a degree of two. As described above, the detector cell 300 of FIG. 3 has a degree of one. In Table 3, the values for the detector cell 300 correspond to an SDLA with four amplifier stages, a gain, A, of 10 in each amplifier stage, and a quiescent current, I.sub.Q, of 1.56 mA. Also, in the Table 3, the values for the other detector cell correspond to an SDLA with five amplifier stages, a gain, A, of 6.7 in each amplifier stage, and a quiescent current, I.sub.Q, of 2.64 mA, which is a two times reduction in quiescent current, I.sub.Q. As illustrated in Table 3, the quiescent current of an SDLA improves by 1.08 mA for the same LCE and DR when utilizing the detector cell 300 of FIG. 3, with a degree of one, as compared to the other detector cell, with a degree of two.

TABLE-US-00003 TABLE 3 Specification Detector Cell 300 Other Detector Cell I.sub.Q 1.56 mA 2.64 mA LCE 0.5 dB 0.5 dB Input Signal Range 20 V.sub.P-2 V.sub.P (1 dB) 20 V.sub.P-2 V.sub.P (2 dB) Dynamic Range 100 dB (1 dB) 100 dB (1 dB)

[0091] While an example manner of implementing the detector cell 300 of FIG. 3 is illustrated in FIG. 3, one or more of the elements, processes, or devices illustrated in FIG. 3 may be combined, divided, re-arranged, omitted, eliminated, or implemented in any other way. Further, the example detector cell 300 of FIG. 3, may be implemented by hardware alone or by hardware in combination with software and firmware. Thus, for example, the example detector cell 300 of FIG. 3, could be implemented by programmable circuitry in combination with one or more machine-readable instructions, for example, firmware or software, processor circuitry, analog circuit(s), digital circuit(s), logic circuit(s), programmable processor(s), programmable microcontroller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), ASIC(s), programmable logic device(s) (PLD(s)), or field programmable logic device(s) (FPLD(s)) such as FPGAs. Further still, the example detector cell 300 of FIG. 3 may include one or more elements, processes, or devices in addition to, or instead of, those illustrated in FIG. 3, or may include more than one of any or all of the illustrated elements, processes, and devices.

[0092] Including and comprising (and all forms and tenses thereof) are used herein to be open ended terms. Thus, whenever a claim employs any form of include or comprise as a preamble or within a claim recitation of any kind, additional elements, terms, etc., may be present without falling outside the scope of the corresponding claim or recitation. Examples forms of include and comprise include comprise, include, comprises, includes, comprising, including, having, etc. As used herein, when the phrase at least is used as the transition term in, for example, a preamble of a claim, it is open-ended in the same manner as the term comprising and including are open ended. As used herein in the context of describing structures, components, items, objects and things, the phrase at least one of A and B refers to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects and things, the phrase at least one of A or B refers to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase at least one of A and B refers to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase at least one of A or B refers to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0093] As used herein, singular references do not exclude a plurality. Examples of singular references include a, an, first, second, etc. The term a or an object, as used herein, refers to one or more of that object. The terms a (or an), one or more, and at least one are used interchangeably herein. Furthermore, although individually listed, a plurality of means, elements, or actions may be implemented by, for example, the same entity or object. Also, although individual features may be included in different examples or claims, these may possibly be combined, and the inclusion in different examples or claims does not imply that a combination of features is at least one of not feasible or advantageous.

[0094] As used herein, connection references, for example, attached, coupled, connected, and joined, may include intermediate members between the elements referenced by at least one of the connection reference or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected or in fixed relation to each other.

[0095] Unless specifically stated otherwise, descriptors such as first, second, third, etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, or ordering in any way, but are merely used as at least one of labels or arbitrary names to distinguish elements for ease of understanding the described examples. In some examples, the descriptor first may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as second or third. In such instances, such descriptors are used merely for identifying those elements distinctly within the context of the discussion, for example, within a claim, in which the elements might, for example, otherwise share a same name.

[0096] As used herein, the phrase in communication, including variations thereof, encompasses one of or a combination of direct communication or indirect communication through one or more intermediary components, and does not require direct physical, for example, wired, communication or constant communication, but rather also includes selective communication at least one of periodic intervals, scheduled intervals, aperiodic intervals, or one-time events.

[0097] As used herein, programmable circuitry is defined to include at least one of (i) one or more special purpose electrical circuits, for example, an application specific circuit (ASIC), structured to perform specific operation(s) and including one or more semiconductor-based logic devices, for example, electrical hardware implemented by one or more transistors, or (ii) one or more general purpose semiconductor-based electrical circuits programmable with instructions to perform one or more specific functions(s) or operation(s) and including one or more semiconductor-based logic devices, for example, electrical hardware implemented by one or more transistors. Examples of programmable circuitry include programmable microprocessors such as Central Processor Units (CPUs) that may execute first instructions to perform one or more operations or functions, Field Programmable Gate Arrays (FPGAs) that may be programmed with second instructions to at least one of configure or structure the FPGAs to instantiate one or more operations or functions corresponding to the first instructions, Graphics Processor Units (GPUs) that may execute first instructions to perform one or more operations or functions, Digital Signal Processors (DSPs) that may execute first instructions to perform one or more operations or functions, XPUs, Network Processing Units (NPUs) one or more microcontrollers that may execute first instructions to perform one or more operations or functions or integrated circuits such as Application Specific Integrated Circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system including multiple types of programmable circuitry, for example, one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and any combination(s) thereof, and orchestration technology, for example, application programming interface(s) (API(s), that may assign computing task(s) to whichever one(s) of the multiple types of programmable circuitry is/are suited and available to perform the computing task(s).

[0098] As used herein integrated circuit/circuitry is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system on chip (SoC), etc.

[0099] In this description, the term couple may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0100] A device that is configured to perform a task or function may be configured, for example, at least one of programmed or hardwired, at a time of manufacturing by a manufacturer to at least one of perform the function or be configurable (or re-configurable) by a user after manufacturing to perform the function/or other additional or alternative functions. The configuring may be through at least one of firmware or software programming of the device, through at least one of a construction or layout of hardware components and interconnections of the device, or a combination thereof.

[0101] As used herein, the terms terminal, node, interconnection, pin and lead are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronics or semiconductor component.

[0102] In the description and claims, described circuitry may include one or more circuits. A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as one of or a combination of resistors, capacitors, or inductors), or one or more sources (such as voltage or current sources) may instead include only the semiconductor elements within a single physical device, for example, at least one of a semiconductor die or integrated circuit (IC) package, and may be adapted to be coupled to at least some of the passive elements or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by at least one of an end-user or a third-party.

[0103] Circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in at least one of series or parallel to provide an amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor. While certain elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated. As used herein, the term integrated circuit means one or more circuits that are at least one of: (i) incorporated in/over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; or (iv) incorporated in/on the same printed circuit board.

[0104] Uses of the phrase ground in the foregoing description include at least one of a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, or any other form of ground connection applicable to, or suitable for, the teachings of this description. As used herein, approximately and about modify their subjects/values to recognize the potential presence of variations that occur in real world applications. For example, approximately and about may modify dimensions that may not be exact due to at least one of manufacturing tolerances or other real-world imperfections. Unless otherwise stated, about, approximately, or substantially preceding a value means +/10 percent of the stated value, or, if the value is zero, a reasonable range of values around zero.

[0105] Modifications are possible in the described examples, and other examples are possible, within the scope of the claims.

[0106] From the foregoing, it will be appreciated that example systems, apparatus, articles of manufacture, and methods have been described that reduce the LCE of a logarithmic amplifier, improve minimum input detectability of a logarithmic amplifier, and increase the dynamic range of a logarithmic amplifier. For example, described detector cells have a linear transfer function, for example, as opposed to a non-linear transfer function. By implementing a detector cell with a linear transfer function to improve conformance to a non-linear, logarithmic function of a logarithmic amplifier, examples described herein reduce the LCE of the logarithmic amplifier for a given gain, A, per amplifier stage without compromising on dynamic range of the logarithmic amplifier, area consumption by the logarithmic amplifier on chip, power consumption of the logarithmic amplifier, or minimum input detectability of the logarithmic amplifier.

[0107] Also, by improving LCE of a logarithmic amplifier as described herein, the gain, A, per amplifier stage of the logarithmic amplifier can be increased while attaining the same LCE as other approaches. As such, the number of amplifier stages, N, of a logarithmic amplifier can be reduced while attaining the same dynamic range as other approaches. Described examples reduce the number of amplifier stages, N, of a logarithmic amplifier by 20% and reduce the quiescent current of the logarithmic amplifier by 40% while attaining the same minimum input detectability and dynamic range as other approaches. Also, described examples improve the minimum input detectability by two times as compared to other approaches and facilitate two times the dynamic range while attaining the same area and power consumption as other approaches. Described systems, apparatus, articles of manufacture, and methods improve the efficiency of using a computing device by reducing the area and power consumption of a logarithmic amplifier.

[0108] Described systems, apparatus, articles of manufacture, and methods are also directed to one or more improvement(s) in the operation of a machine such as a computer or other electronic, electromechanical, or mechanical device.