CMOS frequency reference circuit with temperature coefficient cancellation

Abstract

Systems and methods for frequency reference generation are described. In an embodiment, a frequency reference circuit, includes: a bandgap proportional to temperature (PTAT) generator circuit that generates a bandgap PTAT current; a resistor complementary to temperature (CTAT) generator circuit that generates a resistor CTAT current; an adder that adds the PTAT current and the CTAT current to generate a constant current I.sub.cons; a switched-resistor (switched-R) circuit that receives the constant current I.sub.cons and a previously generated output clock and generates an output; a bandgap voltage reference generator circuit that generates a bandgap voltage V.sub.BG; an integrator circuit that receives the output of the switched-R circuit and the bandgap voltage V.sub.BG and generates an output; and a voltage-controlled oscillator (VCO) circuit that receives the output of the integrator circuit and generates a frequency reference.

Claims

1. A frequency reference circuit, comprising: a bandgap proportional to temperature (PTAT) generator circuit that generates a bandgap PTAT current; a resistor complementary to temperature (CTAT) generator circuit that generates a resistor CTAT current; an adder that adds the PTAT current and the CTAT current to generate a constant current I.sub.cons; a switched-resistor (switched-R) circuit that receives the constant current I.sub.cons and a previously generated output clock and generates an output; a bandgap voltage reference generator circuit that generates a bandgap voltage V.sub.BG; an integrator circuit that receives the output of the switched-R circuit and the bandgap voltage V.sub.BG and generates an output; and a voltage-controlled oscillator (VCO) circuit that receives the output of the integrator circuit and generates a frequency reference.

2. The frequency reference circuit of claim 1, wherein the bandgap PTAT and resistor CTAT currents are given by: $I_{\mathrm{PTAT}}=\frac{k.Math.T.Math.\ln \left(N\right)}{q.Math.R},I_{\mathrm{CTAT}}=\frac{V_{\mathrm{BG}}}{\beta R}$ where β is ratio of resistors used in the bandgap PTAT generator circuit, N is ratio of areas of two bipolar transistors used in the bandgap PTAT generator circuit, k is Boltzmann constant, q is the charge of an electron and V.sub.BG is the bandgap voltage.

3. The frequency reference circuit of claim 1, wherein the bandgap PTAT current and the resistor CTAT currents are added together to generate the constant current I.sub.cons by: $I_{\mathrm{cons}}=\frac{V_{\mathrm{BG}}}{\beta .Math.R_0}.\frac{1+\frac{\beta .Math.k.Math.T.Math.\ln \left(N\right)}{q.Math.V_{\mathrm{BG}}}}{1+\alpha .Math.T}$ such that the resistor temperature coefficient (α) is equated to $\frac{\beta .Math.k.Math.\ln \left(N\right)}{q.Math.V_{\mathrm{BG}}},$ such that the current is constant with temperature, and wherein I.sub.cons is independent of process, voltage, and temperature variations.

4. The frequency reference circuit of claim 1, wherein the switch-R circuit further comprises two capacitors that are ping ponged at a frequency f that is generated by the VCO.

5. The frequency reference circuit of claim 4, wherein a voltage generated by the switched-R circuit is constantly compared with V.sub.BG, and an error signal is generated and is integrated and fed as a control signal to the VCO, wherein the VCO frequency sweeps until the error signal reaches zero.

6. The frequency reference circuit of claim 5, wherein the frequency is given by: $f=\frac{1}{2.Math.\beta .Math.R_0.Math.C_{\mathrm{mos}}}$ wherein the frequency temperature coefficient depends on capacitor C.sub.mos temperature coefficient.

7. The frequency reference circuit of claim 1, wherein the bandgap voltage reference generator circuit includes an opamp.

8. The frequency reference circuit of claim 7, wherein a current mismatch error in a bandgap current mirror is addressed by Dynamic Element Matching.

9. A method of generating a reference frequency, comprising: generating a bandgap PTAT current using a bandgap proportional to temperature (PTAT) generator circuit; generating a resistor CTAT current using a resistor complementary to temperature (CTAT) generator circuit; adding the PTAT current and the CTAT current to generate a constant current I.sub.cons using an adder; receiving the constant current I.sub.cons and a previously generated output clock and generating an output using a switched-resistor (switched-R); generating a bandgap voltage V.sub.BG using a bandgap voltage reference generator; receiving the output of the switched-R circuit and the bandgap voltage V.sub.BG and generating an output using an integrator circuit; and receiving the output of the integrator circuit and generating a frequency reference using a voltage-controlled oscillator (VCO) circuit.

10. The method of claim 9, wherein the bandgap PTAT and resistor CTAT currents are given by: $I_{\mathrm{PTAT}}=\frac{k.Math.T.Math.\ln \left(N\right)}{q.Math.R},I_{\mathrm{CTAT}}=\frac{V_{\mathrm{BG}}}{\beta R}$ where β is ratio of resistors used in the bandgap PTAT generator circuit, N is ratio of areas of two bipolar transistors used in the bandgap PTAT generator circuit, k is Boltzmann constant, q is the charge of an electron and V.sub.BG is the bandgap voltage.

11. The method of claim 9, wherein the bandgap PTAT current and the resistor CTAT currents are added together to generate the constant current I.sub.cons by: $I_{\mathrm{cons}}=\frac{V_{\mathrm{BG}}}{\beta .Math.R_0}.\frac{1+\frac{\beta .Math.k.Math.T.Math.\ln \left(N\right)}{q.Math.V_{\mathrm{BG}}}}{1+\alpha .Math.T}$ such that the resistor temperature coefficient (α) is equated to $\frac{\beta .Math.k.Math.\ln \left(N\right)}{q.Math.V_{\mathrm{BG}}},$ such that the current is constant with temperature, and wherein I.sub.cons is independent of process, voltage, and temperature variations.

12. The method of claim 9, wherein the switch-R circuit further comprises two capacitors that are ping ponged at a frequency f that is generated by the VCO.

13. The method of claim 12, wherein a voltage generated by the switched-R circuit is constantly compared with V.sub.BG, and an error signal is generated and is integrated and fed as a control signal to the VCO, wherein the VCO frequency sweeps until the error signal reaches zero.

14. The method of claim 13, wherein the frequency is given by: $f=\frac{1}{2.Math.\beta .Math.R_0.Math.C_{\mathrm{mos}}}$ wherein the frequency temperature coefficient depends on capacitor C.sub.mos temperature coefficient.

15. The method of claim 9, wherein the bandgap voltage reference generator circuit includes an opamp.

16. The method of claim 15, wherein a current mismatch error in a bandgap current mirror is addressed by Dynamic Element Matching.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 conceptually illustrates a frequency reference circuit within a system-on-chip (SoC), capable of providing a frequency reference to various circuits within the SoC in accordance with an embodiment of the invention.

(2) FIG. 2 is a circuit diagram of a CMOS frequency reference circuit with temperature coefficient cancellation in accordance with an embodiment of the invention.

(3) FIG. 3 is a flow diagram of a method for temperature compensated frequency reference generation in accordance with an embodiment of the invention.

(4) FIG. 4 is a schematic circuit diagram of a CMOS frequency reference circuit with temperature coefficient cancellation in accordance with an embodiment of the invention.

(5) FIG. 5 illustrates a top-level layout of a CMOS frequency reference circuit with temperature coefficient cancellation in accordance with an embodiment of the invention.

(6) FIG. 6 shows a test bench schematic circuit of a CMOS frequency reference circuit with temperature coefficient cancellation in accordance with an embodiment of the invention.

(7) FIG. 7 shows results of simulations of a CMOS frequency reference circuit with temperature coefficient cancellation.

(8) FIG. 8 shows zoomed in results of simulations of a CMOS frequency reference circuit with temperature coefficient cancellation.

(9) FIG. 9 illustrates performance of a CMOS frequency reference circuit with temperature coefficient cancellation in comparison to previously reported frequency references.

DETAILED DESCRIPTION OF THE DRAWINGS

(10) Turning now to the drawings, CMOS frequency reference circuits with temperature coefficient cancellation in accordance with various embodiments of the invention are illustrated. In many embodiments, a CMOS frequency reference circuit can be implemented using direct integration of on-chip oscillators, which can provide for a fully integrated system-on-chip (SoC), thus reducing overall device volume and costs. In this way, CMOS frequency reference circuit with temperature coefficient cancellation can be utilized within a variety of circuits and systems including (but not limited to) phase locked loop (PLL) circuits.

(11) Existing on-chip frequency references may employ look-up table methods or voltage ratio techniques, where extensive post-silicon trimming can be required in order to achieve stability of the frequency reference over temperature variations. As can readily be appreciated, such techniques can increase the time and cost associated with fabrication due to the additional expense of performing the requisite trimming processes. Furthermore, the resulting circuits can have a temperature coefficient of 100 ppm/° C. As is discussed further below, CMOS frequency reference circuits with temperature coefficient cancellation implemented in accordance with various embodiments of the invention can achieve significantly lower temperature coefficients (e.g. 12 ppm/° C.).

(12) In many embodiments, a CMOS frequency reference circuit with temperature coefficient cancellation can convert a constant current to a frequency reference by utilizing a frequency locked loop (FLL). In several embodiments, a CMOS frequency reference circuit with temperature coefficient cancellation can be implemented using active circuits including a bandgap voltage reference used in a proportional to temperature (PTAT) circuit, an integrator circuit, a voltage-controlled oscillator (VCO) circuit, and passive circuits including a switched resistor (switched-R) circuit and a complimentary to temperature (CTAT) circuit. In a number of embodiments, the CMOS frequency reference circuit with temperature coefficient cancellation can generate PTAT and CTAT currents. In several embodiments, the PTAT and CTAT currents are utilized to generate a constant current. In many embodiments, a CMOS frequency reference circuit with temperature coefficient cancellation can also employ a bandgap voltage reference generator to obtain a low temperature coefficient. In certain embodiments, CTAT and PTAT currents can be generated and added together to generate a constant current. In various embodiments, the constant current and a previously generated output clock signal can be fed into a switched-R circuit. The output of the switched-R circuit can be input into an integrator circuit. The output of the integrator circuit can be fed into a VCO, where a frequency reference is generated. In many embodiments, the CMOS frequency reference circuit with temperature coefficient cancellation can be fabricated using a 180 nm CMOS process technology. Various CMOS frequency reference circuits with temperature coefficient cancellation and applications in accordance with certain embodiments of the invention are discussed further below.

(13) Frequency Reference Circuits

(14) Frequency reference circuits can be utilized within a system-on-chip (SoC). A circuit diagram of a SoC 100 in accordance with an embodiment of the invention is illustrated in FIG. 1. In the illustrated embodiment, a frequency reference circuit 102 can provide a frequency reference 110 to different circuits (104, 106, 108) within the SoC 100. In the SOC 100, the frequency of the generated reference signal can have a predetermined level of frequency stability as a function of temperature. In many embodiments, implementations of frequency reference circuits can achieve low temperature coefficients (e.g. 12 ppm/° C.).

(15) In several embodiments, the frequency reference circuit can be utilized for many different purposes, including but not limited to providing a stable frequency reference to a microprocessor, a microcontroller, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), and/or clocking an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a sampled-data filter, a discrete-time analog signal processor, and/or to circuits used in RF applications. As can readily be appreciated, frequency reference circuits can be utilized in any of a variety of applications in accordance with various embodiments of the invention. In many embodiments, an on-chip frequency reference circuit can be utilized to fabricate a fully integrated SoC, thus reducing overall device volume and costs.

(16) Although various frequency reference circuits are described above with reference to FIG. 1, any of a variety of frequency references may be utilized as appropriate to the requirements of specific applications in accordance with various embodiments of the invention. Sub-circuits of CMOS frequency reference circuits with temperature coefficient cancellation are discussed further below.

(17) In several embodiments, a CMOS frequency reference circuit with temperature coefficient cancellation can include a PTAT circuit, a CTAT circuit, a switched-R circuit, an integrator circuit, and a VCO circuit. A circuit diagram of a CMOS frequency reference circuit with temperature coefficient cancellation 200 in accordance with an embodiment of the invention is illustrated in FIG. 2. In the illustrated embodiment, bandgap PTAT 204 and resistor CTAT 202 currents can be generated and added together in a summing node 206 to generate a constant current 214. In various embodiments, the constant current 214 and a previously generated output clock 216 can be fed into a switched-R circuit 208. The output of the switched-R circuit 218 and a bandgap voltage 220 can be input into an integrator circuit 210. The output of the integrator circuit 210 can be fed into a VCO 212, where a frequency reference is generated.

(18) In the illustrated embodiment, bandgap PTAT and resistor CTAT currents are given by:

(19) $I_{\mathrm{PTAT}}=\frac{k.Math.T.Math.\ln \left(N\right)}{q.Math.R},I_{\mathrm{CTAT}}=\frac{V_{\mathrm{BG}}}{\beta R}$
where β is ratio of resistors used in the bandgap circuit 204, N is ratio of areas of two bipolar transistors used in the bandgap circuit 204, k is Boltzmann constant, q is the charge of an electron and V.sub.BG is bandgap voltage. The bandgap PTAT and the resistor CTAT currents are added together to generate a constant current I.sub.cons:

(20) $I_{\mathrm{cons}}=\frac{V_{\mathrm{BG}}}{\beta .Math.R_0}.\frac{1+\frac{\beta .Math.k.Math.T.Math.\ln \left(N\right)}{q.Math.V_{\mathrm{BG}}}}{1+\alpha .Math.T}$
By equating resistor temperature coefficient (α) to

(21) $\frac{\beta .Math.k.Math.\ln \left(N\right)}{q.Math.V_{\mathrm{BG}}},$
the current will be constant with temperature. Thus, I.sub.cons is

(22) $\frac{V_{\mathrm{BG}}}{\beta .Math.R_0},$
which is independent of process, voltage, and temperature variations.

(23) In certain embodiments, there can be two capacitors in the switched-R circuit that are ping ponged at a frequency f, generated by VCO 212. The voltage generated by the switched-R circuit 208 is constantly compared with V.sub.BG, and the error signal generated is integrated and fed as control signal to VCO 212. The VCO frequency keeps sweeping until the error signal reaches zero. The frequency is given by:

(24) $f=\frac{1}{2.Math.\beta .Math.R_0.Math.C_{\mathrm{mos}}}$
The factor 2 is due to time interleaved capacitors in the switched-R circuit. Thus, the frequency temperature coefficient depends on capacitor C.sub.mos temperature coefficient.

(25) Although various CMOS frequency reference circuits with temperature coefficient cancellation are described above with reference to FIG. 2, any of a variety of CMOS frequency reference circuits with temperature coefficient cancellation may be utilized as appropriate to the requirements of specific applications in accordance with various embodiments of the invention. Methods of generating a frequency reference with temperature coefficient cancellation are discussed further below.

(26) A method for temperature compensated frequency reference generation in accordance with an embodiment of the invention is illustrated in FIG. 3. The method 300 includes generating (302) a PTAT current. A CTAT current is generated (304). The PTAT current and the CTAT currents can be added to generate (306) a constant current I.sub.cons. The I.sub.cons and an output clock can be fed (308) into a switched-R circuit. An output of the switched-R circuit and a bandgap voltage V.sub.bg can be fed (310) into an integrator. The output of the integrator can be fed (312) into a VCO. The VCO can generate (314) a frequency reference.

(27) Although various flow diagrams of methods for temperature compensated frequency reference generation are described above with reference to FIG. 3, any of a variety of methods for temperature compensated frequency reference generation may be utilized as appropriate to the requirements of specific applications in accordance with various embodiments of the invention. Detailed simulation of frequency reference circuits are discussed further below.

(28) Cadence circuit simulator (Cadence Design Systems Inc, San Jose, Calif.) can be utilized to simulate the performance of CMOS frequency reference circuits with temperature coefficient cancellation. Cadence simulation circuits of a CMOS frequency reference circuit with temperature coefficient cancellation are shown in FIG. 4. In the illustrated figure, a circuit schematic 400 of a CMOS frequency reference circuit with temperature coefficient cancellation is shown. The circuit schematic 400 includes a bandgap voltage and a constant current generator 404. Further, circuit schematic 400 includes circuit schematics for a switched-R circuit 402, an integrator 406, an oscillator 408, and decoders 410. The bandgap voltage generator within circuit 404 includes an opamp 420. In existing solutions, one of the sources of error in a bandgap circuit can be an opamp offset, and current mismatch. Existing solutions address bandgap opamp offset by employing chopping techniques, which can draw 1/fC noise from the bandgap core. Further chopping can create tones and can reduce signal gain. In certain embodiments, CMOS frequency reference circuits with temperature coefficient cancellation can operate without chopping of the input differential pair of the bandgap opamp 420. The current mismatch error in the bandgap current mirror can be addressed by Dynamic Element Matching. Though the differential pair offset can still remain, its temperature coefficient can be kept zero.

(29) Although various circuit schematics for CMOS frequency reference circuits with temperature coefficient cancellation are described above with reference to FIG. 4, any of a variety of circuit schematics may be utilized as appropriate to the requirements of specific applications in accordance with various embodiments of the invention. Circuit layouts are discussed further below.

(30) Cadence circuit layout simulator can be utilized to simulate the performance of CMOS frequency reference circuits with temperature coefficient cancellation using extracted values for all circuit parameters. Cadence circuit layout of a CMOS frequency reference circuit with temperature coefficient cancellation is shown in FIG. 5. In the illustrated figure, the layout of a CMOS frequency reference circuit with temperature coefficient cancellation includes a bandgap, a relaxation oscillator, an integrator, and a switched-R circuit. In many embodiments, the layout of a CMOS frequency reference circuit with temperature coefficient cancellation can be fabricated in many fabrication process technologies (e.g. 28 nm CMOS process). Simulation results are discussed further below.

(31) Cadence circuit simulator can be utilized to simulate the performance of CMOS frequency reference circuits with temperature coefficient cancellation. Cadence simulation test circuit of a CMOS frequency reference circuit with temperature coefficient cancellation is shown in FIG. 6. In the illustrated figure, the CMOS frequency reference is shown along with power (Vdd) and ground nodes. The simulation results for the frequency reference of the circuit schematic of FIG. 6 are shown in FIG. 7. As shown in FIG. 7, an output clock of a CMOS frequency reference circuit with temperature coefficient cancellation circuit is plotted as a function of time. The CMOS frequency reference circuit with temperature coefficient cancellation circuit can achieve a locking of the output clock within a short period of time (e.g. 10 us). In FIG. 8, a zoomed-in plot of the output clock of FIG. 7 is shown for time around 25 us, where it can be seen a stable operation of the frequency reference.

(32) A CMOS frequency reference circuit with temperature coefficient cancellation can achieve a temperature coefficient of, for example, 12 ppm/° C. FIG. 9 table illustrates performance of a CMOS frequency reference circuit with temperature coefficient cancellation in accordance with an embodiment of the invention compared to previously reported frequency references. In the illustrated table, a figure-of-merit (FOM) of the various circuits is shown, where the FOM is defined as:

(33) 0$\mathrm{FOM}=\frac{\mathrm{freq}}{P_{DC}\mathrm{Tempco}}$
where freq is an operating frequency of the circuit, P.sub.Dc is a power consumption of the circuit, and Tempco is a temperature coefficient of the circuit.

(34) While the above descriptions and associated figures have depicted a CMOS frequency reference circuit with temperature coefficient cancellation, it should be clear that any of a variety of configurations for CMOS frequency reference circuits with temperature coefficient cancellation can be implemented in accordance with embodiments of the invention. More generally, although the present invention has been described in certain specific aspects, many additional modifications and variations would be apparent to those skilled in the art. It is therefore to be understood that the present invention may be practiced otherwise than specifically described. Thus, embodiments of the present invention should be considered in all respects as illustrative and not restrictive.