Circuit arrangement of an amplifier with current controlled gain and corresponding method

Abstract

In accordance with an embodiment, a variable gain amplifier includes: a first differential transistor pair coupled to a signal input; a first current source configured to provide a first bias current to the first differential transistor pair; a pair of diodes coupled to an output of the first differential transistor pair; a second differential transistor pair having an input coupled to the pair of diodes; a second current source configured to provide a second bias current to the second differential transistor pair; and a current control circuit coupled to the first current source and the second current source.

Claims

1. A circuit, comprising: a variable gain amplifier comprising: a first differential transistor pair coupled to a signal input, a first current source configured to provide a first bias current to the first differential transistor pair, a pair of diodes coupled to an output of the first differential transistor pair, a second differential transistor pair having an input coupled to the pair of diodes, a second current source configured to provide a second bias current to the second differential transistor pair, and a current control circuit coupled to a first reference current input, a second reference current input, the first current source and the second current source, the current control circuit configured to cause a common-mode output current of the pair of diodes to be substantially equal to a first reference current provided at the first reference current input, and a common-mode output current of the second differential transistor pair to be substantially equal to a sum of the first reference current and a second reference current provided at the second reference current input.

2. The circuit of claim 1, further comprising a reference current generator coupled to the first reference current input and the second reference current input and configured to provide the first reference current and the second reference current to the current control circuit, to control a gain of the variable gain amplifier by modifying the first reference current and the second reference current, and to keep the sum of the first reference current and the second reference current constant over a plurality of gain settings.

3. The circuit of claim 2, wherein the reference current generator comprises a digital-to-analog converter (DAC).

4. The circuit of claim 3, wherein the DAC is a differential DAC having a first differential output configured to provide the first reference current and a second differential output configured to provide the second reference current.

5. The circuit of claim 1, wherein the second differential transistor pair comprises a plurality of bipolar transistors.

6. The circuit of claim 5, further comprising a base current compensation circuit configured to recover and compensate base currents of the plurality of bipolar transistors.

7. The circuit of claim 6, wherein the base current compensation circuit comprises, for each respective bipolar transistor of the plurality of bipolar transistors: a supporting bipolar transistor; and control loop coupled to the supporting bipolar transistor and the respective bipolar transistor, the control loop circuitry comprising: a first current mirror having an input coupled to a collector of the respective bipolar transistor, and an output coupled to a collector of the supporting bipolar transistor, and a second current mirror having an input coupled to a base of the supporting bipolar transistor and an output coupled to a base of the respective bipolar transistor.

8. The circuit of claim 5, wherein the pair of diodes comprises a plurality of diode-connected transistors.

9. The circuit of claim 1, wherein the first differential transistor pair comprises a resistor degenerated MOSFET differential pair.

10. The circuit of claim 9, wherein each differential branch of the first differential transistor pair comprises an amplifier having an output coupled to a gate of a respective MOSFET of the resistor degenerated MOSFET differential pair, a first input coupled to a source of the respective MOSFET, and a second input coupled to a corresponding input of the signal input.

11. The circuit of claim 1, wherein the current control circuit comprises an output-stage control loop configured for controlling the second current source to regulate the common-mode output current of the pair of diodes.

12. The circuit of claim 1, wherein the current control circuit comprises an input-stage control loop configured for controlling the first current source to regulate the common-mode output current of the pair of diodes to be substantially equal to the first reference current.

13. An ultrasonic obstacle detector having a receiver comprising: a variable gain amplifier comprising: a first differential transistor pair coupled to a signal input, a first current source configured to provide a first bias current to the first differential transistor pair, a pair of diodes coupled to an output of the first differential transistor pair, a second differential transistor pair having an input coupled to the pair of diodes, a second current source configured to provide a second bias current to the second differential transistor pair, and a current control circuit coupled to a first reference current input, a second reference current input, the first current source and the second current source, the current control circuit configured to cause a common-mode output current of the pair of diodes to be substantially equal to a first reference current provided at the first reference current input, and a common-mode output current of the second differential transistor pair to be substantially equal to a sum of the first reference current and a second reference current provided at the second reference current input; and a reference current generator coupled to the first reference current input and the second reference current input and configured to provide the first reference current and the second reference current to the current control circuit, to control a gain of the variable gain amplifier by modifying the first reference current and the second reference current, and to keep the sum of the first reference current and the second reference current constant over a plurality of gain settings.

14. The ultrasonic obstacle detector of claim 13, wherein: the second differential transistor pair comprises a plurality of bipolar transistors; and the pair of diodes comprises a plurality of diode-connected transistors.

15. The ultrasonic obstacle detector of claim 14, wherein the first differential transistor pair comprises a resistor degenerated MOSFET differential pair.

16. The ultrasonic obstacle detector of claim 13, wherein the reference current generator comprises a digital-to-analog converter (DAC) having a first differential output configured to provide the first reference current and a second differential output configured to provide the second reference current.

17. The ultrasonic obstacle detector of claim 13, wherein the current control circuit comprises: an output-stage control loop configured for controlling the second current source to regulate the common-mode output current of the pair of diodes; and an input-stage control loop configured for controlling the first current source to regulate the common-mode output current of the pair of diodes to be substantially equal to the first reference current.

18. A method for operating a variable gain amplifier comprising a first differential transistor pair coupled to a signal input, a first current source configured to provide a first bias current to the first differential transistor pair, a pair of diodes coupled to an output of the first differential transistor pair, a second differential transistor pair having an input coupled to the pair of diodes, and a second current source configured to provide a second bias current to the second differential transistor pair, the method comprising: causing a common-mode output current of the pair of diodes to be substantially equal to a first reference current by adjusting a current of the first current source; causing a common-mode output current of the second differential transistor pair to be substantially equal to a sum of the first reference current and a second reference current by adjusting a current of the second current source; and adjusting a gain of the variable gain amplifier by adjusting the first reference current and the second reference current.

19. The method of claim 18, wherein the first reference current and the second reference current are adjusted such that the sum of the first reference current and the second reference current is constant over a plurality of gain settings and the common-mode output current of the second differential transistor pair is kept constant.

20. The method of claim 19, further comprising providing the first reference current and the second reference current using a digital-to-analog converter (DAC), wherein adjusting the gain of the variable gain amplifier comprises providing a digital input code to the DAC.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the present disclosure will now be described with reference to the annexed drawings, which are provided purely by way of non-limiting example, and in which:

(2) FIG. 1 is a schematic illustration of a circuit arrangement according to first embodiments;

(3) FIG. 2 is a schematic illustration of the circuit arrangement of FIG. 1 according to embodiments with further details of implementation;

(4) FIG. 3 is a schematic illustration of a circuit arrangement according to embodiments;

(5) FIG. 4 is a schematic illustration of a circuit used by the circuit arrangement according to the foregoing embodiments;

(6) FIG. 5 illustrates a diagram of implementation of the circuit of FIG. 4;

(7) FIGS. 6A and 6B illustrate additional biasing circuits that can be used in a circuit arrangement according to embodiments;

(8) FIG. 7 is a schematic illustration of a circuit arrangement according to embodiments that is associated to the additional biasing circuits of FIGS. 6A and 6B;

(9) FIG. 8 shows a detailed diagram of the additional circuit of FIG. 6A;

(10) FIG. 9 shows a detailed diagram of the additional circuit of FIG. 6B;

(11) FIG. 10 illustrates a detailed diagram of a circuit arrangement according to embodiments that is associated to the additional circuits of FIGS. 8 and 9;

(12) FIG. 11A is a schematic illustration of a compensation circuit that can be associated to the circuit arrangement according to embodiments;

(13) FIG. 11B is a schematic illustration of a detail of the above compensation circuit;

(14) FIG. 12A is a schematic illustration of an ultrasonic obstacle detector comprising the circuit arrangement described herein; and

(15) FIG. 12B illustrates a partial detailed block diagram of the detector of FIG. 12A.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(16) In the ensuing description, numerous specific details are illustrated in order to enable an in-depth understanding of embodiments. The embodiments may be implemented without one or more of the specific details or with other methods, components, materials, etc. In other cases, well-known operations, materials or structures are not illustrated or described in detail so that certain aspects of the embodiments will not be obscured.

(17) Reference to an embodiment or one embodiment in the framework of the present disclosure is intended to indicate that a particular configuration, structure, or characteristic described with reference to the embodiment is comprised in at least one embodiment. Hence, phrases such as in an embodiment or in one embodiment or the like that may be present in various points of the present description do not necessarily all refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

(18) The references used herein are provided merely for convenience and hence do not define the sphere of protection or the scope of the embodiments.

(19) Components, elements, or parts that will be described with reference to one drawing are designated, in the subsequent drawings, by the same references as those used in that drawing; the description of the aforesaid elements already described will not be subsequently repeated in order not to overburden the present detailed description.

(20) Shown in FIG. 1 is a current-controlled gain amplifier 20, which has a structure of a substantially Gilbert-cell type.

(21) The current-controlled gain amplifier 20 substantially has a symmetrical differential structure. It includes an input stage 21 comprising a first differential branch that includes an operational amplifier OP1, the output of which is coupled to the input electrode of a MOSFET M1, in which a current I.sub.M1 flows between the drain electrode and the source electrode. The source electrode of the MOSFET M1 is coupled to the inverting input of the operational amplifier OP1 and, through an input resistance R.sub.I, to an input node NI, there being set, between the input node and ground, a current generator 22 for biasing the input stage 21, which receives a value of input current I.sub.bIN that is controlled via a digital signal D.sub.in, in particular a 10-bit signal, D.sub.in<9:0>, generated by a digital-to-analog converter, not illustrated in FIG. 1, the input current I.sub.bIN having a direction exiting from the node NI towards ground GND. The drain electrode of the MOSFET M1 is coupled to the supply voltage Vss through a diode D1, the negative terminal of which is coupled to the drain of the MOSFET M1 and the positive terminal of which is coupled to the supply voltage Vss. The drain electrode of the MOSFET M1, formed on which is a base voltage V.sub.B1, is also coupled to an output stage 23, comprising two bipolar transistors T1 and T2, specifically to the base electrode of a first bipolar transistor T1, the collector of which is coupled to the supply voltage through an output resistance R.sub.O, whereas coupled to its emitter is a current generator 24 for biasing the output stage 23, which generates an output current I.sub.bOUT, the direction of flow of which is from the emitter to ground. In the diode D1 is a current I.sub.D1 flows from the supply voltage to the drain of the MOSFET M1, while in the output resistance R.sub.O is a collector current I.sub.C1 flows towards ground GND, the emitter current I.sub.E1 being indicated also as flowing towards ground.

(22) Symmetrically, the current-controlled gain amplifier 20 comprises a second differential branch, which includes an amplifier OP2, the output of which is coupled to the input of a MOSFET M2, in which a current I.sub.M2 flows between the drain and the source. The source electrode is coupled to the inverting input of the operational amplifier OP2 and, through an input resistance R.sub.I, having a value equal to that of the other branch and hence designated by the same reference, to the input node NI, which is hence coupled to the sources of the MOSFETs M1 and M2 and to the input-current generator 22. The drain electrode of the MOSFET M2 is coupled to the supply voltage Vcc through a respective diode D2, similar to the diode D1 of the other branch and likewise positioned with its negative terminal, or cathode, towards the drain of the MOSFET M2 and its positive terminal, or anode, towards the supply voltage Vcc.

(23) The drain electrode of the MOSFET M2, on which a base voltage V.sub.B2 is set up, is also coupled to the base electrode of a second bipolar transistor T2, the collector of which is coupled to the supply voltage through a further output resistance R.sub.O, while coupled to its emitter is the output-current generator 24 and the emitter of the first transistor T1. In the diode D2 a current I.sub.D2 flows from the supply voltage to the drain of the MOSFET M2, while in the output resistance R.sub.O a collector current I.sub.C2 flows towards ground, an emitter current I.sub.E2 being instead indicated as flowing in the opposite direction, so that the output current T.sub.bOUT, which flows towards ground GND, is equal to the sum of the currents I.sub.E1 and I.sub.E2. MOSFETs M1 and M2 may be referred to as a differential pair of transistors. MOSFETs M1 and M2 in combination with resistors R.sub.I may be referred to as a degenerated MOSFET differential pair.

(24) An output voltage Vout is measured between the collectors of the bipolar transistors T1 and T2, towards the bases of which base currents I.sub.B1 and I.sub.B2 flow.

(25) An input voltage Vin is applied between the non-inverting terminals of the operational amplifiers OP1 and OP2.

(26) As regards biasing of the circuit 20 we have the following situation. Recalling that I.sub.C=I.sub.EI.sub.B, the biasing conditions are that the transistors T1 and T2 are biased in the active region. To a first approximation, the base currents I.sub.B1 and I.sub.B2 are negligible with respect to the collector currents. By symmetry,
I.sub.E1=I.sub.E2=I.sub.bOUT/2
I.sub.C1I.sub.E1=I.sub.bOUT/2
I.sub.C2I.sub.E2=I.sub.bOUT/2
This but for the contribution of the current injected into the base of each transistor. Regarding transistors M1 and M2, by symmetry,
I.sub.M1=I.sub.M2=I.sub.bIN/2

(27) As in the case of biasing of the bipolar transistors T1 and T2, it is assumed that the base current subtracted from the biasing current of the diodes D1 and D2 is negligible, and hence
I.sub.D1=I.sub.M1I.sub.B1I.sub.bIN/2
I.sub.D2=I.sub.M2I.sub.B2I.sub.bIN/2.

(28) FIG. 2 is a representation of the circuit of the current-controlled gain amplifier 20, corresponding as regards circuit arrangement to that of FIG. 1, where quantities for small-signal analysis are indicated, in which the input circuit 21 and the output circuit 23 are visible in a more distinct way.

(29) Hence, the circuit of the current-controlled gain amplifier 20 comprises the output circuit 23, which basically comprises the pair of bipolar transistors T1, T2 and the output-current generator 23, which supplies the biasing current of the pair, i.e., the output current I.sub.bOUT, the output circuit 23 representing a differential amplification stage with emitter-coupled bipolar transistors. For this structure, in small-signal regime, the relation between the variation V.sub.Bdiff of the input signal, which is the difference between the voltages on the bases of the two transistors, V.sub.Bdiff=V.sub.B1V.sub.B2, and the variation of the output signal, which is the difference between the voltages on the collectors, V.sub.OUT=V.sub.C1V.sub.C2, is the following:
V.sub.OUTdiff=g.sub.mTR.sub.OV.sub.Bdiff
where .sub.OUTdiff and V.sub.Bdiff are the small-signal variations of the respective quantities V.sub.OUTdiff (output) and V.sub.Bdiff (input).

(30) The parameter g.sub.mT=dI.sub.C/dV.sub.BE=I.sub.C/V.sub.T represents the transconductance of each of the two bipolar transistors T1 and T2 in the operating point determined by the biasing collector current I.sub.C and, given what has been said previously, is the same for both and is approximately equal to:

(31) $g_{\mathrm{mT}}\frac{I_{\mathrm{bOUT}}}{2V_T}.$

(32) The input stage 21, comprising the components OP1, OP2, M1, M2, R.sub.I, 22, uses a circuit to provide high impedance and render the biasing current of the input transistor M1, M2 independent of the input signal.

(33) The function performed by the two operational amplifiers OP1 and OP2 is to bring the voltage level present on the non-inverting input directly back onto the respective source electrode of the two MOS transistors M1 and M2. As a result of this function, once again analysing the circuit in the small-signal regime, when a (small-signal) voltage V.sub.IN is imposed on the input of the circuit, this alters the static biasing condition and is transferred to the series of the two resistances R.sub.I, thus bringing about a variation of input current I.sub.IN that flows in each of them, proportional to the input signal applied and obviously of opposite sign (and hence direction), in the two branches of the input stage 21:
I.sub.IN=V.sub.IN/(2R.sub.I)

(34) As regards calculation of the gain in small-signal regime, the diodes D1 and D2 are, for example, obtained via diode-connected transistors (base shorted to the collector).

(35) As is known, the transconductance of the two diodes D1 and D2, g.sub.mD1, g.sub.mD2, is

(36) $g_{\mathrm{mD}1}=\frac{{\mathrm{dI}}_D}{{\mathrm{dV}}_D}=I_{D1}/V_T{g}_{\mathrm{mD}2}=\frac{{\mathrm{dI}}_D}{{\mathrm{dV}}_D}=I_{D2}/V_T.$

(37) In the case of the amplification circuit with current-controlled gain 20 described, the above two diodes D1 and D2 are the same as one another and biased in the same way so that the transconductances are identical to one another and (approximately) equal to

(38) $g_{\mathrm{mD}}=g_{\mathrm{mD}1}=g_{\mathrm{mD}2}=\frac{I_D}{V_T}{I}_{\mathrm{bIN}}/2V_T$
where, in the analysis of biasing, it is assumed, as has been said, that the contribution of the base current absorbed by the respective bipolar transistors and subtracted from the biasing of the two diodes is negligible.

(39) Proceeding with the analysis, as a result of the variation of the input current I.sub.IN in each of the two branches there is brought about a variation of the current I.sub.D1I.sub.IN and I.sub.D2I.sub.IN that flows in the respective diodes D1 and D2 (but for the base currents absorbed by the transistors T1 and T2), which, in turn, as a result of the voltage-current characteristic of the diode, results in a variation of voltage on the bases of the respective transistors T1, T2, namely, V.sub.B1I.sub.IN/g.sub.mD and V.sub.B2I.sub.in/g.sub.mD. Hence, we have
V.sub.Bdiff=2I.sub.in/g.sub.mD
and consequently
V.sub.Bdiff=V.sub.in/(g.sub.mDR.sub.I).
Substituting the above in the equation V.sub.OUTdiff=gm.sub.TR.sub.OV.sub.Bdiff, we obtain

(40) $V_{\mathrm{OUTdiff}}=g_{\mathrm{mT}}{R}_0{V}_{\mathrm{IN}}/\left(g_{mD}{R}_I\right)=\frac{g_{\mathrm{mT}}{R}_O}{g_{mD}{R}_I}{V}_{\mathrm{in}}\frac{I_{\mathrm{bOUT}}{R}_O}{I_{\mathrm{bIN}}{R}_I}{V}_{\mathrm{in}},$

(41) As may be noted from the formula of the voltage gain A.sub.V, the latter can be programmed on a scale of different values keeping fixed and constant the biasing current of the output stage 23 I.sub.bOUT and varying/controlling the biasing current of the input stage I.sub.bIN using a current generator controlled by a digital-to-analog converter (DAC).

(42) $A_V=\frac{V_{\mathrm{OUTdiff}}}{V_{\mathrm{in}}}=\frac{g_{\mathrm{mT}}{R}_O}{g_{mD}{R}_I}-\frac{I_{\mathrm{bOUT}}}{I_{\mathrm{bIN}}}\frac{R_O}{R_I}=\frac{I_{\mathrm{bOUT}}}{I_{\mathrm{LSB}}{D}_{\mathrm{in}<9:0>}}\frac{R_O}{R_I}.$
The current gain is instead

(43) $A_I=\frac{V_{\mathrm{OUTdiff}}}{2I_{\mathrm{IN}}}=\frac{I_{\mathrm{OUTdiff}}}{I_{\mathrm{INdiff}}}=\frac{g_{\mathrm{mT}}}{g_{mD}}-\frac{I_{\mathrm{bOUT}}}{I_{\mathrm{bIN}}}=\frac{I_{\mathrm{bOUT}}}{I_{\mathrm{LSB}}{D}_{\mathrm{in}<9:0>}}.$

(44) As has been said, this analysis has been made on the assumption of negligible base currents. But if also these were taken into account, it can be shown that a more accurate relation between the input-current variation I.sub.IN and the output-current variation I.sub.OUT (and hence the current gain) is

(45) $I_{\mathrm{OUTdiff}}\left(1+\frac{1}{g_{mD}}\right)=\frac{g_{\mathrm{mT}}}{g_{mD}}{I}_{\mathrm{INdiff}},$$\mathrm{where}:g_{\mathrm{mT}}=\frac{I_C}{V_T}=-\frac{I_E}{V_T}\frac{}{1+}=-\frac{I_{\mathrm{bOUT}}}{2V_T}\frac{}{1+}$$g_{mD}=\frac{I_D}{V_T}=\frac{\left(\frac{I_{\mathrm{bIN}}}{2}-I_B\right)}{V_T}=\frac{\left(\frac{I_{\mathrm{bIN}}}{2}-\frac{I_{\mathrm{bOUT}}}{2}\frac{1}{1+}\right)}{V_T},$
where, as is known, is the ratio between the collector current and the base current of the bipolar transistors T1, T2 and their threshold voltage V.sub.T.

(46) The amplification circuit with current-controlled gain 20 described with reference to FIGS. 1 and 2 provides a variable-gain amplifier with constant input and output biasing.

(47) The above circuit in general presents a criticality as regards matching of the currents. The input current I.sub.bIN must range from one hundredth of the value to the value of the output current I.sub.bOUT, so that the ratio between the currents I.sub.bOUT/I.sub.LSB should be precise and kept constant in time, i.e., independent of the any disturbance during production and operation (temperature variation, process spread, etc.). Further criticalities, described in greater detail with reference to the embodiment of FIG. 11, may regard the beta factor.

(48) Hence, with reference to FIG. 3 an embodiment is described for implementing a function of amplifier used for equalizing the output signal as the input signal varies, via gain adjustment.

(49) The embodiment described thus refers to a variable-gain amplifier with constant output biasing that divides the input and output biasing currents as a function of the gain to be obtained.

(50) Constant-current output biasing presents the advantage of maintaining the stage downstream always in the same operating conditions, thus preventing, for example, problems of common-mode variation that might disturb the operating point.

(51) In particular, as illustrated in FIG. 3, a biasing of the input stage is carried out with a denominator current of programmable value I.sub.d. Biasing of the output stage is carried out with a constant current I.sub.bOUT, the value of which is, however, obtained from the sum of two current contributions, one of which is a first reference current, or denominator current, of programmable value I.sub.d, and the other is a second reference current, or numerator current I.sub.n, i.e., of a value complementary with respect to the constant current I.sub.bOUT, namely, such that I.sub.bOUT=I.sub.d+I.sub.n.

(52) FIG. 3 hence shows an embodiment 30 of an amplification circuit with current-controlled gain that corresponds for the most part to the amplification circuit 20. Instead of the generator 22, however, a programmable current generator 32 is provided, which generates the denominator current of programmable value I.sub.d under the control of a signal of a DAC (not illustrated in FIG. 3).

(53) Instead of the current generator 24, a current generator 34 is provided, which generates a current of constant value obtained from the sum of two current contributions, one of which is the denominator current of programmable value I.sub.d and the other is the complementary numerator current I.sub.n, such that I.sub.bOUT=I.sub.d+I.sub.n, which is a constant current.

(54) As has been said, the amplification circuit 30 represented is topologically similar to the amplification circuit 20 and is distinguished by the choice of the biasing currents of the input and output stages. It is hence possible to proceed with biasing and small-signal analyses similar to those developed previously for the amplification circuit 20.

(55) As has been said, the input stage, designated by 31 in FIG. 3, uses a circuit to render the biasing current of the input transistor independent of the input signal.

(56) In small-signal regime, if I.sub.IN is the variation of the current in the individual branch of the input stage 31 that flows in each resistance R.sub.I and is induced by the variation of the input signal V.sub.IN and if I.sub.diffout=(I.sub.C1I.sub.C2) is the variation of the differential output current (I.sub.C1I.sub.C2) induced once again by the input signal V.sub.IN, we can write the relation between these two variations of currents, thus determining the current gain.

(57) The gain of the circuit 30 defined as I.sub.diffout over 2I.sub.IN can be obtained from the following:

(58) $I_{\mathrm{OUTdiff}}=2I_{\mathrm{IN}}.Math.\frac{g_{\mathrm{mT}}}{g_{mD}},$
and hence, to a first approximation, i.e., neglecting the contribution of the base currents,

(59) $I_{\mathrm{OUTdiff}}2I_{\mathrm{IN}}.Math.\frac{I_d+I_n}{I_d}.$

(60) The expression of the current gain is thus

(61) 0$A_I=\frac{I_{\mathrm{OUTdiff}}}{2I_{\mathrm{IN}}}=\frac{I_{\mathrm{OUT}\mathrm{diff}}}{I_{\mathrm{INdiff}}}\frac{I_d+I_n}{I_d}$
which, as expected, is a function of the denominator current I.sub.d and the numerator current I.sub.n. Hence, the output biasing depends upon the sum current I.sub.d+I.sub.n.

(62) The gain is a function of the denominator current I.sub.d and the numerator current I.sub.n. If the sum of the currents, or sum current, I.sub.d+I.sub.n is constant, the output stage 33 is biased always in the same way. This makes it possible to get the stage downstream of the circuit 30 to function at a constant biasing independent of the gain.

(63) It is thus envisaged to use, in association with the amplification circuit 30, a differential DAC, the output currents of which are complementary and the sum of which is constant, i.e., the output currents correspond to the currents I.sub.d and I.sub.n used by the circuit 30.

(64) The denominator current I.sub.d is mirrored by a branch of the differential DAC, and the sum current I.sub.d+I.sub.n is the sum of the two branches. The currents I.sub.d and I.sub.d+I.sub.n can be obtained from components that are the same as one another and have the same temperature dependence.

(65) The gain of the Gilbert cell depends upon the collector currents of the bipolar transistors (the diodes may also be implemented using bipolar transistors). In the configuration of the circuit 30, these currents are not controlled because they are imposed by the emitter and the cathode of the diode. Hence, for applications that require gains that are very precise and high (high current ratio (I.sub.d+I.sub.n)/I.sub.d, low currents I.sub.d) the circuit 30 may present a limitation in precision.

(66) To solve the aforesaid problem, illustrated in FIG. 4 is an embodiment 40, which corresponds to the embodiment 30 but in which a digital-to-analog converter (DAC) 45 is illustrated that supplies the denominator current I.sub.d and the numerator current I.sub.n. DAC 45 may also be referred to as a reference current generator.

(67) The DAC 45 comprises an input for an n-bit digital datum D.sub.in<n . . . o> and supplies at output the complementary current I.sub.n to a first current mirror MR1 and the denominator current of programmable value I.sub.d to a second current mirror MR2. The first current mirror MR1 mirrors the current I.sub.n towards a sum node SN, flowing into which is also the current mirrored by the second current mirror MR2, thus obtaining the current I.sub.d+I.sub.n, and consequently providing the output biasing-current generator 34, whereas a current mirror in parallel MR3 mirrors the current I.sub.d towards a further output, consequently providing the input biasing-current generator 32.

(68) The same circuit that enables selection of the gain provides matching between the ratio of the currents that determine the gain.

(69) The DAC 45 is linear, with linear variation of gain, where there is, for example:
I.sub.n=((D.sub.in<n1:0>)/2.sup.n)I.sub.ref
I.sub.d=((2.sup.nD.sub.in<n1:0>)/2.sup.n)I.sub.ref
where I.sub.ref is an analog reference current used by the DAC 45 for carrying out the conversion (in a way in itself known, for example using a DAC of a current-steering type), not illustrated in the figure. It may be seen from the above relations how I.sub.n and I.sub.d are complementary. In alternative embodiments, the function of DAC 45 may be replaced by other types of circuits configured to provide complimentary currents I.sub.n and I.sub.d. For example, analog circuitry (e.g. current mirrors) may be used to provide continuous gain control.

(70) FIG. 5 shows an embodiment of the DAC 45 of a current-steering type, in which a plurality of current mirrors is formed, where one branch is constituted by the diode-connected MOSFET Mo, with aspect ratio W/L, in which a current I.sub.ref/2 flows, connected in parallel to which are n MOSFETs M1, . . . , Mn with aspect ratio decreasing from W/L; W to W/2.sup.n1L; i.e., each successive transistor determines an output current halved from I.sub.ref/2 to I.sub.ref/2.sup.n. Hence, in particular, the aforesaid DAC 45 is of a binary type in so far as the output currents have values according to powers of 2 distinct according to the bit selected.

(71) Each of the aforesaid currents can be connected, via a respective switch Dn1, . . . , Do, either to the output terminal on which the current I.sub.n is picked up, or else to the output terminal on which the current I.sub.d is picked up.

(72) The digital input D.sub.in corresponding to the desired gain determines the state of each of the switches Do, . . . , Dn1 and hence the level of the two output currents I.sub.n and I.sub.d. It may be noted how, irrespective of the code of the digital input D.sub.in, the sum of the two output currents remains constant and equal to I.sub.ref, the gain being given by the ratio of I.sub.d+I.sub.n over I.sub.d. It follows that any imprecision/imperfection within the DAC 45 with respect to ideality is transferred proportionally to the numerator and to the denominator of the gain, thus achieving a substantial immunity of the latter with respect to the imperfections/imprecisions during operation of the circuit and/or due to the production process.

(73) To obtain a precise gain of the Gilbert cell it is necessary to be able to set a precise collector current I.sub.C. The reason for this is that the transconductance of a bipolar transistor is defined as g.sub.m=I.sub.C/V.sub.T, where V.sub.T is the threshold voltage of the bipolar transistor. Forcing a collector current I.sub.C may not be easy because the collector has a high impedance. Hence, according to a further embodiment, it is envisaged to force an emitter current I.sub.E of given value on each of the transistors T1 and T2 of FIG. 2 or FIG. 3 in order to obtain the required collector current I.sub.C.

(74) With reference to FIG. 6A, which shows a block diagram of a biasing subsystem of the output stage 50C, in order to force the aforesaid emitter current I.sub.E a circuit is used for biasing the transistors T1 and T2 that comprises a reference current I.sub.refC that is to be forced as the same collector current I.sub.C1, I.sub.C2, on the two transistors T1 and T2, supplied by a generator (not illustrated), which is sent to a comparison node NCC, where, in particular, a subtraction is made, to obtain an error err.sub.C (difference) between an effective collector current I.sub.C1, I.sub.C2, and the reference current I.sub.refC, the error err.sub.C being supplied to a block that applies a gain K.sub.C(s), which is a transfer function where s is the variable in the Laplace domain, to amplify the error err.sub.C. The output of the gain block K.sub.C(s) is supplied as control signal to a current generator 501C, which is hence controlled by the amplified error err.sub.c and which is coupled to the emitters of T1 and T2 and simultaneously forces the emitter current I.sub.E1, I.sub.E2, on the two transistors T1 and T2 so as to bring the error to zero.

(75) To obtain a precise gain of the Gilbert cell in the diagram of FIG. 1 or FIG. 3 it is likewise necessary to be able to set a precise diode current I.sub.d. This through the transconductance of the diode, likewise defined as g.sub.m=I.sub.d/V.sub.T, where V.sub.T is the threshold voltage of the diode D1, D2.

(76) Forcing a precise diode current is not easy either, in so far as part of the biasing current ends up in the base of the transistor T1, T2 (especially for a beta factor of the bipolar transistor that is not particularly high) connected to the diode D1, D2 so that the diode comes to be biased at a current different from the design current.

(77) The embodiment described herein envisages, in some embodiments, forcing an appropriate biasing current of the input stage in such a way as to guarantee the diode current I.sub.D1, I.sub.D2 required on each diode D1, D2.

(78) With reference to FIG. 6B, which shows a block diagram of a diode-biasing subsystem 50B, a reference current I.sub.refD that is to be forced in each of the two diodes D1, D2 is supplied to a comparison node NCD to obtain the error err.sub.D (difference) between the effective diode current I.sub.D and the reference current I.sub.refD, the error err.sub.D being supplied to a block that applies a gain K.sub.D(s), which is a transfer function where s is the variable in the Laplace domain, to amplify the above error err.sub.D. The output of the gain block K.sub.D(s), is supplied as control signal to a current generator 501D, which is hence controlled by the error err.sub.D, amplified, that forces the biasing current I.sub.biasIN into each of the two branches of the input stage 21 or 31 in such a way as to bring the error err.sub.D to zero.

(79) Illustrated in the subsequent FIG. 7 is a possible embodiment of the gain-controlled amplifier 50, provided with a fine-biasing system 50C, 50D. Each of the two blocks 50C, 50D represents the ensemble of the respective comparison nodes NCC, NCD and of the gain blocks K.sub.C(s), K.sub.D(s), which supply the amplified errors, err.sub.C*K.sub.C(s) for the transistors and err.sub.D*K.sub.D(s) for the diodes, understood as difference between the desired biasing current or reference current (I.sub.refC=I.sub.d+I.sub.n for the transistors and I.sub.refD=I.sub.d for the diodes) and the effective current which instantaneously flows in the element to be biased (I.sub.C1, I.sub.C2 for the transistors and I.sub.D1 and I.sub.D2 for the diodes) and on which there is applied a transfer function/gain denoted as K.sub.C(s) for the transistors and as K.sub.D(s) in the domain of the Laplace transform. The other elements of the circuits 50C and 50D of FIGS. 6A and 6B are illustrated explicitly, in particular, the reference-current generators 502C and 502D that generate the reference currents I.sub.refC, I.sub.refD respectively, which are sent to the comparison nodes NCC, NCD in blocks 50C, 50D. The collector currents I.sub.C1 and I.sub.C2 are sent at input to the block 50C (coupled to the collector electrodes of the transistors T1 and T2), whereas the diode currents I.sub.D1 and I.sub.D2 are sent at input to the block 50D (which is coupled to their anodes).

(80) The controlled current generator 501C of the biasing circuit of the output stage 50C corresponds to the biasing-current generator 24 or 34 of the output stage 23 or 33, which, in this case, becomes a current generator controlled by the output of the block 50C, i.e., err.sub.C*K.sub.C(s). The controlled current generator 501C of the diode-biasing circuit 50D corresponds to the biasing-current generator 22 or 32 of the input stage 21 or 31, which in this case becomes a current generator controlled by the output of the block 50D, i.e., err.sub.D*K.sub.D(s).

(81) The circuitry of blocks 50C and 50D or 50C and 50D or other circuitry that controls the currents of current sources 501D and 501C may be referred to as a current control circuit. Moreover, the circuitry of blocks 50C and 50C may be said to form an input-stage control loop, and the circuitry of blocks 50D and 50D may be said to form an output stage control loop.

(82) The sum of collector currents I.sub.C1 and I.sub.C2 may be referred to as a common-mode output current of transistors T1 and T2 (which form a differential pair of transistors). Thus, the sum of collector currents I.sub.C1, I.sub.C2, on the two transistors T1 and T2 may be made to be substantially equal to the reference current I.sub.refC within practical implementation limits such as device mismatch and finite amplifier gain using block 50C or 50C. Similarly, the sum of diode currents I.sub.D1 and I.sub.D2 may be referred to as the common-mode output current of diodes D1 and D2 (which form a pair of diodes). Thus, the sum of diode currents I.sub.D1, I.sub.D2, on didoes D1 and D2 may be made to be substantially equal to the reference current I.sub.refD within practical implementation limits such as device mismatch and finite amplifier gain using block 50D or 50D.

(83) FIG. 8 illustrates a possible implementation of the input-stage biasing loop 50C.

(84) The circuit 50C is represented for the transistor T, which may be either T1 or T2. The collector current I.sub.C from the collector is mirrored by a current mirror MR1C, formed by a diode-connected MOSFET M4 and a MOSFET M5, the transistors, which are p-channel transistors, having their sources coupled to the supply voltage V.sub.dd, into a comparison branch at input to a second current mirror MR2C, formed by a diode-connected MOSFET M1 and a MOSFET M2, the transistors, which are n-channel transistors, having their sources coupled to the ground voltage. At output from the second current mirror, the aforesaid current I.sub.C is mirrored towards a node that may be referred to as the comparison node NCC, which receives the reference current I.sub.refC=I.sub.d+I.sub.n from the current generator 502C. Consequently, an output branch from the aforesaid node NCC yields a current that is the difference between the two currents, hence the current error err.sub.C. Coupled to the node NCC is the gate of a MOSFET M3 representing the current-controlled generator 501C, the drain of which is coupled to the emitter of the transistor T. A series RC circuit, Cc+Rc, is set in parallel to the gate, thus bringing about a control voltage drop V.sub.DS2 that controls the MOSFET M3, which represents the current-controlled generator 501C.

(85) As may be shown, the point of equilibrium of this circuit 50C, which represents a control loop, is the one in which the current I.sub.C that flows in the collector of the transistor T and henceas a result of the mirror MR1Cin the comparison branch is equal to the reference current I.sub.refC=I.sub.d+I.sub.n. Assuming that we start from that condition of equilibrium and that for any circumstance the collector current I.sub.C varies with respect to the reference current I.sub.refC by a variation i.sub.C it may be seen how this reflects upon the control voltage V.sub.DS2. In the small-signal regime and assuming that the transistors M1, M2 and M3 are in a condition of saturation, the analysis can be developed as described in what follows.

(86) As a result of the current-mirror arrangement MR1C, i.sub.1=i.sub.C.

(87) The perturbation i.sub.1=i.sub.c is impressed on the drain terminal of the transistor M1, which, as a result of the shorting between drain and source, causes a variation in the gate-to-drain voltage v.sub.GS1 equal to

(88) $i_1.fwdarw.v_{GS1}=\frac{i_1}{g_{m1}}.$

(89) Given the gate connection between the transistors M1 and M2 in the current-mirror arrangement MR2C, we have V.sub.GS2=V.sub.GS1 so that the variation of the gate-to-source voltage V.sub.GS2 of the transistor M2 causes a variation of the drain-to-source voltage v.sub.DS2 given by:

(90) $v_{\mathrm{DS}2}\left(-g_{m2}\left(\mathrm{Rc}+\frac{1}{\mathrm{SCc}}\right)\right)v_{\mathrm{GS}1}.$$V_{\mathrm{GS}3}=V_{\mathrm{DS}2}{v}_{\mathrm{GS}3}{v}_{\mathrm{GS}3}\left(-g_{m2}\left(\mathrm{Rc}+\frac{1}{\mathrm{SCc}}\right)\right)v_{\mathrm{GS}1}$
Given the connection between M2 and M3, we have so that the variation of the drain-to-source voltage of the transistor M2 causes a variation in the gate-to-source voltage

(91) $V_{\mathrm{GS}3}=V_{\mathrm{DS}2}{v}_{\mathrm{GS}3}{v}_{\mathrm{GS}3}\left(-g_{m2}\left(\mathrm{Rc}+\frac{1}{\mathrm{SCc}}\right)\right)v_{\mathrm{GS}1}$$\frac{i_3}{g_{m3}}\left(\left(-g_{m2}\left(\mathrm{Rc}+\frac{1}{\mathrm{SCc}}\right)\right)\right)\frac{i_1}{g_{m1}}.$

(92) It may be noted that, as a result of the connection between the transistors M3 and M2, the transistor M3 functions as a voltage-controlled current generator, in particular controlled by the voltage V.sub.DS2, thus providing the generator 501C of FIGS. 6A and 7.

(93) We then have, for the current of the generator 501C denoted by i.sub.3,

(94) $i_3=\left(g_{m2}\left(Rc+\frac{1}{\mathrm{SCc}}\right)\right)\frac{gm3i_1}{g_{m1}}.$

(95) Assuming the MOSFETs M1, M2, M3 as being all the same, the variation of current for the current of the generator 501C is

(96) $i_3=\left(g_m\left(Rc+\frac{1}{\mathrm{SCc}}\right)\right)i_1.$

(97) It is possible to distinguish a first contribution proportional to the error/disturbance signal and a contribution basically linked to the integral of the error.

(98) There is obtained a first contribution of controlled current i.sub.3, which is proportional to the error/perturbation signal i.sub.1 according to the gain factor, which is basically equal, the MOSFETs being all the same, to g.sub.mr.sub.DS10 and has a sign opposite to that of the perturbation so that the loop 50C will compensate the error and progressively tend to bring it to zero:

(99) $\mathrm{For}\mathrm{low}\mathrm{frequencies}:\left(g_m\left(\mathrm{Rc}+\frac{1}{\mathrm{SCc}}\right)\right).fwdarw.\mathrm{gm}/\mathrm{SCc}\left(\mathrm{integration}\mathrm{term}\right)$$\mathrm{For}\mathrm{high}\mathrm{frequencies}:\left(g_m\left(\mathrm{Rc}+\frac{1}{\mathrm{SCc}}\right)\right).fwdarw.\mathrm{gm}\mathrm{Rc}\left(\mathrm{proportional}\mathrm{term}\right).$

(100) Illustrated in FIG. 9 is a possible implementation of the diode-biasing loop 50D. The circuit 50C is represented for the diode D, which may be either D1 or D2. The diode current I.sub.D from the cathode of the diode D is mirrored by a current mirror MR2D, formed by a diode-connected MOSFET M1D and a MOSFET M2D, which are p-channel MOSFETs with sources connected to the supply voltage. At output from the current mirror MR2D, at the drain of the MOSFET M2D, the aforesaid diode current I.sub.D is mirrored towards a node that may be referred to as the comparison node NCD, which receives the reference current I.sub.refD=I.sub.d from the generator 502D. Consequently, an output branch from the above node NCD yields a current that is the difference between the two currents, and hence the current error err.sub.c. At output from the second current mirror MR2D, the aforesaid diode current I.sub.D is mirrored towards a node that may be referred to as the comparison node NCD, which receives the reference current I.sub.refD=I.sub.d. Consequently, an output branch from the node NCD yields a current that is the difference between the two currents, and hence the current error err.sub.D. Coupled to the node NCD is the gate of a MOSFET M3D, which represents the current-controlled generator 501D, the drain of which is coupled to the cathode of the diode D through a current mirror MR1C, formed by a diode-connected MOSFET M4D and a MOSFET MSD, the transistors, which are n-channel transistors, having their sources coupled to the ground voltage. The source of the MOSFET M3D, which is a p-channel MOSFET, is connected to the supply voltage, while the drain is connected to the drain of the NOSFET M4D. A series RC circuit, Cc+Rc, is set in parallel to the gate of the transistor M3D, between the node NCD and ground, bringing about on itself a control voltage drop that controls the MOSFET M3D that represents the current-controlled generator 501D.

(101) Following the same considerations developed for the circuit 50C, it may be shown that the relation between the control current and the error/disturbance current is also in this case equal to that of the transistor-biasing loop 50C.

(102) Assuming that the MOS transistors M1, M2, M3 are all the same, the current variation i.sub.3 for the current of the current generator 501D is:

(103) $i_3=\left(g_m\left(Rc+\frac{1}{\mathrm{SCc}}\right)\right)i_1$

(104) Hence, illustrated in FIG. 10 is an overall diagram of the circuit 50 of FIG. 7, with the implementations of FIGS. 8 and 9, where the biasing of the diodes D1 and D2 is fixed by the denominator current I.sub.d. As may be seen, for each of the transistors T1 and T2, a respective current mirror MR1C is used on the respective collector to convey the collector currents at input to the mirror MR2C.

(105) A node designated by NA, corresponding to the comparison node NCD, which is subject to high gain, imposes a current equal to the denominator current I.sub.d through the loop 50D. The node NB, corresponding to the comparison node NCC, which subject to high gain, imposes a current equal to the sum current I.sub.d+I.sub.n through the loop 50C. The output biasing depends upon the sum current I.sub.d+I.sub.n. The transconductance g.sub.m of the transistors T1, T2 depends only upon the collector currents, which are fixed and independent of the beta factor of the transistors T1, T2 used.

(106) The amplification circuit with current-controlled gain 30, 40 or 50 may present a further criticality, due to a gain error. The factor of the transistors, which are bipolar transistors, for example BCDs (Bipolar CMOS DMOS), may be very low (for example, between 30 and 50). In this case, the base current of the transistors T1 and T2 subtracts current from the diodes D1 and D2, which hence have a current lower than I.sub.bIN/2, leading to a gain error that depends upon the factor , as shown by the foregoing equations. Given that the factor markedly depends upon temperature, as well as upon the collector current itself, it emerges that the expected gain could undergo substantial variations during the service life of the device.

(107) In this regard, FIG. 11A shows a further circuit 60 for recovery and compensation of the base current of the bipolar transistors T, T1, and T2, which also enables compensation of the difference of the base currents due to an unbalancing of the input signal.

(108) The Gilbert cell with bipolar transistors presents in fact intrinsically a limit due to the base current, I.sub.B in FIG. 1, of the bipolar transistors due to the finite beta factor. Above all, in BCD technology the beta factor may assume values lower than 100. Moreover, the base currents I.sub.B1, I.sub.B2 may differ between the two transistors T1, T2 when a differential signal is applied, giving rise to behaviours that are not easily predictable. For instance, if the beta factor has a value 100 and I.sub.C=100.Math.I.sub.d, the base current is I.sub.B=I.sub.C/100=I.sub.d, thus committing an error of 50% on the gain of the Gilbert cell. To overcome this drawback, a circuit 60 is applied to the amplifier with controlled gain, in particular current-controlled gain, 20, 30, 40, 50, to compensate for the individual base currents of the bipolar transistors T1 and T2.

(109) In FIG. 11A, the transistor B2 represents each individual transistor of the output stage 23, whether T1 or T2, which is consequently traversed by the output current I.sub.OUT, which corresponds to the collector current I.sub.C1 or I.sub.C2 of the bipolar transistor T1 or T2 of which the base current is to be compensated so as to provide a so-called super-beta virtual transistor.

(110) The compensation circuit designated by 60 comprises a reference component that normally is used as amplifier, the transistor B2 that corresponds to T1 or T2, and a supporting component, the transistor B1 forced to work in the same working conditions as the transistor B2, a loop L1 used to force the operating condition of the supporting transistor B1, which comprises the transistor B1, and a current mirror MR1S, comprising MOSFETs M1S (which is diode-connected) and M2S. The source electrode of the transistor M1S is coupled to the emitter of the supporting transistor B1, and the gate of the supporting transistor B1 is coupled to the source of M2S.

(111) The transistor B1 (or T1, T2) receives on its collector a copy of the output current of the transistor B2, I.sub.OUT, via a p-channel current mirror MR2S coupled to the branch in which there flows the current I.sub.OUT that traverses the reference transistor B2 and as output the base current I.sub.B1 which in turn is mirrored on the base of the transistor B2 by a p-channel current mirror MR3S. A mirror M4RS in parallel to the current mirror M3RS supplies the output current of the amplifier.

(112) The base current I.sub.B1 of the transistor B1 is linked to the collector current I.sub.C1 of the transistor B1 via the beta factor of the transistor B1. The collector of the supporting transistor B1 represents a comparison node (with high impedance and hence high gain), between the current I.sub.OUT and its collector current I.sub.C1.

(113) The difference between these currents (I.sub.OUTI.sub.C1) sets up a collector-to-emitter voltage V.sub.CE1 on the collector-to-emitter resistance R.sub.CE1 of the transistor B1 (which has a normally very high value), the above collector-to-emitter voltage V.sub.CE1 being used for controlling the base current I.sub.B1 of the transistor B1 via the MOSFET M2S, thus forming a negative loop with inversion of sign on the collector of the transistor B1. The MOSFET M2S forces a base current such that the collector current I.sub.C1 is equal to the current I.sub.OUT, thanks to the negative loop comprising the base current I.sub.B1, the collector current I.sub.C1, and the collector-to-emitter voltage V.sub.CE1 of the transistor B1. The collector of the transistor B1 thus represents a gain point.

(114) The wide operating dynamics is guaranteed by the fact that the bipolar transistors B1 and B2 work with a collector-to-emitter voltage V.sub.CE equal to the base-to-emitter voltage V.sub.BE. In fact, V.sub.CE2=V.sub.BE1+V.sub.GS2V.sub.GS2=V.sub.BE1 (given that the currents I.sub.C1 and I.sub.C2 are equal). Also V.sub.CE1=V.sub.BE1+V.sub.GS2V.sub.GS1=V.sub.BE1.

(115) In FIG. 11B the supporting transistor B1 is represented by the small-signal model. Denoted by r is the dynamic input resistance traversed by the base current I.sub.B1 coming from the transistor M2S and is, in particular, equal to /g.sub.m. A current-controlled generator g.sub.m.Math.V.sub.BE, l.sub.C1, between the collector and the emitter has, in parallel between the collector and ground, the collector-to-emitter resistance r.sub.CE1. It may be shown that the following relation applies:
I.sub.B1=I.sub.OUT/.sub.1=I.sub.B2. I.sub.B1I.sub.B2 The compensation circuit 60 applied to the transistors T1 and T2 of the circuits 30, 40, 50 affords the following features: I.sub.B1I.sub.B2 wide operating dynamics; and I.sub.B1I.sub.B2 equality between the respective voltages of B1 and B2; this means that the precision of cancelling-out of the base current of the transistor B2 will be very high: there is thus obtained a practically zero net current at input (=0).

(116) Illustrated schematically in FIG. 12A is an ultrasonic obstacle detector 150, comprising a pulse transmitter 151, which drives, via its own pulses, a piezoelectric transducer 152, which is an ultrasound transceiver; i.e., it both transmits ultrasounds and receives them, for example via a piezoelectric membrane, and operates under the control of transmission-control pulses TP sent by a control circuit, to emit ultrasound pulses, i.e., pressure-wave pulses.

(117) Also illustrated in FIG. 12A is an object 160 at a distance L, which reflects the ultrasound waves associated to the ultrasound pulses, which are then detected by the piezoelectric transducer 152 itself, the output of which is sent to a receiver circuit 153. The receiver circuit 153 then sends reception-control pulses RP to the control circuit CM, which measures the difference in time T between the transmission-control pulses TP and the reception-control pulses TP. The difference in time T is also known as time of flight. Knowing the rate of propagation of the ultrasound pulses, it is possible to determine the distance L.

(118) FIG. 12B shows a partial block diagram of the ultrasonic obstacle detector 150, which comprises the transducer 152, which is represented schematically as a parallel RC circuit, which is driven by the pulse transmitter 51, to which it is coupled via a transformer. The transducer 152 is also coupled in reception to the receiver circuit 153, a receiver of the ultrasound sensor, in its turn an analog-to-digital converter (ADC) 130.

(119) Hence, in FIG. 12B, an ultrasound signal received RS, which is an analog differential signal, is transmitted via a signal chain comprising a clamp circuit CP, followed by a low-noise amplifier LNA and then by a variable-gain amplifier VGA, the gain of which is controlled by the control module CM through a digital-to-analog converter DC1 and which supplies a differential voltage Vdiff at input to the ADC 130. A digital output DO of the ADC 130, or a filtered version thereof, the filtered digital output DF, which may in general comprise the reception-control pulses RP, is supplied to the control module CM, which, as has been said, is configured for computing the distance L from the object 160 on the basis of the time of flight T of the ultrasonic pulses between the transmitter 151 and the receiver 153.

(120) Hence, through the stimulation of a piezoelectric transducer it is possible to transmit ultrasound waves that can be detected thereby for obstacle recognition. The increase in the transmission distance and the use of specific modulations enable an increase in the performance of the ADAS (Advanced Driver Assistance System) applications for the automotive market. The evolution of the base systems already present makes it possible to pass from diagnostics to assisted/automatic driving.

(121) Ultrasonic obstacle-detection systems may be used to manage problems of environmental interference and of detection systems of adjacent vehicles. However, wind and rain may attenuate and disturb the transmitted signal. Accordingly, pulses coming from adjacent vehicles may give rise to false diagnostics and detection. It is possible to modulate the transmitted signal (above all for distances greater than one metre) to render the latter recognizable during reception. It is difficult, in particular, to provide a system capable of recognizing simultaneously objects that are far away and nearby. Detecting signals reflected by nearby and distant obstacles requires a wide reception range.

(122) A gain control like that of the VGA of FIG. 12B enables conversion of the signal received with an ADC with a conversion range that is small than what is actually necessary.

(123) Embodiments described hence affords various advantages over the solutions of the prior art. Embodiment circuit-arrangements described makes it possible to obtain a variable-gain stage with high gain precision. Moreover, a compact architecture is achieved using a differential current DAC. Embodiment circuit arrangements described likewise makes it possible to obtain a biasing that is independent of the gain.

(124) Of course, without prejudice to the underlying principles of the invention, the details of construction and the embodiments may vary, even appreciably, with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present invention, as defined by the ensuing claims.