CONFIGURING A CIRCUIT FOR GENERATING SAMPLES FROM A TARGET DISTRIBUTION

Abstract

A method for configuring a circuit for generating samples from a target distribution comprises: receiving a matrix representing parameters associated with the target distribution; tuning a plurality of tunable capacitance circuits in a tunable capacitance network based at least in part on respective elements of the matrix, wherein the tunable capacitance network consists essentially of interconnected wires intersecting at a plurality of nodes with selected pairs of nodes of the plurality of nodes interconnected by a respective tunable capacitance circuit of the plurality of tunable capacitance circuits and one or more nodes of the plurality of nodes connected to a common ground by a respective tunable capacitance circuit of the plurality of tunable capacitance circuits; recording respective voltage samples from the plurality of nodes of the tunable capacitance network; and storing a linear transformation of a vector of the voltage samples based at least in part on the matrix.

Claims

1. A method for configuring a circuit for generating samples from a target distribution, the method comprising: receiving a matrix representing parameters associated with the target distribution; tuning a plurality of tunable capacitance circuits in a tunable capacitance network based at least in part on respective elements of the matrix, wherein the tunable capacitance network consists essentially of interconnected wires intersecting at a plurality of nodes with selected pairs of nodes of the plurality of nodes interconnected by a respective tunable capacitance circuit of the plurality of tunable capacitance circuits and one or more nodes of the plurality of nodes connected to a common ground by a respective tunable capacitance circuit of the plurality of tunable capacitance circuits; recording respective voltage samples from the plurality of nodes of the tunable capacitance network; and storing a linear transformation of a vector of the voltage samples based at least in part on the matrix.

2. The method of claim 1, wherein each tunable capacitance circuit of the plurality of tunable capacitance circuits in the tunable capacitance network comprises a plurality of switchable capacitors connected in parallel and each switchable capacitor of each plurality of switchable capacitors comprises an active switching element connected in series with a corresponding capacitor.

3. The method of claim 2, wherein each active switching element of each switchable capacitor of each plurality of switchable capacitors is a transistor comprising three or more terminals including at least as first terminal connected to a voltage source of one or more voltage sources and a second terminal and a third terminal, wherein the second terminal and the third terminal are configured to connect a corresponding capacitor to the tunable capacitance network in a closed switch state and to disconnect the corresponding capacitor from the tunable capacitance network in an open switch state.

4. The method of claim 3, wherein at least the first terminal of each active switching element of each switchable capacitor of each plurality of switchable capacitors is connected to the voltage source of the one or more voltage sources and the voltage source of the one or more voltage sources is configured to provide a voltage that is lower than a threshold voltage of the transistor.

5. The method of claim 1, wherein recording voltage samples is performed using one or more voltage sampling circuits configured to perform non-destructive voltage measurements.

6. The method of claim 1, wherein the target distribution is a Gaussian distribution.

7. The method of claim 1, wherein the linear transformation is based at least in part on one or more eigenvalues and one or more eigenvectors associated with one or more capacitors in the plurality of tunable capacitance circuits.

8. The method of claim 7, wherein the linear transformation comprises transforming the vector of voltage samples based at least in part on the one or more eigenvalues and the one or more eigenvectors associated with one or more capacitors in the plurality of tunable capacitance circuits.

9. The method of claim 7, wherein the linear transformation comprises iteratively calculating one or more eigenvectors using the vector of voltage samples and one or more eigenvectors associated with one or more capacitors in the plurality of tunable capacitance circuits.

10. An apparatus comprising: one or more voltage sources configured to provide respective voltages relative to a common ground; a tunable capacitance network consisting essentially of interconnected wires intersecting at a plurality of nodes with selected pairs of nodes of the plurality of nodes interconnected by a respective tunable capacitance circuit of a plurality of tunable capacitance circuits and one or more nodes of the plurality of nodes connected to the common ground by a respective tunable capacitance circuit of the plurality of tunable capacitance circuits, wherein: each tunable capacitance circuit of the plurality of tunable capacitance circuits comprises a plurality of switchable capacitors connected in parallel, and each switchable capacitor of each plurality of switchable capacitors comprises an active switching element connected in series with a corresponding capacitor; and at least one voltage sampling circuit connected to a corresponding node of the plurality of nodes of the tunable capacitance network configured to record one or more voltage samples.

11. The apparatus of claim 10, wherein each active switching element of a switchable capacitor of the plurality of switchable capacitors comprises a transistor having three or more terminals including at least a first terminal connected to a first voltage source of the one or more voltage sources and a second terminal and a third terminal, wherein the second terminal and the third terminal are configured to connect a corresponding capacitor to the tunable capacitance network in a closed switch state and to disconnect the corresponding capacitor from the tunable capacitance network in an open switch state.

12. The apparatus of claim 11, wherein each transistor of an active switching element of a switchable capacitor of the plurality of switchable capacitors comprises one or more semiconductors doped with one or more electron donor elements or one or more electron acceptor elements.

13. The apparatus of claim 11, wherein the first voltage source is configured to provide a voltage that is lower than a threshold voltage of the transistor.

14. The apparatus of claim 11, wherein each active switching element in a closed switch state is configured to individually dissipate power by a resistance between the second terminal and the third terminal of the active switching element in the closed switch state that is larger than resistances over any wires of the interconnected wires that connect any tunable capacitance circuit of the plurality of tunable capacitance circuits to any node of the plurality of nodes in the tunable capacitance network.

15. The apparatus of claim 10, wherein a voltage sampling circuit of the at least one voltage sampling circuit comprises a sense amplifier and a gain amplifier.

16. The apparatus of claim 10, wherein a voltage sampling circuit of the at least one voltage sampling circuit is configured to perform non-destructive voltage measurements that do not alter a voltage sample that is being recorded by more than 1% during a particular non-destructive voltage measurement.

17. The apparatus of claim 10, wherein each active switching element of a switchable capacitor of the plurality of switchable capacitors comprises three or more terminals including at least a first terminal connected to one voltage source of the one or more voltage sources and a second terminal and a third terminal, wherein the second terminal and the third terminal are configured to connect a corresponding capacitor to the tunable capacitance network in a closed switch state and to disconnect the corresponding capacitor from the tunable capacitance network in an open switch state.

18. The apparatus of claim 17, wherein all closed active switching elements in switchable capacitors of the plurality of switchable capacitors in a first tunable capacitance circuit of the plurality of tunable capacitance circuits that are in a closed switch state during recording of at least one voltage sample of the one or more voltages samples are configured to: individually dissipate power by a resistance between the second terminal and the third terminal of that closed active switching element larger than resistances over any wires of the interconnected wires that connect any of the tunable capacitance circuits to any node of the plurality of nodes in the tunable capacitance network, and collectively provide an effective capacitance of the first tunable capacitance circuit of the plurality of tunable capacitance circuits that is substantially equal to a sum of capacitances of all capacitors connected to the closed active switching elements.

19. The apparatus of claim 18, wherein the selected pairs consist of all pairs of nodes of the plurality of nodes in the tunable capacitance network.

20. The apparatus of claim 18, wherein each capacitor in each switchable capacitor of the plurality of switchable capacitors in the first tunable capacitance circuit of the plurality of tunable capacitance circuits has a different capacitance from any other capacitor in any switchable capacitor of the plurality of switchable capacitors in the first tunable capacitance circuit of the plurality of tunable capacitance circuits.

21. The apparatus of claim 20, wherein each capacitor of a plurality of capacitors in each switchable capacitor of the plurality of switchable capacitors of the first tunable capacitance circuit of the plurality of tunable capacitance circuits has a capacitance that is twice a capacitance of at least one other capacitor in any switchable capacitor of the plurality of switchable capacitors of the first tunable capacitance circuit of the plurality of tunable capacitance circuits.

22. The apparatus of claim 18, wherein each active switching element comprises one or both of an n-type metal-oxide-semiconductor transistor, or a p-type metal-oxide-semiconductor transistor.

23. The apparatus of claim 22, wherein each active switching element is operated using an applied voltage that is lower than a threshold voltage of the one or both of an n-type metal-oxide-semiconductor transistor or a p-type metal-oxide-semiconductor transistor associated with the active switching element.

24. The apparatus of claim 22, wherein each voltage source connected to a respective first terminal of an active switching element is configured to provide a voltage that is lower than a threshold voltage of the one or both of an n-type metal-oxide-semiconductor transistor or a p-type metal-oxide-semiconductor transistor associated with the active switching element.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawing. It is emphasized that, according to common practice, the various features of the drawing are not to-scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. The plots resulting from numerical simulations, as indicated below, are working examples of experimental results associated with some of the techniques described herein, and other plots are prophetic examples of expected experimental results.

[0034] FIG. 1 is a schematic diagram of an example transistor.

[0035] FIG. 2 is a schematic diagram of an example circuit comprising charge nodes.

[0036] FIGS. 3A-3B are schematic diagrams of example circuits.

[0037] FIG. 4 is a schematic diagram of an example circuit comprising transistors and charge nodes.

[0038] FIGS. 5A-5D are schematic diagrams of example CMOS transistors.

[0039] FIGS. 6A-6B are schematic diagrams of example tunable circuits comprising CMOS transistors.

[0040] FIGS. 7A-7B are schematic diagrams of example circuits.

[0041] FIG. 7C is a plot of numerical simulations associated with example circuits.

[0042] FIG. 8 is a schematic diagram of an example circuit comprising island nodes.

[0043] FIGS. 9A-9B are schematic diagrams of example circuits comprising i-gates.

[0044] FIGS. 10A-10B are plots of numerical simulations associated with example tunable circuits.

[0045] FIG. 11 is a schematic diagram of an example tunable circuit.

[0046] FIG. 12 is a schematic diagram of an example tunable circuit that can sample from a distribution.

[0047] FIG. 13 is a flowchart of an example procedure for sampling from a distribution.

[0048] FIGS. 14A-14B are schematic diagrams of example circuits for measuring voltages.

DETAILED DESCRIPTION

[0049] Metal-oxide semiconductor (MOS)-based transistor circuits or complementary metal-oxide semiconductor (CMOS)-based transistor circuits operating in the subthreshold regime can efficiently sample from a Gaussian distribution. In some implementations, MOS-based or CMOS-based transistor circuits can comprise t-gate circuits that act as switches and allow the tuning of the capacitances of transistor/capacitance based circuits by tuning the gate voltages of the t-gates. The effective Maxwell capacitance matrix associated with closed circuits is related to the covariance matrix of the equilibrium Gaussian distribution from which the free charge nodes may be sampled. As such, the ability to tune the Maxwell capacitance matrix results in the ability to tune the covariance matrix from which the free charge nodes are sampled. In some examples, a free charge node can refer to a node that is subject to a time evolution associated with dynamics of a circuit. In some examples, one or more circuits can be combined to form an apparatus or apparatuses.

[0050] A transistor is a voltage-controlled conductor. Some transistors comprise three terminals, as shown in FIG. 1. A three-terminal transistor 100 comprises a source terminal 102, drain terminal 104, and gate terminal 106. By applying a voltage at the gate terminal 106, a current I.sub.DS flowing from the drain terminal 104 to the source terminal 102 can be controlled, as shown by the arrow. When a fixed voltage V is applied across a resistor having a fixed resistance R, the current I can be determined as I=V/R. In contrast to a resistor, the resistance of a transistor is not fixed and can depend on the voltage applied to the gate.

[0051] Some transistors can be operated or driven with a voltage below a certain threshold such that the transistor's behavior is characterized by thermodynamic processes associated with the transport of discrete charges in the transistor. By way of example, a subthreshold transistor can be operated or driven at voltages between 0 and 175 mV. This operating regime is referred to as the subthreshold or weak inversion limit. Ins some examples, this regime can also be referred to as the sub-threshold limit. Fundamentally, the transport of discrete charges within a system can lead to shot noise. Without intending to be bound by theory, the following is an example of a theoretical model for illustrating features associated with the subthreshold limit. The current I.sub.DS flowing from a drain terminal 104 to a source terminal 102 for the three-terminal transistor 100 shown in FIG. 1 operating in the subthreshold limit can be written as

[00001]$\begin{array}{cc}{I}_{\mathrm{DS}}\left(V_{\mathrm{DS}},V_{\mathrm{GS}}\right)=e\left({}_{+}-{}_{-}\right),& \left(1\right)\end{array}$$\begin{array}{cc}{}_{+}=I_0{e}^{\frac{V_{\mathrm{GS}}}{{\mathrm{nV}}_T}},& \left(2\right)\end{array}$$\begin{array}{cc}{}_{-}=I_0{e}^{\frac{V_{\mathrm{GS}}}{{\mathrm{nV}}_T}}{e}^{-\frac{V_{\mathrm{DS}}}{V_T}},& \left(3\right)\end{array}$

where V.sub.DS is the voltage between the drain terminal 104 and the source terminal 102, V.sub.GS is the voltage between the gate terminal 106 and the source terminal 102, and I.sub.0 is a threshold current. In equations eqs. (2) and (3), n is the slope of I.sub.DS in the subthreshold limit and I.sub.DS is linear when plotted on a log scale as a function of

[00002]$e^{\frac{V_{\mathrm{GS}}}{{\mathrm{nV}}_T}}.Math.{}_{+}$

in eq. (2) describes a forward hopping process for a discrete charge i.e., a discrete charge going from the drain terminal 104 to the source terminal 102. Similarly, .sub. in eq. (3) describes a backwards hopping process i.e., a discrete charge going from the source terminal 102 to the drain terminal 104. In eqs. (2) and (3), V.sub.T corresponds to the thermal voltage and is given by

[00003]$\begin{array}{cc}{V}_T=\frac{k_{B}T}{e},& \left(4\right)\end{array}$

where k.sub.B is Boltzmann's constant, T is the temperature of the device and e is the fundamental electron charge. Shot noise can be inseparable from deterministic currents since deterministic currents can be composed of the difference between forward hopping processes and backwards hopping processes. The deterministic current can be an average measure of the noisy electron hopping. The subthreshold regime can therefore be a clean regime in which to build a thermodynamic computer since the noise is relatively well controlled.

[0052] An integrated circuit containing transistors and capacitors can localize charge to nodes of the circuit, as a transistor can regulate the stochastic transport of charge and no charge can cross a capacitor. These nodes of localized charge can be referred to as charge nodes. In particular, transistors can pin down the relationship between voltage and charge. The formula for a voltage vector representing a voltage at each node of the circuit relative to ground, is given by

[00004]$\begin{array}{cc}V={\mathrm{eC}}^{-1}m-C^{-1}{C}_g{V}_r,& \left(5\right)\end{array}$

where C, C.sub.g are matrices and in, V.sub.r are vectors. The matrix C describes how the capacitances are distributed in the circuit and how the capacitances influence the voltage at each node when charges are present. The vector n corresponds to the number of charges in each free node of the free nodes of the circuit. The matrix C.sub.g represents the gate capacitances in a circuit comprising transistors. In particular, the matrix C.sub.g connects the gate voltages of transistors to the nodes of the circuit, influencing the overall voltage distribution of the circuit. The vector V.sub.r represents the reference (or fixed) voltages applied through the gate terminals of the transistors. For a circuit containing d charge nodes with t transistors, C is a matrix with dimensions dd whereas C.sub.g is a dt matrix since C.sub.g maps how each gate capacitance of a transistor influences each node. The result in eq. (5) comes from the charge and voltage equation related to the Maxwell capacitance matrix with

[00005]$\begin{array}{cc}\left[\begin{array}{c}m\\ m_r\end{array}\right]=\frac{V_{\mathrm{th}}}{e}\left[\begin{array}{cc}C& C_g\\ C_g^T& C_r\end{array}\right]\left[\begin{array}{c}V\\ V_r\end{array}\right].& \left(6\right)\end{array}$

[0053] The Maxwell capacitance matrix describes the relationship between charges and voltages on a set of conductors such that

[00006]$\begin{array}{cc}Q=\mathrm{CV},& \left(7\right)\end{array}$

where C is the capacitance matrix, and V and Q correspond to the voltage vector and charge vector, respectively. An example circuit 200 comprising a plurality of nodes, i.e., a node 201, a node 202, a node 203, and a node 204, is shown in FIG. 2. In some examples, a node can be referred to as a charge node such that the circuit 200 comprises four charge nodes. Each of the node 201, the node 202, the node 203, and the node 204 is connected to a capacitor 206, a capacitor 208, a capacitor 210, and a capacitor 212, respectively. Each of the capacitor 206, the capacitor 208, the capacitor 210, and the capacitor 212 is connected to a ground 214, a ground 216, a ground 218, and a ground 220, respectively. Capacitors interconnect the node 201, the node 202, the node 203, and the node 204. Specifically, a capacitor 222 interconnects the node 201 and the node 202, a capacitor 224 interconnects the node 201 and the node 203, a capacitor 226 interconnects the node 201 and the node 204, a capacitor 228 interconnects the node 202 and the node 203, a capacitor 230 interconnects the node 202 and the node 204, and a capacitor 232 interconnects the node 203 and the node 204. Maxwell's equations can be used to show that the charge Q.sub.201 on the node 201, given the voltages V.sub.201, V.sub.202, V.sub.203 and V.sub.204 on the node 201, the node 202, the node 203, and the node 204, respectively, is

[00007]$\begin{array}{cc}{Q}_{201}=C_{206}{V}_{201}+C_{222}\left(V_{201}-V_{202}\right)+C_{224}\left(V_{201}-V_{203}\right)+C_{226}\left(V_{201}+V_{204}\right)=\left(C_{206}+C_{222}+C_{224}+C_{226}\right)V_{201}-C_{222}{V}_{202}-C_{224}{V}_{203}-C_{226}{V}_{204},& \left(8\right)\end{array}$

so that the first row of the capacitance matrix is given by

[00008]$\begin{array}{cc}\left[C_{206}+C_{222}+C_{224}+C_{226}-C_{222}-C_{224}-C_{226}.\right]& \left(9\right)\end{array}$

Extending the above to all nodes, the capacitance matrix can be written

[00009]$\left(10\right)$$\left[\begin{array}{cccc}\begin{array}{c}{C}_{206}+C_{222}+\\ C_{224}+C_{226}\end{array}& -C_{222}& -C_{224}& -C_{226}\\ -C_{222}& \begin{array}{c}{C}_{222}+C_{208}+\\ C_{228}+C_{230}\end{array}& -C_{228}& -C_{230}\\ -C_{224}& -C_{228}& \begin{array}{c}{C}_{224}+C_{228}+\\ C_{210}+C_{232}\end{array}& -C_{232}\\ -C_{226}& -C_{230}& -C_{232}& \begin{array}{c}{C}_{226}+C_{230}+\\ C_{232}+C_{212}\end{array}\end{array}\right]$

[0054] In general, for a circuit with arbitrary nodes, an off diagonal element C.sub.ij in the capacitance matrix represents the mutual capacitance between node i and node j. The negative sign indicates that an increase in the voltage at node j effectively decreases the effective charge due to this mutual capacitance at node i, thus acting in opposition to the voltage at node i. For the diagonal elements in the capacitance matrix, C.sub.ij represents the total capacitance connected to node i, including any capacitors that are connected to node i and ground.

[0055] For some circuits containing charge nodes, the changes in the number of electron charges at each node can be modeled through a Markov process. An example circuit 300A is depicted in FIG. 3A. The circuit 300A comprises a first transistor 302, a second transistor 304, a node 306, a node 308, a node 310, and a node 312 is shown in FIG. 3A. In some examples, these nodes can be referred to as charge nodes. The circuit 300A is one-dimensional since only the node 312 with voltage V.sub.out is free, as each of the node 306, the node 308, and the node 310 is clamped to the voltages V.sub.in, V.sub.dd and V.sub.ss respectively. In some examples, a clamped node can refer to a node that has a voltage that is fixed by an external source. The number of charges on the node 312 is the degree of freedom of the circuit. Both the first transistor 302 and the second transistor 304 can fire and pull charges on or off the node 312. The probability of finding the node 312 in state in per unit time is given by

[00010]$\begin{array}{cc}\frac{p\left(m\right)}{t}=-\left({}_{+}\left(m\right)+{}_{-}\left(m\right)\right)p\left(m\right)+{}_{+}\left(m-1\right)p\left(m-1\right)+{}_{-}\left(m+1\right)p\left(m+1\right),& \left(11\right)\end{array}$

with an illustration of the Markov process 300B shown in FIG. 3B. Flow away from the charge state in occurs with probability per unit time given by (.sub.+(n)+.sub.(n))p(m). Similarly, flow to state in from state m1 occurs with probability per unit time .sub.+(m1)p(m1) and flow to state in from state m+1 occurs with probability per unit time .sub.(m+1)p(m+1).

[0056] In general, a circuit can have many degrees of freedom that correspond to the number of unclamped nodes in the circuit. A general master equation describing the time evolution of the stochastic system can be written as

[00011]$\begin{array}{cc}\frac{p\left(m,t\right)}{t}=\left(U_{\mathrm{in}}\right)p\left(m,t\right),& \left(12\right)\end{array}$

where the linear operator (U.sub.in) can be written as

[00012]$\begin{array}{cc}\left(U_{\mathrm{in}}\right)=-\underset{}{.Math.}\left({}_{-}^{}\left(m,U_{\mathrm{in}}\right)+{}_{+}^{}\left(m,U_{\mathrm{in}}\right)\right)p\left(m,t\right)+{}_{-}^{}\left(m+v_{},U_{\mathrm{in}}\right)p\left(m+v_{},t\right)+{}_{+}^{}\left(m-v_{},U_{\mathrm{in}}\right)p\left(m-v_{},t\right).& \left(13\right)\end{array}$

[0057] In eq. (13), the sum over is a sum over all transistors in the circuit. The vector v.sub. describes what a transistor (labeled does to the circuit. A transistor may pull away charges from a subset of nodes and add charges to another subset of nodes. The terms involving

[00013]${}_{+}^{}\mathrm{and}{}_{-}^{}$

depend explicitly on the node voltages as can be seen from eqs. (2) and (3). As such the 's can be written as functions of V and m using eq. (5).

[0058] An example circuit 400 comprising a node 401, a node 402, a node 403, and a node 404 is shown in FIG. 4. The circuit 400 comprises a transistor 406, a transistor 408, a transistor 410, a capacitor 412, a capacitor 414, a capacitor 416, a capacitor 418, a capacitor 420, a capacitor 422, and a capacitor 424. Node 401 is connected to ground 426 and node 404 is connected to a ground 428. The input voltage supply 430 connected to ground 432 provides an input voltage U.sub.in=U.sub.s. The node 402 and the node 403 are free, i.e., they are not clamped to ground or the input voltage such that n=(m.sub.402,m.sub.403). For the transistor 406 connected to node 401 and node 402 with =1, the transistor 406 can either cause a charge to be added or removed from node 402, corresponding to v.sub.406=(1,0) or v.sub.406=(1,0) respectively. Both possibilities are accounted for in eq. (13) with the terms

[00014]${}_{-}^{}\left(m+v_{},U_{\mathrm{in}}\right)\mathrm{and}{}_{+}^{}\left(m-v_{},U_{\mathrm{in}}\right).$

Similarly, for the transistor 408 connected to the node 402 and the node 403 with =2, the transistor 408 can cause a charge to be removed from the node 403 and added to the node 402 such that v.sub.408=(1,1)). Alternatively, the transistor 408 can cause a charge to be removed from the node 402 and added to the node 403, such that v.sub.408=(1,1)). The sum over would be a sum over three terms since the circuit 400 comprises the transistor 406, the transistor 408, and the transistor 410.

[0059] In addition to considering the dynamics of the probability distribution for the state in as in eq. (12), the trajectories for the state in can also be considered. The change in the state n from time i to time t+dt can be written as

[00015]$\begin{array}{cc}m\left(t+\mathrm{dt}\right)=m\left(t\right)+\underset{}{.Math.}\underset{=}{.Math.}{v}_{}\left({}_{}^{}\left(m\right)\mathrm{dt}\right),& \left(14\right)\end{array}$

where is a Poisson random variable with rate

[00016]${}_{}^{}\left(m\right)\mathrm{dt}.$

In other words, the charge vector evolves according to infinitesimal Poissonian jumps, and the term

[00017]${}_{}^{}\left(m\right)$

can be viewed as the instantaneous probability of making a transition per unit time. Therefore,

[00018]${}_{}^{}\left(m\right)\mathrm{dt}$

is the probability of a transistor causing a change in the charge state in time dt. Further the term accounts for the transistor firing in either the forward or reverse direction.

[0060] Some circuits can be closed and/or isothermal. A closed circuit refers to a circuit wherein none of the conductors (charge degrees of freedom) have their potentials fixed by voltage sources. An isothermal circuit has a temperature that remains constant. Without intending to be bound by theory, the following is an example of a theoretical model for illustrating features associated with closed and isothermal circuits. A Gibbs state associated with a closed and isothermal circuit can be an equilibrium state of the master equation in eq. (12). The Gibbs state can be written

[00019]$\begin{array}{cc}{P}_{\mathrm{Gibbs}}\left(m,t\right)=\frac{e^{-E\left(m\right)}}{Z}\underset{v}{.Math.}\left[L_v\left(m\right),L_v\left(m^{\left(i\right)}\right)\right],& \left(15\right)\end{array}$

where m.sup.(i) is the initial charge state of the system. [a,b]=1 if a=b and 0 otherwise, and v runs over the set of independent conservation laws. The energy E in eq. (15) corresponds to the electrostatic energy. The conservation laws L.sub.v(m) are written as

[00020]$\begin{array}{cc}{L}_{}\left(m\right)=l_{}^{T}m,& \left(16\right)\end{array}$

where

[00021]$l_v^T=0$

with being the matrix of column vectors =[.sub.1, . . . , .sub.M] with each .sub. for transistor specifying the transition m.fwdarw.m+.sub.. For a closed and isothermal circuit, (.sub.).sub.k=.sub.k,n+.sub.k,m. For P.sub.Gibbs(m,t) to be an equilibrium state e circuit is closed and isothermal imposes conditions on the transition rates

[00022]${}_{}^{}\left(m,t\right).$

Such conditions correspond to the local detailed balance (LDB) conditions which can be expressed for each transistor as

[00023]$\begin{array}{cc}\log \frac{{}_{+}^{}\left(m,t\right)}{{}_{-}^{}\left(m+{}_{},t\right)}=-\left(E\left(m+{}_{}\right)-E\left(m\right)\right),& \left(17\right)\end{array}$

The Gibbs distribution in eq. (15) contains the product .sub.v[L.sub.v(m),L.sub.v(m.sup.(i))]. For all circuits considered in this work, L.sub.v(m.sup.(i))=L.sub.v(m). Consequently, in what follows, this term is omitted.

[0061] A charge vector at each node of a circuit can be related to a voltage vector at each node as

[00024]$\begin{array}{cc}Q=\mathrm{CV}.& \left(18\right)\end{array}$

[0062] For a circuit with N conductors, Q=(q.sub.1, . . . , q.sub.N).sup.T and V=(V.sub.1, . . . , V.sub.N).sup.T. Cis the NN Maxwell capacitance matrix. The electrostatic energy E contained in such circuits is given by

[00025]$\begin{array}{cc}\begin{array}{c}E=\frac{1}{2}{Q}^{T}V\\ =\frac{1}{2}{V}^T\mathrm{CV}\\ =\frac{1}{2}{Q}^T{C}^{-1}Q,\end{array}& \left(19\right)\end{array}$

where the second and third lines of eq. (19) were determined using eq. (18) and the relation C=C.sup.T. Inserting eq. (19) into eq. (15), the Gibbs state can be written

[00026]$\begin{array}{cc}{P}_{\mathrm{Gibbs}}\left(m,t\right)=\frac{e^{-\frac{e^2}{2}{m}^T{C}^{-1}m}}{Z}.& \left(20\right)\end{array}$

From eq. (20), for closed and isothermal circuits, measuring a charge state can produce samples of a Gaussian distribution with covariance matrix given by in the inverse of the capacitance matrix, C.sup.1.

[0063] Some circuits can incorporate n-type metal-oxide-semiconductor (nMOS) or p-type metal-oxide-semiconductor (pMOS) transistors. nMOS transistors comprise semiconductors doped with an electron donor element, such as phosphorus, arsenic or antimony. pMOS transistors comprise semiconductors doped with an electron acceptor element such as boron, aluminum, or gallium.

[0064] FIG. 5A depicts an example nMOS transistor 500 comprising a source terminal 502 associated with a voltage V.sub.S, a drain terminal 504 associated with a voltage V.sub.D, and a gate terminal 506 associated with a voltage V.sub.g. nMOS transistors typically have positive threshold voltages V.sub.T. An nMOS transistor can act as a short, or conduct, when V.sub.gV.sub.S>V.sub.T and act as open circuits when V.sub.gV.sub.S<V.sub.T. nMOS transistors can have V.sub.D>V.sub.S and can source current to the load. The voltage V.sub.S associated with the source terminal 502 can be low (near or at ground) to ensure the above conditions can easily be satisfied.

[0065] FIG. 5B depicts an example pMOS transistor 508 comprising a source terminal 510 associated with a voltage V.sub.S, a drain terminal 512 associated with a voltage V.sub.D, and a gate terminal 514 associated with a voltage V.sub.S. pMOS transistors typically have negative threshold voltages (i.e. V.sub.T<0). A pMOS transistor can act as a short, or conduct, when V.sub.gV.sub.S<|V.sub.T| and can act as an open circuit when V.sub.gV.sub.S>|V.sub.T|. For pMOS transistors, V.sub.S can be large to ensure that V.sub.gV.sub.S conditions can more easily be satisfied. In addition, pMOS transistors can have V.sub.D<V.sub.S such that current is sunk from the load to the source. By tuning the source and gate voltages of nMOS and pMOS transistors, a circuit can thus act as a short or open circuit.

[0066] Some nMOS and pMOS transistors have four terminals. FIG. 5C depicts an nMOS transistor 516 comprising four terminals, i.e., a source terminal 518, a drain terminal 520, a gate terminal 522, and a body terminal 524. Transition rates associated with a four terminal nMOS device can be expressed using

[00027]${}_0=\frac{I_0}{e}\mathrm{and}{U}_k=\frac{V_k}{V_{\mathrm{th}}}.$

For an nMOS device.

[00028]$\begin{array}{cc}{}_{\mathrm{DS}}^{\mathrm{nMOS}}={}_0{e}^{\frac{U_G-U_B}{n}}{e}^{U_B-U_S}& \left(21\right)\end{array}$$\begin{array}{cc}{}_{\mathrm{SD}}^{\mathrm{nMOS}}={}_0{e}^{\frac{U_G-U_B}{n}}{e}^{U_B-U_D}.& \left(22\right)\end{array}$

[0067] FIG. 5D depicts a pMOS transistor 526 comprising four terminals, i.e., source terminal 528, a drain terminal 530, a gate terminal 532, and a body terminal 534. For a pMOS device, a transition rate can be expressed using the relation

[00029]${}_0=\frac{I_0}{e}\mathrm{and}{U}_k=\frac{V_k}{V_{\mathrm{th}}}\mathrm{as}$

[00030]$\begin{array}{cc}{}_{\mathrm{DS}}^{\mathrm{pMOS}}={}_0{e}^{\frac{U_B-U_G}{n}}{e}^{U_D-U_B}& \left(23\right)\end{array}$$\begin{array}{cc}{}_{\mathrm{SD}}^{\mathrm{pMOS}}={}_0{e}^{\frac{U_B-U_G}{n}}{e}^{U_S-U_B}.& \left(24\right)\end{array}$

[0068] Some circuits can effectively act as tunable resistors by combining nMOS and pMOS transistors. FIG. 6A depicts a circuit 600 that can act as a tunable resistor comprising a pMOS transistor 602 and a nMOS transistor 604. In some implementations, the circuit 600 can be referred to as a tunable resistance circuit. Each of the pMOS transistor 602 and the nMOS transistor 604 respectively comprises four terminals. The source terminals of the pMOS transistor 602 and the nMOS transistor 604 are connected at a node 606 and drain terminals of the pMOS transistor 602 and the nMOS transistor 604 are connected at a node 608. The body terminals of the pMOS transistor 602 and the nMOS transistor 604 are connected to a ground 610. For the nMOS transistor 604, V.sub.g can be applied to the gate terminal 614 while for the pMOS transistor 602, V.sub.g can be applied to the gate terminal 612. In this setting, the resulting circuit behaves as a tunable resistor. In more complex circuit diagrams, the circuit 600 can be simplified and represented as circuit 616 comprising a source terminal 618, a drain terminal 620, and a gate terminal 622. The current I.sub.DS from the drain terminal 620 to the source terminal 618 in the circuit 616 is given by

[00031]$\begin{array}{cc}\frac{I_{\mathrm{DS}}}{e}={}_{\mathrm{DS}}-{}_{\mathrm{SD}}=4{}_0{e}^{\frac{U_g}{n}}\cos h{U}_{.Math.}\sin h_{},& \left(25\right)\end{array}$

where U.sub.g=V.sub.g/V.sub.T and

[00032]$\begin{array}{cc}{U}_{.Math.}=\frac{U_D+U_S}{2}& \left(26\right)\end{array}$$\begin{array}{cc}{U}_{}=\frac{U_D-U_S}{2}& \left(27\right)\end{array}$

with U.sub., U.sub.<1. Note that in deriving eq. (25), the symmetry of the circuit was used to write

[00033]${}_{\mathrm{DS}}={}_{\mathrm{DS}}^{\mathrm{pMOS}}+{}_{\mathrm{DS}}^{\mathrm{nMOS}}\mathrm{and}{}_{\mathrm{SD}}={}_{\mathrm{SD}}^{\mathrm{pMOS}}+{}_{\mathrm{SD}}^{\mathrm{nMOS}}$

with such terms given in eqs. (21) to (24). For completeness,

[00034]$\begin{array}{cc}{}_{\mathrm{DS}}+{}_{\mathrm{SD}}=4{}_0{e}^{\frac{U_g}{n}}\cos h{U}_{.Math.}\cos h{U}_{},& \left(28\right)\end{array}$$\mathrm{and}$$\begin{array}{cc}{U}_{}=\frac{e^{-\frac{U_g}{n}}}{4e{}_0}{I}_{\mathrm{DS}},& \left(29\right)\end{array}$

where the term

[00035]$\frac{e^{-\frac{U_g}{n}}}{4e{}_0}~R$

can be interpreted as an effective resistance. From eqs. (25) and (29), when V.sub.g>>1, the effective resistance is near zero and thus the circuit 616 in FIG. 6A behaves as a short circuit. On the other hand, when V.sub.g has a large negative value, the effective resistance is very large and thus the circuit 616 in FIG. 6A behaves as an open circuit. Consequently, a switch can be build out of two transistors. Such considerations for the voltages V.sub.g for closed vs open circuits determines important time scales for the dynamics of the circuit. To obtain a short circuit,

[00036]${}_0{e}^{\frac{U_g}{n}}$

must be greater than the effective transition rates for the other circuit components to which the circuit 616 in FIG. 6A is connected as module.

[0069] At first glance the circuit 616 in FIG. 6A is not closed due to the voltages V.sub.g and V.sub.g. However, the circuit is closed because no current flows through the gate nominally. As such, the closed circuit conditions to sample from a Gaussian distribution are still satisfied.

[0070] In general, a transistor-based circuit that can act as a switch, such as the circuits shown in FIGS. 5A-5D and FIG. 6A, can be referred to as a t-gate switch or a t-gate circuit. Using a combination of the t-gate switches in FIGS. 5A-5D or FIG. 6A, a simple programmable capacitor can be built. An example circuit 650 configured as a programmable capacitor is shown in FIG. 6B. The circuit 650 comprises a node 652 and a node 654 between which a capacitor 656, a capacitor 658, and a capacitor 660 are connected in parallel. Each of the capacitor 656, the capacitor 658, and the capacitor 660 is connected in series with a switch 662, a switch 664, and a switch 666, respectively. Each of the switch 662, the switch 664, and the switch 666 can comprise a respective tunable resistor circuit such as circuit 600 in FIG. 6A. If all the switch 662, the switch 664, and the switch 666 are open, circuit 650 is open. If one of the switch 662, the switch 664, or the switch 666 is closed, the capacitor 656, the capacitor 658, or the capacitor 660 connected to the closed switch is connected. Likewise, if two of the switch 662, the switch 664, or the switch 666 are closed, the circuit 650 can have two of the capacitor 656, the capacitor 658, or the capacitor 660 connected in parallel, which results in a capacitance C.sub.i+C.sub.j where i and j correspond to the indices of the two closed switches. If all three of the switch 662, the switch 664, the switch 666 are closed, the total capacitance is C.sub.1+C.sub.2+C.sub.3. Although FIG. 6B has three capacitors, in general, an arbitrary number of capacitors connected in parallel can be used, with the exact number depending on the particular application being considered, i.e., by the total desired variability in the tunable capacitance device. In such cases with an arbitrary number of capacitors, each capacitor can also be connected in series with a switching element. In more complex circuit diagrams, a tunable capacitor circuit such as the circuit 650 can be depicted as the circuit element 668.

[0071] In some t-gate circuits, each of the switch 662, the switch 664, and the switch 666 can comprise the nMOS transistor 500, the nMOS transistor 516, the pMOS transistor 508, or the pMOS transistor 526 in FIGS. 5A-5D. Alternatively, each of the switch 662, the switch 664, and the switch 666 can comprise the circuit 600 in FIG. 6A which is built out of both a pMOS transistor and an nMOS transistor. A switch including a transistor can comprise three or more terminals including a first terminal that is connected to a voltage source and a second terminal and a third terminal. If the switch is connected to a capacitor, the second terminal and the third terminal can be configured to connect a corresponding capacitor to the tunable capacitance network in a closed switch state and to disconnect the corresponding capacitor from the tunable capacitance network in an open switch state. If the voltages at the source nodes V.sub.S (or drain nodes) are fixed throughout a computation, then an nMOS circuit can be used as a switch if V.sub.S is small, since the V.sub.g>V.sub.S+V.sub.T condition can be easier to satisfy. Alternatively, a pMOS circuit can be used if V.sub.S is large, since the V.sub.gV.sub.s<<|V.sub.T| condition can be easier to satisfy. If V.sub.S is dynamical throughout the computation, then using a circuit such as that depicted in FIG. 6A as a t-gate switch can be advantageous.

[0072] Referring again to the example t-gate circuit shown in FIG. 6B, the circuit properties (whether the circuit is open or short) depends on the voltage V.sub.g. When V.sub.S/V.sub.th is large, the switch made of transistors has an effective resistance which is non-zero. The effects of this non-zero resistance can be demonstrated by circuit 700 shown in FIG. 7A and the circuit 750 shown in FIG. 7B. The circuit 700 comprises a resistor 702 connected in parallel to a capacitor 704 and a capacitor 706. The resistor 702 is associated with a resistance R.sub.1 while the capacitor 704 is associated with a capacitance C.sub.1 and the capacitor 706 is associated with a capacitance C.sub.2. A node 712 of the circuit 700 is associated with equilibrium statistics v.sub.1. The circuit 700 further comprises a switch 708 that can be implemented as a tunable resistor 716 as depicted in circuit 714. The circuit 700 is also connected to a ground 710. The circuit 700 and the circuit 714 are functionally equivalent.

[0073] For large values of V.sub.g, the effective resistance associated with the switch 708 is not zero, resulting in the switch 708 in circuit 700 behaving as a resistor 758 associated with a resistance R in circuit 750 in FIG. 7B. The circuit 750 comprises a resistor 752 associated with a resistance R.sub.1 connected in parallel to a capacitor 754 associated with a capacitance C.sub.1 and a capacitor 756 associated with a capacitance C.sub.2. The circuit 750 is connected to a ground 760. The equilibrium statistics of a node 762 or v.sub.1 in FIG. 7B can be expressed as

[00037]$\begin{array}{cc}P\left(v_1\right)e^{-\left(/2\right)v_1^2/C_1}.& \left(30\right)\end{array}$

If the transistor acted as a true short with zero effective resistance as shown in FIG. 7A, the equilibrium statistics v.sub.1 of the node 712 would be

[00038]$\begin{array}{cc}P\left(v_1\right)e^{-\left(/2\right)v_1^2/\left(C_1+C_2\right)}& \left(31\right)\end{array}$

[0074] The equilibrium distribution in eq. (31) should be recovered from the one in eq. (30) by taking the limit where R.fwdarw.0. However the distribution in eq. (31) is independent of R. FIG. 7C depicts plots of numerical simulations associated with operating circuits. A trace 780 depicts the variance of voltage fluctuations of the node v.sub.1 as a function of V.sub.g/V.sub.th. FIG. 7C also depicts a trace 784 of the work per unit time for a resistor root mean square power as a function of V.sub.g/V.sub.th and a trace 786 of the work per unit time for a switch power draw as a function of V.sub.g/V.sub.th. Dashed line 782 indicates an approximate value for V.sub.g/V.sub.th when the gate power is within an order of magnitude of the noise fluctuations, or the point at which a t-gate starts to behave as a short. As shown by the plots in FIG. 7C, when V.sub.g/V.sub.th is large, the t-gate starts to use power and does work on the system. As such, the system no longer goes to equilibrium and thus the t-gate behaves as a true short circuit. The short works as expected since the voltage fluctuations get cut in half. Consequently, in what follows, t-gates can be assumed to behave as true short and open circuits when considering their effect on the effective capacitance of a given circuit.

[0075] In some implementations of t-gate circuits, a circuit can comprise free nodes, regulated nodes, and island nodes. A circuit comprising one or more island nodes can have an localized charge around the one or more island nodes. In such circuits, the voltage covariance of relevant degrees of free is identical to the shorted case if the t-gate circuits do not behave as a true short. Without intending to be bound by theory, the following is an example of a theoretical model for illustrating features.

[0076] Charge and voltage vectors for free, regulated, and island nodes can be defined as (q.sub.f,V.sub.f), (q.sub.r,V.sub.r) and (q.sub.i,V.sub.i). The charge and voltage vectors are related by the Maxwell capacitance matrix as

[00039]$\begin{array}{cc}\left[\begin{array}{c}{q}_f\\ q_r\\ q_i\end{array}\right]=\left[\begin{array}{ccc}{C}_f& C_{\mathrm{fr}}& C_{\mathrm{fi}}\\ C_{\mathrm{fr}}^T& C_r& C_{\mathrm{ri}}\\ C_{\mathrm{fi}}^T& C_{\mathrm{ri}}^T& C_i\end{array}\right]\left[\begin{array}{c}{V}_f\\ V_r\\ V_i\end{array}\right].& \left(32\right)\end{array}$

Performing the matrix multiplications in eq. (32), results in

[00040]$\begin{array}{cc}{V}_i=C_i^{-1}{q}_i-C_i^{-1}{C}_{\mathrm{fi}}^T{V}_f-C_i^{-1}{C}_{\mathrm{ri}}^T{V}_r,& \left(33\right)\end{array}$$\begin{array}{cc}{q}_r=C_{\mathrm{fr}}^T{V}_f+C_r{V}_r+C_{\mathrm{ri}}{V}_i,& \left(34\right)\end{array}$$\begin{array}{cc}{C}_f{V}_f=q_f-C_{\mathrm{fr}}{V}_r-C_{\mathrm{fi}}{V}_i.& \left(35\right)\end{array}$

Inserting eq. (33) into eq. (35),

[00041]$\begin{array}{cc}{q}_f-C_{\mathrm{fi}}{C}_i^{-1}{q}_i=\left(C_f-C_{\mathrm{fi}}{C}_i^{-1}{C}_{\mathrm{fi}}^T\right)V_f+\left(C_{\mathrm{fr}}-C_{\mathrm{fi}}{C}_i^{-1}{C}_{\mathrm{ri}}^T\right)V_r.& \left(36\right)\end{array}$

From eq. (36) the adjusted free capacitance matrix can be defined as

[00042]$\begin{array}{cc}{C}_{\mathrm{eff}}=C_f-C_{\mathrm{fi}}{C}_i^{-1}{C}_{\mathrm{fi}}^T.& \left(37\right)\end{array}$

The voltage V.sub.f can then be written as

[00043]$\begin{array}{cc}{V}_f=C_{\mathrm{eff}}^{-1}{q}_f-C_{\mathrm{eff}}^{-1},C_{\mathrm{fi}}{C}_{\mathrm{eff}}^{-1}\left(C_{\mathrm{fr}}-C_{\mathrm{fi}}{C}_i^{-1}{C}_{\mathrm{ri}}^T\right)V_r.& \left(38\right)\end{array}$

Substituting eq. (38) into eq. (34),

[00044]$\begin{array}{cc}{q}_r=C_{\mathrm{fr}}^T{C}_{\mathrm{eff}}^{-1}{q}_f-C_{\mathrm{fr}}^T{C}_{\mathrm{eff}}^{-1}{C}_{\mathrm{fi}}{C}_i^{-1}{q}_i+\left(C_r-C_{\mathrm{fr}}^T{C}_{\mathrm{eff}}^{-1}{C}_{\mathrm{fr}}+C_{\mathrm{fr}}^T{C}_{\mathrm{eff}}^{-1}{C}_{\mathrm{fi}}{C}_i^{-1}{C}_{\mathrm{ri}}^T\right)V_r.& \left(39\right)\end{array}$

In a similar fashion, inserting eq. (38) into eq. (33) results in

[00045]$\begin{array}{cc}{V}_i=\left(C_i^{-1}+C_i^{-1}{C}_{\mathrm{fi}}^T{C}_{\mathrm{eff}}^{-1}{C}_{\mathrm{fi}}{C}_i^{-1}\right)q_i-C_i^{-1}{C}_{\mathrm{fi}}^T{C}_{\mathrm{eff}}^{-1}{q}_f+\left(C_i^{-1}{C}_{\mathrm{fi}}^T{C}_{\mathrm{eff}}^{-1}\left(C_{\mathrm{fr}}-C_{\mathrm{fi}}{C}_i^{-1}{C}_{\mathrm{ri}}^T\right)-C_i^{-1}{C}_{\mathrm{ri}}^T\right)V_r.& \left(40\right)\end{array}$

Using the above results, the electrostatic energy of the system can be written. Recall that

[00046]$\begin{array}{cc}2E=q_i^T{V}_i+q_r^T{V}_r+q_f^T{V}_f.& \left(41\right)\end{array}$

The eq. (41) can be written in charge space. Using eqs. (38) and (40), eq. (41) becomes

[00047]$\begin{array}{cc}\begin{array}{c}2E=q_f^T{C}_{\mathrm{eff}}^{-1}{q}_f+q_f^T{C}_{\mathrm{eff}}^{-1}{C}_{\mathrm{fi}}{C}_i^{-1}\left(C_{\mathrm{ri}}^T{V}_r-2q_i\right)+V_r^T\left(C_r-C_{\mathrm{fr}}^T{C}_{\mathrm{eff}}^{-1}{C}_{\mathrm{fr}}+C_{\mathrm{ri}}{C}_i^{-1}{C}_{\mathrm{fi}}^T{C}_{\mathrm{eff}}^{-1}{C}_{\mathrm{fr}}\right)V_r\\ +q_i^T\left(C_i^{-1}+C_i^{-1}{C}_{\mathrm{fi}}^T{C}_{\mathrm{eff}}^{-1}{C}_{\mathrm{fi}}{C}_i^{-1}\right)q_i-q_i^T\left(C_i^{-1}{C}_{\mathrm{ri}}^T+C_i^{-1}{C}_{\mathrm{fi}}^T{C}_{\mathrm{eff}}^{-1}{C}_{\mathrm{fi}}{C}_i^{-1}{C}_{\mathrm{ri}}^T\right)V_r.\end{array}& \left(42\right)\end{array}$

From the second term in eq. (42) the island charge, as well as the mutual capacitance matrix between regulated and island charge nodes, shifts the minima of the charge space energy landscape. The covariance of the charge distribution is given by C. The last three terms in eq. (42) do not depend on the state of the system q.sub.f and can thus be treated as constant.

[0077] Next the electrostatic energy can be written in voltage space. In doing so, the charge can first be written q.sub.f as

[00048]$\begin{array}{cc}{q}_f=C_{\mathrm{eff}}{V}_f+\left(C_{\mathrm{fr}}-C_{\mathrm{fi}}{C}_i^{-1}{C}_{\mathrm{ri}}^T\right)V_r+C_{\mathrm{fr}}{C}_i^{-1}{q}_i.& \left(43\right)\end{array}$

Using eqs. (33), (34) and (43) the electrostatic energy can be written as

[00049]$\begin{array}{cc}\begin{array}{c}2E=V_f^T{C}_{\mathrm{eff}}{V}_f+V_f^T\left(2C_{\mathrm{fr}}-C_{\mathrm{fi}}{C}_i^{-1}{C}_{\mathrm{ri}}^T\right)V_r+q_i^T{C}_i^{-1}{q}_i+V_r^T{C}_r{V}_r\\ -q_i^T{C}_i^{-1}{C}_{\mathrm{ri}}^T{V}_r+V_i^T{C}_{\mathrm{ri}}^T{V}_r.\end{array}& \left(44\right)\end{array}$

From eq. (44) that the energy as a function of the regulated voltage V.sub.r does not depend on the island charge q.sub.i (the term

[00050]$q_i^T=C_i^{-1}{q}_i$

is a constant). Due to the term

[00051]$V_f^T=C_{\mathrm{eff}}{V}_f$

in eq. (44), in voltage space, the covariance matrix of the energy function when used in the Boltzmann distribution is given by

[00052]$C_{\mathrm{eff}}^{-1}$

instead of C.sub.eff when expressing E in charge space (see the term

[00053]$q_f^T=C_{\mathrm{eff}}^{-1}{q}_f$

in eq. (42)).

[0078] When adding t-gate shorting devices to a circuit, such devices can connect the charge islands to the rest of the circuit such that they become normal free nodes. The collective system has capacitance matrix given by

[00054]$\begin{array}{cc}{C}_s=\left[\begin{array}{cc}{C}_f& C_{\mathrm{fi}}\\ C_{\mathrm{fi}}^T& C_i\end{array}\right].& \left(45\right)\end{array}$

The charge covariance matrix of the original free nodes in this case is then C.sub.f, which is different than the charge covariance matrix in the open case. Taking the inverse of the shorted capacitance matrix C.sub.s,

[00055]$C_s^{-1}=\left[\begin{array}{cc}{C}_{\mathrm{eff}}^{-1}& -C_{\mathrm{eff}}^{-1}{C}_{\mathrm{fi}}{C}_i^{-1}\\ -C_i^{-1}{C}_{\mathrm{fi}}^T{C}^{-1}{C}_i^{-1}& C_i^{-1}{C}_{\mathrm{fi}}^T{C}^{-1}{C}_{\mathrm{fi}}{C}_i^{-1}\end{array}\right].$

As can be seen from eq. (46), the voltage covariance of the relevant degrees of freedom is identical to the shorted case. As such, a programmable sampling device cannot be built in voltage space using only conservative components.

[0079] Given a circuit containing N capacitors in parallel, each capacitor connected to a switch (for instance, the circuit in FIG. 6B has N=3), the values of the capacitances {C.sub.1, C.sub.2, . . . , C.sub.N} can be chosen to obtain the largest dynamic range of values for C=.sub.j.sub.jC.sub.j where .sub.j is 1 if the i'th switch is a short and zero otherwise. To obtain the maximal dynamic range of values for C, {C.sub.1, C.sub.2, . . . , C.sub.N} can be set to equal {1, 2, 4, . . . , 2.sup.N-1}. This relation results in the largest dynamic range of C because of: (1) Uniqueness: Each subset of {1, 2, 4, . . . , 2.sup.N-1} corresponds uniquely to a binary number of N bits, ensuring all sums are distinct. (2) Maximal span: The sum ranges from 0 to 2.sup.N1 making the span as large as possible for any set of N numbers.

[0080] Since the circuit in FIG. 6B is effectively closed, measuring the charge state m of closed circuits built from the tunable capacitor circuit would generate samples from the Gaussian distribution in eq. (20) with covariance matrix C.sup.1(t), which can be made time dependent by tuning the voltages to effectively change the capacitance of the circuit. As previously demonstrated, the charge space electrostatic energy of the system composed of regulated nodes, free nodes, and island nodes can be written

[00056]$\begin{array}{cc}2E=q_f^T{C}_{\mathrm{eff}}^{-1}{q}_f+q_f^T{C}_{\mathrm{eff}}^{-1}{C}_{\mathrm{fi}}{C}_i^{-1}\left(C_{\mathrm{ri}}^T{V}_r-2q_i\right)+V_r^T\left(C_r-C_{\mathrm{fr}}^T{C}_{\mathrm{eff}}^{-1}{C}_{\mathrm{fr}}+C_{\mathrm{ri}}{C}_i^{-1}{C}_{\mathrm{fi}}^T{C}_{\mathrm{eff}}^{-1}{C}_{\mathrm{fr}}\right)V_r+q_i^T\left(C_i^{-1}+C_i^{-1}{C}_{\mathrm{fi}}^T{C}_{\mathrm{eff}}^{-1}{C}_{\mathrm{li}}{C}_i^{-1}\right)q_i-q_i^T\left(C_i^{-1}{C}_{\mathrm{ri}}^T+C_i^{-1}{C}_{\mathrm{fi}}^T{C}_{\mathrm{eff}}^{-1}{C}_{\mathrm{li}}{C}_i^{-1}{C}_{\mathrm{ri}}^T\right)V_r,& \left(47\right)\end{array}$

where q.sub.f and q.sub.i are the free and island charge vectors, C.sub.r and C.sub.i are the capacitances between regulated nodes and island nodes respectively. In eq. (47), V.sub.r is the voltage vector at regulated nodes, C.sub.fr is the capacitance matrix between free and regulated nodes, C.sub.fi is the capacitance matrix between free and island nodes, C.sub.ri is the capacitance matrix between regulated and island nodes, and C.sub.eff is the effective capacitance matrix given by

[00057]$\begin{array}{cc}{C}_{\mathrm{eff}}=C_f-C_{\mathrm{fi}}{C}_i^{-1}& \left(48\right)\end{array}$

[0081] From the term

[00058]$q_f^T{C}_{\mathrm{eff}}^{-1}{C}_{\mathrm{fi}}{C}_i^{-1}\left(C_{\mathrm{ri}}^T{V}_r-2q_i\right)$

in eq. (47), the island charge can shift a minima associated with the charge space energy landscape. All other terms in eq. (47) do not depend on the state of the system q.sub.f and thus act as a constant. The electrostatic energy can be written in voltage space as

[00059]$\begin{array}{cc}2E=V_f^T{C}_{\mathrm{eff}}{V}_f+V_f^T\left(2C_{\mathrm{fr}}-C_{\mathrm{li}}{C}_i^{-1}{C}_{\mathrm{ri}}^T\right)V_r+q_i^T{C}_i^{-1}{q}_i+V_r^T{C}_r{V}_r-q_i^T{C}_i^{-1}{C}_{\mathrm{ri}}^T{V}_r+V_i^T{C}_{\mathrm{ri}}^T{V}_r.& \left(49\right)\end{array}$

[0082] For a tunable capacitance circuit such as the one depicted in FIG. 5B, eq. (20) shows that the potential energy term that appears in the Boltzmann distribution at equilibrium is given by

[00060]$=e^2\frac{1}{2}{m}^T{C}_{\mathrm{eff}}^{-1}m=\frac{1}{2}{q}_f^T{C}_{\mathrm{eff}}^{-1}{q}_f=\frac{1}{2}{V}_f^T{C}_{\mathrm{eff}}{V}_f$

with C.sub.eff given in eq. (48). By tuning the resistance by adjusting the voltage V.sub.g, charge can flow off the islands, allowing the tuning of the effective capacitance matrix C.sub.eff as expected.

[0083] Some tunable capacitance circuits can comprise island charges and transistors that are associated with intrinsic capacitances. FIG. 8 depicts an example circuit 800 comprising a first node 802 and a second node 804 between which a capacitor 806A, a capacitor 806B, and a capacitor 806C are connected in parallel. Each of the capacitor 806A, the capacitor 806B, and the capacitor 806C is associated with respective capacitance C.sub.1, C.sub.2, C.sub.3. In some examples, the circuit 800 can be referred to as a tunable capacitance circuit. Each of the capacitor 806A, the capacitor 806B, and the capacitor 806C is connected in series to a transistor circuit 808A, a transistor circuit 808B, a transistor circuit 808C, respectively. Each of the transistor circuit 808A, the transistor circuit 808B, the transistor circuit 808C comprises an nMOS and a pMOS transistor. The transistor circuit 808A, the transistor circuit 808B, and the transistor circuit 808C each have a node 810A, a node 810B, and a node 810C, respectively, associated with a negative voltage V.sub.g and a node 812A, a node 812B, and a node 812C, respectively associated with a positive voltage V.sub.g. Each of the transistor circuit 808A, the transistor circuit 808B, and the transistor circuit 808C also has an island node 814A, an island node 814B, and an island node 814C, respectively. Each of the island node 814A, the island node 814B, and the island node 814C is associated with a respective island charge q.sub.i.sub.1, q.sub.i.sub.2 and q.sub.i.sub.3. Capacitors 816 are distributed throughout circuit 800. Since the circuit 800 is effectively closed and eq. (20) is a Gaussian distribution, the circuit 800 in FIG. 8 can allow the sampling of charge vector m of the free nodes from a Gaussian distribution with covariance matrix C.sub.eff given in eq. (48). Additionally, as mentioned above, the term

[00061]$q_f^T=C_{\mathrm{eff}}^{-1}{C}_{\mathrm{fi}}{C}_i^{-1}\left(C_{\mathrm{ri}}^T{V}_r-2q_i\right)$

in eq. (47) creates shifts in the minima of the energy landscape due to island charges.

[0084] A Maxwell capacitance matrix is: (1) Symmetric (2) Positive definite (3) Diagonally dominant: The self-capacitance terms can shift the diagonal elements by an arbitrary positive amount. The diagonal terms in the k'th row is given by

[00062]${.Math.}_{j=1}^n{C}_{\mathrm{kj}}$

(see eq. (50)) with C.sub.kj being the mutual capacitances between nodes k and j (when kj) and C.sub.kk the self-capacitance. (4) Has off-diagonal terms that are either zero or negative.

[0085] The positive semi-definite and symmetric properties are also features of any covariance matrix used to sample from a Gaussian distribution. Regarding diagonal dominance, as previously described, the Maxwell Capacitance matrix for a circuit with n nodes can be written as

[00063]$\begin{array}{cc}\left[\begin{array}{cccc}{.Math.}_{j=1}^n{C}_{1j}& -C_{12}& .Math.& -C_{1n}\\ -C_{21}& {.Math.}_{j=1}^n{C}_{2j}& .Math.& -C_{2n}\\ .Math.& .Math.& .Math.& .Math.\\ -C_{n1}& -C_{n2}& .Math.& {.Math.}_{j=1}^n{C}_{\mathrm{nj}}\end{array}\right].& \left(50\right)\end{array}$

[0086] In the diagonal terms (say for the j'th row of the capacitance matrix), C.sub.jj is the self-capacitance term which is the capacitance between the j'th free node and a distant ground. The self-capacitance term measures how much charge the node can store at a given voltage relative to this ground. The self-capacitance C.sub.jj is often greater than or equal to the sum of the magnitudes of the off-diagonal elements in that row, which reflects the fact that the nodes self-capacitance is often greater than the mutual capacitances with other nodes. Importantly, eq. (50) shows that the diagonal terms are shifted by a positive amount given by the self-capacitance.

[0087] For a system with state v.sub.f, a general Gaussian distribution describing the voltage fluctuations has a probability density function given by

[00064]$\begin{array}{cc}p\left(v_f\right)=\frac{1}{{\left(2\right)}^{n/2}{.Math..Math..Math.}^{1/2}}\exp \left(-\frac{1}{2}{\left(v_f-\right)}^T{.Math.}^{-1}\left(v_f-\right)\right).& \left(51\right)\end{array}$

Expanding the exponent in eq. (51) and comparing it with the electrostatic energy in eq. (47), the covariance matrix and mean vector in voltage space are related to the capacitance and island charges by

[00065]$\begin{array}{cc}{.Math.}^{-1}~C_{\mathrm{eff}}& \left(52\right)\end{array}$$\begin{array}{cc}{.Math.}^{-1}~\left(C_{\mathrm{fi}}{C}_i^{-1}{C}_{\mathrm{ri}}^T-2C_{\mathrm{fr}}\right)V_r,& \left(53\right)\end{array}$
so that

[00066]$\begin{array}{cc}.Math.~C_{\mathrm{eff}}^{-1}& \left(54\right)\end{array}$$\begin{array}{cc}~C_{\mathrm{eff}}^{-1}\left(C_{\mathrm{fi}}{C}_i^{-1}{C}_{\mathrm{ri}}^T-2C_{\mathrm{fr}}\right)V_r,& \left(55\right)\end{array}$

where C.sub.eff is given by eq. (48). Although circuits with t-gate switches allow the tuning of C.sub.eff, since C.sub.eff can take on only discrete values, C.sub.eff may not match exactly the desired .sup.1. As discussed later, various trivial linear algebra transformations can be performed whenever there are discrepancies.

[0088] As previously discussed, a t-gate can comprise either a nMOS transistor (when V.sub.gV.sub.S>V.sub.r) or pMOS transistor (when V.sub.gV.sub.S<|V.sub.T|) or a combination thereof. Some t-gate circuits can be associated with a thermal equilibrium time. FIGS. 9A and 9B depict example t-gate circuits. FIG. 9A depicts an example t-gate circuit 900 comprising a capacitor 902, a node 904, a t-gate 908, and a node 906. The node 904 is connected to ground 910 while the node 906 is free. FIG. 9B depicts an example t-gate circuit 950 comprising a first capacitor 952, a second capacitor 954, a node 956, a node 960, a node 966, a t-gate 958 and a t-gate 962. The node 956 is connected to a ground 968 while the node 960 and the node 966 are free. In FIG. 9A and FIG. 9B, the t-gate can be a nMOS transistor, such as the ones depicted in FIG. 5A and FIG. 5C, a pMOS transistor such as the ones depicted in FIG. 5B and FIG. 5D, or a combination thereof, such as the circuits depicted in FIG. 6A.

[0089] FIG. 10A depicts a plot of numerical simulations of thermal equilibrium times associated with the t-gate circuit 900 in FIG. 9A. The curve 1000 corresponds to a circuit comprising a t-gates such as the circuit depicted in FIG. 6A while the curve 1002 corresponds to a circuit comprising a the t-gates comprising an nMOS switch or a pMOS switch such as those depicted in FIGS. 5A-5D. FIG. 10B depicts a plot of numerical simulations of thermal equilibrium times associated with the t-gate circuit 950 in FIG. 9B. The curve 1006 corresponds to a circuit comprising a t-gates such as the circuit depicted in FIG. 6A while the curve 1008 corresponds to a circuit comprising a the t-gates comprising an nMOS switch or a pMOS switch such as those depicted in FIGS. 5A-5D. As shown in FIGS. 10A-10B, the thermal equilibrium time of the circuit depicted in FIG. 6A is lower than that of the nMOS and pMOS switches. However the difference in thermal equilibrium times is fairly minor. In addition, pMOS and nMOS devices can have nearly identical thermal equilibrium times. For these plots, the gate voltage for the pMOS device is V.sub.g and the gate voltage for the nMOS device is +V.sub.g.

[0090] To obtain the plots of thermal equilibrium times of the devices considered in FIGS. 10A-10B, the smallest non-zero eigenvalues for the steady state equation

[00067]$\begin{array}{cc}\left(U_{\mathrm{in}}\right)p\left(m,t\right)=0,& \left(56\right)\end{array}$

are numerically obtained. In the steady state equation, the linear operator (U.sub.in) is given in eq. (13). If .sub.1 is the smallest non-zero eigenvalue of , the thermal equilibrium time of the free nodes .sub.thermal is given by .sub.thermal=1/.sub.1.

[0091] A capacitance matrix associated with a circuit can be tuned by controlling the flow of charges on or off of a charge island node using t-gate switches. Such manipulations can be performed to tune the effective capacitance matrix in eq. (48) such that the matrix more closely approximates or matches some target covariance matrix used in a Gaussian distribution of interest. More details on trivial linear algebra transformations that can be performed to map C.sub.eff to E are discussed later.

[0092] FIG. 11 depicts an example circuit 1100 comprising a first node 1102 and a ground node 1104. The circuit 1100 comprises a capacitor 1106, a capacitor 1108, and a capacitor 1110 that are connected in parallel. Each of the capacitor 1106, the capacitor 1108, and the capacitor 1110 is connected in series with a t-gate switch 1112, a t-gate switch 1114, and a t-gate switch 1116, respectively. The presence of the t-gate switch 1112, the t-gate switch 1114, the t-gate switch 1116 results in three island nodes. If t-gate switches are tuned such that the t-gate switch 1112 and the t-gate switch 1116 are open, the circuit 1100 behaves as circuit 1150 with open switch 1162, closed switch 1164, and open switch 1166. The circuit 1150 comprises a first node 1152 and a ground node 1154. The circuit 1150 comprises a capacitor 1156, a capacitor 1158, and a capacitor 1160 connected in parallel. Each of the capacitor 1156, the capacitor 1158, and the capacitor 1160 is associated with a respective capacitance C.sub.1,C.sub.2,C.sub.3. The effective capacitance for circuit 1150 is C.sub.2.

[0093] In a more general case of tuning the capacitance matrix associated with circuit 1100, the capacitor 1106, the capacitor 1108, and the capacitor 1110 can each be associated with a capacitance C.sub.1, C.sub.2, and C.sub.3, respectively. The effective capacitance of the circuit 1100 can be written

[00068]$\begin{array}{cc}{C}_{\mathrm{eff}}=\underset{j=1}{\overset{3}{.Math.}}\left(j\right)C_j,& \left(57\right)\end{array}$$\mathrm{where}$$\begin{array}{cc}\left(j\right)=\{\begin{array}{cc}0& \mathrm{if}\mathrm{the}t-\mathrm{gate}\mathrm{is}\mathrm{open},\\ 1& \mathrm{otherwise}\end{array}& \left(58\right)\end{array}$

This equation follows from the fact that in the FIG. 11, the capacitors are connected in parallel and thus the total capacitance of the circuit is the sum of all capacitances when each t-gate is a short. When the j'th t-gate is open, the associated capacitor C.sub.j is disconnected from the circuit, effectively removing it. Thus, for a circuit containing N capacitors

[00069]$\begin{array}{cc}{C}_{\mathrm{eff}}=\underset{j=1}{\overset{N}{.Math.}}\left(j\right)C_j.& \left(59\right)\end{array}$

[0094] Some circuits such as the example circuit 1100 can comprise a plurality of capacitors connected in parallel. In such capacitance circuits, each capacitor in the plurality of capacitors can have a different capacitance from any other capacitor in the capacitance circuit. In some capacitance circuits, each capacitor of a plurality of capacitors can have a capacitance that is twice a capacitance of at least another capacitor in the capacitance circuit.

[0095] In a general case of a circuit comprising multiple free nodes, the self and mutual capacitances of the circuit can be replaced with tunable capacitance circuit modules such as the circuit depicted in FIG. 11 but with N capacitors, as two distinct tunable capacitance circuits can have different numbers of capacitors. Since a t-gate can behave as a switch, each tunable capacitance circuit may be tuned to have a capacitance in the range 0 to 2.sup.N1 where N is the number of t-gates in a given tunable capacitance module. For instance, the off-diagonal term C.sub.ij in eq. (50) may be tuned to be in the range 0 to (2.sup.N1). The self-capacitances may also be tuned to be in the range 0 to 2.sup.N1. As such, the Maxwell capacitance matrix can be written as

[00070]$\begin{array}{cc}{C}_{\mathrm{eff}}=\left[\begin{array}{cccc}{.Math.}_{j=1}^n{C}_{1j}^{\left(t\right)}& -C_{12}^{\left(t\right)}& .Math.& -C_{1n}^{\left(t\right)}\\ -C_{21}^{\left(t\right)}& {.Math.}_{j=1}^n{C}_{2j}^{\left(t\right)}& .Math.& -C_{2n}^{\left(t\right)}\\ .Math.& .Math.& .Math.& .Math.\\ -C_{n1}^{\left(t\right)}& -C_{n2}^{\left(t\right)}& .Math.& {.Math.}_{j=1}^n{C}_{\mathrm{nj}}^{\left(t\right)}\end{array}\right],& \left(60\right)\end{array}$

where the superscript t in

[00071]$C_{\mathrm{ij}}^{\left(t\right)}$

indicates that the capacitance C.sub.ij may be tuned to take a value in the range 0 to 2.sup.N1 depending on which t-gates are shorts or opened for the tunable capacitance circuit used between free nodes i and j. An example circuit comprising multiple nodes that are interconnected with each other by tunable capacitance circuits that can be used to tune a Maxwell capacitance matrix associated with the system is depicted in FIG. 12.

[0096] FIG. 12 depicts an example circuit 1200 comprising a tunable capacitance network consisting essentially of interconnected wires intersecting at a plurality of nodes formed by nodes 1204. Selected pairs of nodes 1204 are interconnected by a tunable capacitance circuit 1206 and one or more of the nodes 1204 are connected to the common ground 1208 by a tunable capacitance circuit 1202. In other words, the circuit 1200 comprises a plurality of tunable capacitance circuits formed by the tunable capacitance circuits 1202 and the tunable capacitance circuits 1206. A circuit 1200 can also comprise one or more voltage sources (not pictured) configured to provide respective voltages relative to a common ground. Each tunable capacitance circuit 1202 and each tunable capacitance circuit 1206 can comprise a circuit configuration similar to the circuit depicted in FIG. 6B, wherein a plurality of switchable capacitors are connected in parallel, and each switchable capacitor of a plurality of the switchable capacitors comprises an active switching element connected in series with a corresponding capacitor. Each active switching element of each switchable capacitor of each plurality of the switchable capacitors can comprise an nMOS transistor such as depicted in FIG. 5A and FIG. 5C, a pMOS transistor such as depicted in FIG. 5B and FIG. 5D, or some combination thereof such as depicted in FIG. 6A and FIG. 6B. In other words, each active switching element comprises a transistor having three or more terminals including at least a first terminal connected to a first voltage source of the one or more voltage sources and a second terminal and a third terminal, wherein the second terminal and third terminal are configured to connect a corresponding capacitor to the tunable capacitance network in a closed switch state and to disconnect the corresponding capacitor from the tunable capacitance network in an open switch state. In some implementations, the first voltage source can be configured to provide a voltage that is lower than a threshold voltage of the transistor.

[0097] In some implementations, external circuitry can be configured to interact with a circuit architecture or a circuit, or portions thereof. Some implementations of external circuitry can interact with a circuit architecture by applying voltages to or reading voltages from a circuit architecture or portions thereof. For instance, control circuitry can be configured to apply control signals or generate voltages to be applied to a circuit. In some examples, readout circuitry configured to read, sample, and/or store voltages from a circuit. Some implementations of readout circuitry can comprise at least one voltage sampling circuit connected to a corresponding node of the tunable capacitance network such that the voltage sampling circuit is configured to record one or more voltage samples. In such implementations, a measurement can be performed wherein all closed active switching elements in switchable capacitors in a first tunable capacitance circuit of the plurality of tunable capacitance circuits are in a closed switch state during recording of at least one of the voltages samples. In some examples, the closed switching elements can be configured to: individually dissipate power by a resistance between the second and third terminals of the closed active switching element larger than resistances over any of the wires that connect any of the tunable capacitance circuits to any node in the tunable capacitance network, and collectively provide an effective capacitance of the first tunable capacitance circuit that is substantially equal to a sum of capacitances of all capacitors connected to the closed active switching elements.

[0098] In some implementations, circuitry configured to apply control signals to a circuit architecture, or portions thereof, can be positioned on a separate integrated circuit chip or device as the circuit architecture. In some examples, control signals applied to a circuit or signals produced by a circuit can be weak. In some implementations, to mitigate weak signals, circuitry configured to apply control signals to a circuit architecture, or portions thereof, can be positioned in proximity to the circuit architecture, i.e., on the same integrated circuit chip or device that comprises the circuit architecture. In some implementations, circuitry configured to readout signals from a circuit architecture, or portions thereof, can be positioned in proximity to the circuit architecture. i.e., on the same integrated circuit chip or device that comprises the circuit architecture. Positioning one or both of the readout circuitry or the control circuitry in proximity to a circuit architecture can be useful to mitigate losses associated with transmitting weak signals over larger distances.

[0099] The effective capacitance matrix C.sub.eff given in eq. (60) can identically be obtained from eq. (48) when considering island charges. For convenience, eq. (48) is reproduced

[00072]$\begin{array}{cc}{C}_{\mathrm{eff}}=C_f-C_{\mathrm{fi}}{C}_i^{-1}{C}_{\mathrm{fi}}^T.& \left(61\right)\end{array}$

In eq. (61), C.sub.f is the standard Maxwell capacitance matrix when all t-gates are shorts since in this case there are no island charges.

[0100] Without intending to be bound by theory, the following is an example of a theoretical model for illustrating features. Let C.sub.f be an MM matrix. Suppose all t-gate circuits are short except for one in the tunable capacitance circuit for the capacitor

[00073]$C_{\mathrm{ij}}^{\left(t\right)}.$

In this case a charge island is created (say with capacitance

[00074]$C_{\mathrm{ij}}^{\left(1\right)}).$

Now

[00075]$C_i^{-1}=1/C_{\mathrm{ij}}^{\left(1\right)}$

and the M1 matrix C.sub.fi can non-zero elements given by

[00076]$C_{\mathrm{ij}}^{\left(1\right)}$

in rows i and j. The product

[00077]$C_{\mathrm{fi}}{C}_i^{-1}{C}_{\mathrm{fi}}^T$

can be an MM matrix which is non-zero only in row i and column j with value

[00078]$C_{\mathrm{ij}}^{\left(1\right)}.$

As such, the row i and column j of C.sub.f can be reduced by

[00079]$C_{\mathrm{ij}}^{\left(1\right)}.$

[0101] In general, if there are k open t-gates, a circuit can contain k charge islands. The matrix C.sub.i.sup.1=diag(1/C.sub.1, . . . , 1/C.sub.k) (where for notational simplicity, the j'th charge island is assumed to have capacitance C.sub.j). The matrix C.sub.fi can be Mk with a non-zero entry in row i and column i if the i'th free node has a mutual capacitance with the t'th island charge (and if non-zero, it can have capacitance C.sub.t). Performing the multiplication

[00080]$C_{\mathrm{init}}=C_i^{-1}{C}_{\mathrm{fi}}^T$

results in a kM matrix which is 1 if in row s and column t if there is an mutual capacitance between island charge s and free node t. Otherwise the element of C.sub.int is zero. Performing the multiplication C.sub.fiC.sub.int results in an MM matrix where the row i and column j is

[00081]${.Math.}_i{C}_t^{\left(\mathrm{ij}\right)}\mathrm{where}{C}_t^{\left(\mathrm{ij}\right)}$

is a capacitance between an island charge and free nodes i and j. As such,

[00082]$C_{\mathrm{fi}}{C}_i^{-1}{C}_{\mathrm{fi}}^T$

can reduce the capacitance of row i and column

[00083]${\mathrm{jC}}_f\mathrm{by}{.Math.}_t{C}_t^{\left(\mathrm{ij}\right)}$

which is equivalent to the added island charges with mutual capacitances between free nodes i and j.

[0102] The effective capacitance matrix associated with tunable capacitance circuits can be written as

[00084]$\begin{array}{cc}{C}_{\mathrm{eff}}=\left[\begin{array}{cccc}{.Math.}_{j=1}^n{C}_{1j}^{\left(t\right)}& -C_{12}^{\left(t\right)}& .Math.& -C_{1n}^{\left(t\right)}\\ -C_{21}^{\left(t\right)}& {.Math.}_{j=1}^n{C}_{2j}^{\left(t\right)}& .Math.& -C_{2n}^{\left(t\right)}\\ .Math.& .Math.& .Math.& .Math.\\ -C_{n1}^{\left(t\right)}& -C_{n2}^{\left(t\right)}& .Math.& {.Math.}_{j=1}^n{C}_{\mathrm{nj}}^{\left(t\right)}\end{array}\right],& \left(62\right)\end{array}$

where

[00085]$C_{\mathrm{ij}}^{\left(t\right)}$

indicates that the capacitance C.sub.ij may be tuned to take a value in the range 0 to 2.sup.N1 depending on which t-gates are shorts or opened for the tunable capacitance circuit used between free nodes i and j (assuming there are N capacitors in parallel in the tunable capacitance circuit for C.sub.ij). As can be seen from eq. (62), such transformations cannot make the off-diagonal terms of C.sub.eff positive (since such terms are shifted by negative values). Further, the diagonal terms are also shifted by negative values.

[0103] Families of covariance matrices E can be mapped to the family of matrices given by

[00086]$C_{\mathrm{eff}}^{-1}$

through the use of trivial linear algebra transformations. A more restrictive case is introduced and then a more general case is considered. In what follows,

[00087]$C_{\mathrm{eff}}^{-1}$

is used instead of C.sub.eff due to the relationship in eq. (54). The Maxwell Capacitance matrices are positive definite, which means that the inverse matrices are also positive definite.

[0104] Case 1: Let E be the covariance matrix of some Gaussian distribution from which to sample, and let C.sub.eff be obtained from eq. (48) for some closed circuit comprising a t-gate switch. Suppose the off-diagonal elements of satisfy .sub.ij0 for all ij. Suppose further that using eq. (62), there exists a choice of elements of C.sub.fi in eq. (48) such that

[00088]${\left(C_{\mathrm{eff}}^{\left(\mathrm{ij}\right)}\right)}^{-1}={.Math.}_{\mathrm{ij}},$

where

[00089]${\left(C_{\mathrm{eff}}^{\left(\mathrm{ij}\right)}\right)}^{-1}$

is the element of

[00090]$C_{\mathrm{eff}}^{-1}$

in the i'th row and j'th column. In this setting,

[00091]$C_{\mathrm{eff}}^{-1}$

and differ in their diagonal elements. The difference is assumed to arise from a constant shift across all rows, i.e.

[00092]$\begin{array}{cc}{C}_{\mathrm{eff}}^{-1}=.Math.+I& \left(63\right)\end{array}$

for some constant . In this case, both and

[00093]$C_{\mathrm{eff}}^{-1}$

have the same eigenvectors, and the eigenvalues .sub. of are related to the eigenvalues .sub.C.sub.eff by .sub.C.sub.eff=.sub.+. Samples from the distribution (,) can be reconstructed given samples from (,C.sub.eff) when eq. (63) is satisfied.

[0105] Now let U be the matrix of eigenvectors for and

[00094]$C_{\mathrm{eff}}^{-1}$

(which is orthonormal since and

[00095]$C_{\mathrm{eff}}^{-1}$

is positive-definite and symmetric). Also let be the diagonal matrix of eigenvalues of . and

[00096]$C_{\mathrm{eff}}^{-1}$

can be written as

[00097]$\begin{array}{cc}.Math.=U{U}^T,& \left(64\right)\end{array}$$\begin{array}{cc}{C}_{\mathrm{eff}}^{-1}=U\left(+I\right)U^T,& \left(65\right)\end{array}$

[0106] Suppose a sample

[00098]$X^{}~\left(,C_{\mathrm{eff}}^{-1}\right)$

needs to be transformed into a sample X(,). A centered random variable can be defined

[00099]$Y^{}=X^{}-~\left(0,C_{\mathrm{eff}}^{-1}\right)$

and =+I. Y can be written as

[00100]$\begin{array}{cc}\begin{array}{c}{Y}^{}={U\left({}^{}\right)}^{1/2}z\\ ={U\left(+I\right)}^{1/2}z,\end{array}& \left(66\right)\end{array}$

where Z(0,I). The result in eq. (66) follows from the fact that [Y]=U().sup.1/2[Z]=0 and

[00101]$\begin{array}{cc}\begin{array}{c}\mathrm{Var}\left[Y^{}\right]=U{\left({}^{}\right)}^{1/2}\mathrm{Var}\left[Z\right]{\left({\left({}^{}\right)}^{1/2}\right)}^T{U}^T\\ =U{}^{}{U}^T=C_{\mathrm{eff}}^{-1}.\end{array}& \left(67\right)\end{array}$

From eq. (66), Z can be written

[00102]$\begin{array}{cc}Z={}^{-1/2}{U}^T{Y}^{},& \left(68\right)\end{array}$

where .sup.1/2 is just the element-wise inverse square root of the eigenvalues of

[00103]$C_{\mathrm{eff}}^{-1}.$

Defining Y=X, X is

[00104]$\begin{array}{cc}X=+U{}^{1/2}Z& \left(69\right)\end{array}$

where Z is computed from eq. (68). The matrix U requires knowledge of all the eigenvectors of

[00105]$C_{\mathrm{eff}}^{-1}.$

Having to diagonalize

[00106]$C_{\mathrm{eff}}^{-1}$

to compute U may be undesired due to the computational costs. However since

[00107]$C_{\mathrm{eff}}^{-1}$

can only take on a finite set of values (which are known based on the capacitances at fabrication time of the chip), the eigenvectors for each possible combination of

[00108]$C_{\mathrm{eff}}^{-1}$

can be pre-computed, and based on the choice of V.sub.g for each t-gate circuit or tunable capacitance circuit, the U matrix would be known.

[0107] Case 2: The following analysis can apply to any symmetric positive definite matrices (and thus to

[00109]$C_{\mathrm{eff}}^{-1}$

and ). The following eigenvalue decomposition can be performed

[00110]$\begin{array}{cc}{C}_{\mathrm{eff}}^{-1}=U_e{}_e{U}_e^T& \left(70\right)\end{array}$$\begin{array}{cc}.Math.=U_s{}_s{U}_s^T,& \left(71\right)\end{array}$

where U.sub.e and U.sub.s are orthogonal matrices whose columns are the eigenvectors of

[00111]$C_{\mathrm{eff}}^{-1}$

and . Further, the matrices .sub.e and .sub.s are diagonal matrices whose diagonal elements are eigenvalues of

[00112]$C_{\mathrm{eff}}^{-1}$

and .

[0108] Let

[00113]$X^{}\left(,C_{\mathrm{eff}}^{-1}\right).$

Y can be defined as Y=X. The samples Y can be transformed to the standard normal space using eigenvalues and eigenvectors of

[00114]$C_{\mathrm{eff}}^{-1}$

as

[00115]$\begin{array}{cc}Z={}_e^{-1/2}{U}_e^T{Y}^t,& \left(72\right)\end{array}$

where Z(0,I). Next, the standardized samples Z can be scaled to match the covariance matrix of

[00116]$\begin{array}{cc}Y=U_s{}_s^{-1/2}Z,& \left(73\right)\end{array}$

upon which X=+Y(,).

[0109] Case 3: Suppose that the off-diagonal elements of

[00117]$C_{\mathrm{eff}}^{-1}$

are identical to those of (as in Case 1). However, multiple diagonal elements of

[00118]$C_{\mathrm{eff}}^{-1}$

can differ from . That is, can be written

[00119]$\begin{array}{cc}.Math.=C_{\mathrm{eff}}^{-1}+\mathrm{diag}\left(c_1,.Math.,c_n\right),& \left(74\right)\end{array}$

with c.sub.i for all i{1, . . . , n}. diag(c.sub.1, . . . , c.sub.n) is assumed to act as a small perturbation of

[00120]$C_{\mathrm{eff}}^{-1}.$

Let .sub.1, .sub.2, . . . , .sub.n be the eigenvalues of

[00121]$C_{\mathrm{eff}}^{-1}$

and v.sub.1, . . . , v.sub.n be its eigenvectors, which as in Case 1 may be pre-computed since the range of values for C.sub.eff are finite. Since C.sub.eff.sup.1 is symmetric and positive-definite, it can be written as

[00122]$\begin{array}{cc}{C}_{\mathrm{eff}}^{-1}=V{V}^T& \left(75\right)\end{array}$

where V is an orthonormal matrix whose columns are eigenvectors of

[00123]$C_{\mathrm{eff}}^{-1},$

and [0110] =diag(.sub.1, .sub.2, . . . , .sub.n) is the matrix of eigenvalues. can be written

[00124]$\begin{array}{cc}.Math.=C_{\mathrm{eff}}^{-1}+D& \left(76\right)\end{array}$

where D=diag(c.sub.1, . . . , c.sub.n).

[0111] The first-order correction to the eigenvalues of

[00125]$C_{\mathrm{eff}}^{-1}$

due to D is given by the Rayleigh quotient for the unperturbed eigenvectors. Given the eigenvector v.sub.i of

[00126]$C_{\mathrm{eff}}^{-1},$

the eigenvalue of can be approximated as

[00127]$\begin{array}{cc}{}_i^{}{}_i+v_i^T{\mathrm{Dv}}_i,& \left(77\right)\end{array}$

where it is assumed that the eigenvectors v.sub.i are normalized. The perturbed eigenvectors are given by

[00128]$\begin{array}{cc}{v}_i^{}{v}_i+\underset{ji}{.Math.}\frac{v_j^T{\mathrm{Dv}}_i}{{}_i-{}_j}{v}_j.& \left(78\right)\end{array}$

[0112] The steps in eqs. (77) and (78) can be iterated to obtain better approximations to the eigenvalues and eigenvectors of . In other words, this process can comprise iteratively calculating one or more eigenvectors. With the approximate eigenvalues and eigenvectors of given in eqs. (77) and (78), the steps in Case 2 above can be repeated to obtain samples X(,) given samples

[00129]$X^{}~\left(,C_{\mathrm{eff}}^{-1}\right).$

Note that such computations can much more efficient than having to diagonalize E as can be needed for instance in Case 2.

[0113] Without intending to be bound by theory, the following is an example of a theoretical model for deriving eq. (78). Consider two symmetric and positive-definite matrices A and B, with

[00130]$\begin{array}{cc}B=A+D& \left(79\right)\end{array}$

where D is a diagonal matrix that acts as a small perturbation. Since A is symmetric and positive-definite, its eigenvectors {v.sub.1, v.sub.2, . . . , v.sub.n} form an orthonormal basis. The eigenvalues of A can also be denoted by {.sub.1, .sub.2, . . . , .sub.n}.

[0114] The Rayleigh quotient for a vector x with respect to the matrix B can be defined as

[00131]$\begin{array}{cc}\begin{array}{c}{R}_B\left(x\right)=\frac{x^T\mathrm{Bx}}{x^{T}x}\\ =\frac{x^T\mathrm{Ax}}{x^{T}x}+\frac{x^T\mathrm{Dx}}{x^{T}x}.\end{array}& \left(80\right)\end{array}$

For the eigenvector v.sub.i,

[00132]$\begin{array}{cc}{R}_B\left(v_i\right)={}_i+v_i^T{\mathrm{Dv}}_i,& \left(81\right)\end{array}$

where the fact that the vectors {v.sub.1, v.sub.2, . . . , v.sub.n} are normalized was used. The approximate eigenvalues .sub.i of B are given by

[00133]$\begin{array}{cc}{}_i^{}={}_i+v_i^T{\mathrm{Dv}}_i.& \left(82\right)\end{array}$

[0115] Since D is a small perturbation, the approximate eigenvectors of B can be written to leading order as

[00134]$\begin{array}{cc}{v}_i^{}{v}_i+v_i.& \left(83\right)\end{array}$

A goal can then be to compute the elements Svi. Using eq. (79) and the fact that Av.sub.i=.sub.iv.sub.i, the eigenvalue equation for B can be written as

[00135]$\begin{array}{cc}B\left(v_i+v_i\right)=\left({}_i+v_i^T{\mathrm{Dv}}_i\right)\left(v_i+v_i\right)& \left(84\right)\end{array}$$\left(A+D\right)\left(v_i+v_i\right)={}_i{v}_i+{}_i{v}_i+\left(v_i^T{\mathrm{Dv}}_i\right)v_i$${}_i{v}_i+A{v}_i+{\mathrm{Dv}}_i={}_i{v}_i+{}_i{v}_i+\left(v_i^T{\mathrm{Dv}}_i\right)v_i$$A{v}_i+{\mathrm{Dv}}_i={}_i{v}_i+\left({}_i\right)v_i.$

Rearranging the terms in last line of eq. (84),

[00136]$\begin{array}{cc}\left(A-{}_{i}I\right)v_i=-{\mathrm{Dv}}_i+\left(v_i^T{\mathrm{Dv}}_i\right)v_i.& \left(85\right)\end{array}$

The perturbation v.sub.i can be expressed as a sum of the eigenvectors of A as

[00137]$\begin{array}{cc}{v}_i=\underset{ji}{.Math.}{c}_{\mathrm{ij}}{v}_i.& \left(86\right)\end{array}$

Inserting eq. (86) into eq. (85) and using the eigenvalue equation for A,

[00138]$\begin{array}{cc}\underset{ji}{.Math.}{c}_{\mathrm{ij}}\left({}_j-{}_i\right)v_j=-{\mathrm{Dv}}_i+\left(v_i^T{\mathrm{Dv}}_i\right)v_i.& \left(87\right)\end{array}$

Multiplying eq. (87) to the left by v.sub.k (with ki) and using the orthonormal properties of the eigenvectors,

[00139]$\begin{array}{cc}{c}_{\mathrm{ik}}\left({}_k-{}_i\right)=-v_k^T{\mathrm{Dv}}_i,& \left(88\right)\end{array}$
so that

[00140]$\begin{array}{cc}{c}_{\mathrm{ik}}=-\frac{v_k^T{\mathrm{Dv}}_i}{{}_k-{}_i}.& \left(89\right)\end{array}$

Using eqs. (86) and (89), the approximate eigenvalues of B to leading order are given by

[00141]$\begin{array}{cc}{v}_i^{}{v}_i-\underset{ji}{.Math.}\left(\frac{v_j^T{\mathrm{Dv}}_i}{{}_j-{}_i}\right)v_j.& \left(90\right)\end{array}$

Using the updated eigenvectors, the steps leading to eq. (90) can be iterated to get better approximations for the eigenvalues and eigenvectors of B. In other words, this process can comprise iteratively calculating one or more eigenvectors.

[0116] FIG. 13 depicts a flowchart 1300 containing an example method for configuring a circuit for generating samples from a target distribution. The method comprises receiving 1302 a matrix representing parameters associated with the target distribution, tuning 1304 a plurality of tunable capacitance circuits in a tunable capacitance network based at least in part on respective elements of the received matrix, wherein the tunable capacitance network consists essentially of interconnected wires intersecting at a plurality of nodes with selected pairs of the nodes interconnected by a respective tunable capacitance circuit and one or more of the nodes connected to a common ground by a respective tunable capacitance circuit, recording 1306 respective voltage samples from a plurality of nodes of the tunable capacitance network, and storing 1308 a linear transformation of a vector of the voltage samples based at least in part on the received matrix.

[0117] Some circuits that can sample a Gaussian distribution can incorporate a measurement circuit that can measure voltage fluctuations of the free nodes. Some measurement circuits can be non-destructive. Some circuits capable of performing non-destructive measurements can be configured such that the measurements do not alter a voltage sample that is being recorded by more than 1% during a particular non-destructive voltage measurement. FIG. 14A depicts an example circuit 1400 that can perform a non-destructive measurement of a voltage node 1404. The circuit 1400 contains a probabilistic circuit 1402, a sense amplifier 1406, a gain amplifier 1408, and an output node 1410. In some example circuits, the gain amplifier 1408 can be associated with a gain close to 0 dB.

[0118] The input capacitance of a sense amplifier, sometimes referred to as a sense amp, can load the state of a free node being measured and in some implementations, can be destructive. As such, a small device can be used to act as the input state of the sense amplifier. This device makes the input capacitance in the same order or smaller than the probabilistic circuit whose output is the free node being measured and which drives the sense amplifier. FIG. 14B depicts an example circuit 1450 that can be utilized as a sense amplifier in circuit 1400. The circuit 1450 comprises a node 1452 associated with a voltage V.sub.in and a node 1454 associated with a voltage Vow. The circuit 1450 also comprises a capacitor 1456 associated with a capacitance C.sub.gd, a capacitor 1458 associated with a capacitance C.sub.gs, a current source 1460 associated with a current I.sub.1, and a current source 1462 associated with a current I.sub.2 The circuit 1450 also comprises a pnp transistor 1464 and an npn transistor 1466. A source-follower configuration with feedback as the buffer can also be used. The example circuit 1450 has two capacitances, namely C.sub.gs and C.sub.gd that load the state of the free node being measured. In a source-follower configuration, the input and output nodes are the same and the C.sub.gs capacitance is not seen by the input node. A capacitor can be seen as a load if it needs to be charged or discharged. If the voltage across the capacitor doesn't charge, then there is no charging or discharging and hence it is not loading which is what happens for C.sub.gs since the input and output of the sense amplifier are the same. This input and output can be similar when a gain is close to 0 dB.

[0119] In some implementations, C.sub.gd is the only capacitance seen by the input node and can be half that of C.sub.gs. Overall the measurement is non-destructive because the measurement can have minimal to no-impact on the free node that is being measured as the free node can be loaded with a very small capacitance.

[0120] In some implementations, a circuit architecture can be formed as part of a system. A system can be implemented in various configurations, including as a single apparatus or as a combination of one or more apparatuses that collectively perform the functions of a system. In some examples, the one or more apparatuses can form a device, i.e., a system-on-a-chip, or the one or more apparatuses can be separate devices.

[0121] In some implementations, a system can be formed from one or more integrated circuit (IC) chips comprising portions of a circuit architecture. Some circuit architectures can be distributed across multiple chips or consolidated onto a single chip. Some chips can comprise multiple layers of material. In some examples, portions of a circuit architecture can be formed across several layers of devices.

[0122] Some systems can comprise analog, digital, or mixed-signal circuitry configured to perform functions such as signal processing, voltage regulation, or data acquisition. Some systems can comprise interface or control circuitry configured to perform functions such as applying bias voltages, measuring voltages, or interfacing with components of the circuit. In some examples, control circuitry can be implemented in one or more dedicated regions of an IC, or distributed throughout a circuit architecture. In some examples, control circuitry can comprise components such as a field-programmable gate array (FPGA), an application specific integrated circuit (ASIC), one or more processors or processor cores, including central processing unit(s) (CPU(s)) and/or graphics processing unit(s) (GPU(s)), or other computing devices or modules capable of executing a program (e.g., software and/or firmware) comprising instructions or other compiled or executable code. The electronic circuitry can also include at least one data storage system (e.g., including volatile and non-volatile memory, and/or storage media). The program may be provided on a computer-readable storage medium, or delivered over a communication medium such as a wired or wireless network, to a device module where it can be stored and eventually executed when read by the device to perform the procedures of the program.

[0123] In some implementations, portions of a circuit architecture and control circuitry can be arranged in a flip-chip configuration to allow for three-dimensional integration of multiple chips or substrates. Some flip-chip configurations comprise conductive structure such as wire bonds, microbumps, or vias to facilitate electrical communication between multiple layers or chips.

[0124] While the disclosure has been described in connection with certain embodiments, it is to be understood that the disclosure is not to be limited to the disclosed embodiments but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims, which scope is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures as is permitted under the law.