TRANSFER DIE FOR MICRO-TRANSFER PRINTING

Abstract

A method of manufacturing a transfer die. The manufactured transfer die comprises a semiconductor device suitable for bonding to a silicon-on-insulator wafer. The method comprises the steps of providing a non-conductive isolation region in a semiconductor stack, the semiconductor stack comprising a sacrificial layer above a substrate; and etching an isolation trench into the semiconductor stack from an upper surface thereof, such that the isolation trench extends only to a region of the semiconductor stack above the sacrificial layer. The isolation trench and the non-conductive isolation region together separate a bond pad from a waveguide region in the optoelectronic device.

Claims

1. A method of manufacturing a transfer die, the transfer die comprising an optoelectronic device suitable for bonding to a silicon-based platform via a transfer print process, the method comprising the steps of: providing a non-conductive isolation region in a semiconductor stack, the semiconductor stack comprising a sacrificial layer above a substrate; and etching an isolation trench into the semiconductor stack from an upper surface thereof, such that the isolation trench extends only to a region of the semiconductor stack above the sacrificial layer, wherein the isolation trench and the non-conductive isolation region together separate a bond pad from a waveguide region in the optoelectronic device.

2. The method of claim 1, wherein the non-conductive isolation region is an iron-doped layer in the semiconductor stack, and wherein the isolation trench is etched to the iron-doped layer to separate the waveguide region from the bond pad.

3. The method of claim 1, wherein the non-conductive isolation region is created in the semiconductor stack by implantation.

4. The method of claim 3, wherein the implanted non-conductive isolation region extends from a bottom of the etched isolation trench to the sacrificial layer.

5. The method of claim 1, further comprising the step of: providing a Benzocyclobutene, BCB, fill in the isolation trench.

6. The method of claim 1, further comprising the step of: epitaxially growing an iron-doped material in the isolation trench from the non-conductive isolation region.

7. The method of claim 1, further comprising the step of: epitaxially growing an iron-doped material from the non-conductive isolation region to form the bond pad.

8. The method of claim 1, wherein the semiconductor stack comprises a first doped layer, a second doped layer and an optically active layer, the first doped layer containing dopants of a different species to the second doped layer.

9. The method of claim 1, further comprising the step of: etching away the sacrificial layer to form an undercut region which spaces the optoelectronic device from the substrate.

10. A method of manufacturing a transfer die, the manufactured transfer die comprising an optoelectronic device suitable for bonding to a silicon-based platform via a transfer print process, the method comprising the steps of: creating a first doped region in a portion of an un-doped region of a semiconductor stack, the semiconductor stack comprising an optically active layer above a second doped region, wherein the first doped region contains dopants of a different species to the second doped region; and etching an isolation trench in the semiconductor stack to the second doped region, wherein the isolation trench separates a waveguide region comprising the first doped region from a remaining portion of the un-doped region, the remaining portion of the un-doped region forming an un-doped bond pad of the optoelectronic device.

11. The method of claim 10, wherein the first doped region is created in the semiconductor stack by localised diffusion of a dopant.

12. The method of claim 10, wherein the method further comprises the step of: providing a Benzocyclobutene, BCB, fill in the isolation trench.

13. The method of claim 10, wherein the semiconductor stack is located above a substrate.

14. The method of claim 13, wherein the semiconductor stack comprises a sacrificial layer above the substrate, and wherein the method further comprises the step of: etching away the sacrificial layer.

15. (canceled)

16. (canceled)

17. A transfer die comprising an optoelectronic device and a substrate, the optoelectronic device being suitable for bonding to a silicon-based platform via a transfer print process, wherein the optoelectronic device comprises a waveguide region for guiding light through the optoelectronic device, a bond pad for providing an electrical connection to the optoelectronic device, an isolation trench and a non-conductive isolation region, and wherein the bond pad is separated from the waveguide region by the isolation trench and the isolation region.

18. The transfer die of claim 17, wherein the isolation region is an iron-doped isolation region.

19. The transfer die of claim 17, wherein the isolation trench contains an iron-doped material.

20. The transfer die of claim 17, wherein the bond pad comprises an iron-doped material.

21. The transfer die of claim 17, wherein the isolation region is an ion-implantation isolation region.

22. (canceled)

23. (canceled)

24. (canceled)

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0135] Embodiments of the invention will now be described by way of example with reference to the accompanying drawings in which:

[0136] FIG. 1 is a schematic cross-section of a transfer die according to an embodiment of the invention;

[0137] FIGS. 2a and 2b illustrate a method of manufacturing a transfer die according to an embodiment of the invention;

[0138] FIG. 3 illustrates a schematic cross-section of a transfer die according to another embodiment of the invention;

[0139] FIG. 4 illustrates a schematic cross-section of a transfer die according to another embodiment of the invention;

[0140] FIGS. 5a-5c illustrate a method of manufacturing a transfer die according to another embodiment of the invention;

[0141] FIG. 6 illustrates a hybrid III-V/Si optoelectronic device according to an embodiment of the invention; and

[0142] FIG. 7 illustrates a hybrid III-V/Si optoelectronic device according to an embodiment of the invention.

DETAILED DESCRIPTION AND FURTHER OPTIONAL FEATURES

[0143] Aspects and embodiments of the present invention will now be discussed with reference to the accompanying figures. Further aspects and embodiments will be apparent to those skilled in the art. The detailed description set forth below in connection with the appended figures is intended as a description of exemplary embodiments of the invention and is not intended to represent the only forms in which the present invention may be constructed or utilized.

[0144] FIG. 1 illustrates a schematic cross-section of a transfer die, also referred to as a device coupon, 1 according to an embodiment of the invention. The cross-section looks along the line (x) along which light is guided by a waveguide 10 of the device. The transfer die 1 comprises a III-V optoelectronic device 2 and a native III-V substrate 3. The transfer die 1 is suitable for use in an MTP process, in which the optoelectronic device 2 is transferred, using an elastomer stamp, from the native substrate 3 to a non-native platform e.g. a silicon-based platform. The optoelectronic device 2 can then be bonded to the non-native silicon-based platform to form a hybrid III-V/Si optoelectronic device.

[0145] The optoelectronic device 2 is spaced from the substrate 3 by an undercut region 4, but is mechanically connected to the substrate 3 by tethers 5. In the MTP process, an elastomer stamp lifts the optoelectronic device 2 from the substrate 3, thereby severing the tethers 5, such that the optoelectronic device 2 can then be transferred to the non-native platform.

[0146] The optoelectronic device 2 comprises a waveguide region 10, and a bond pad 11. The waveguide region 10 is a region of the optoelectronic device 2 in which an optical mode propagates, and is formed by a p-doped region 12, an optically active layer 13, and an n-doped region 14. The optically active layer 13 (e.g. multiple quantum well layer) separates the p-doped region 12 from the n-doped region 14, with the optically active layer 13 on top of the n-doped region 14, and the p-doped region 12 on top of the optically active layer 13.

[0147] An isolation trench 15 extends vertically into the optoelectronic device 2 from a top surface of the optoelectronic device 2 towards the substrate 3. The isolation trench 15 laterally separates the waveguide region 10 and the bond pad 11, and contains a BCB fill.

[0148] A non-conductive ion-implantation isolation region 16 is formed beneath the isolation trench 15. The ion-implantation isolation region 16 extends from a lower end (i.e. bottom) of the isolation trench 15 to the lower surface of the optoelectronic device 2. Accordingly, the isolation trench 15 and the ion-implantation isolation region 16 together separate and thus isolate the waveguide region 10 from the bond pad 11.

[0149] The non-conductive ion-implantation isolation region may comprise hydrogen ions, helium ions, oxygen ions, or iron ions.

[0150] The waveguide region 10 also comprises a p+ doped 17 region on top of the p-doped region 12. A metal n-contact 18 is electrically connected to the n-doped region 14 and a p-contact 19 is electrically connected to the p+ doped region 17 and the bond pad 11.

[0151] Although not shown in the figures, in a method of manufacturing the transfer die 1 of FIG. 1, a III-V semiconductor stack is provided. The semiconductor stack is located above a native substrate 3, and comprises a sacrificial layer on top of the native substrate 3, an n-doped layer on top of the sacrificial layer, an optically active layer on top of the n-doped layer, a p-doped layer on top of the optically active layer, and a p+ doped layer on top of the p-doped layer.

[0152] The native substrate 3 may be an indium phosphide (InP) substrate, the sacrificial layer may be an indium gallium arsenide (InGaAs) sacrificial layer or aluminium indium arsenide (AllnAs) sacrificial layer, the n-doped layer may be an n-doped indium phosphide (N-lnP) layer, the optically active layer may be an aluminium indium gallium arsenide (AllnGaAs) multiple quantum well layer, the p-doped layer may be a p-doped indium phosphide (P-lnP) layer, and the p+ doped layer may be a p-doped indium gallium arsenide (P-lnGaAs) layer, for example.

[0153] An isolation trench 15 is etched in the semiconductor stack from the upper surface thereof, such that the isolation trench 15 extends vertically downwards into the semiconductor stack. Standard patterning and etching techniques are used.

[0154] The isolation trench 15 extends through the p+ doped layer, the p-doped layer, the optically active layer and into the n-doped layer. The isolation trench 15 terminates in the n-doped layer and therefore does not extend to/into the sacrificial layer. As such, the bottom of the isolation trench 15 is in the n-doped layer.

[0155] Next, ions (e.g. hydrogen, helium, oxygen or iron ions) are implanted in a portion of the n-doped layer from the bottom of the isolation trench 15 to form the ion-implantation region 16. This ion implantation makes the portion of the n-doped layer non-conductive such that the ion-implantation region 16 is non-conductive. The ion-implantation region 16 extends from the bottom of the isolation trench 15 to, or through, the sacrificial layer. Accordingly, the vertically-extending isolation trench 15 and the non-conductive ion-implantation region 16 together laterally space and isolate the waveguide region 10 from the bond pad 11.

[0156] Next, a BCB fill is provided in the isolation trench 15, which retains the separation and thus isolation of the bond pad 11 from waveguide region 10, but mechanically strengthens the optoelectronic device.

[0157] The sacrificial layer is etched away from underneath the n-doped layer to vertically space the optoelectronic device 2 from the native substrate 3. Standard etching techniques are used to etch away the sacrificial layer, leaving an undercut region 4, and tethers 5 mechanically connecting the optoelectronic device 2 and the substrate 3.

[0158] Also, a portion of the semiconductor stack is etched (using standard patterning and etching techniques) to the n-doped layer, and an n-contact 18 is electrically connected to the n-doped layer. A p-contact 19 is electrically connected to the p+ doped layer in the waveguide region 10 and the bond pad 11.

[0159] An alternative method of manufacturing a transfer die 100 according to an embodiment of the invention is illustrated in FIGS. 2a and 2b. FIG. 2b illustrates the manufactured transfer die 100.

[0160] In a first step of the method, illustrated in FIG. 2a, a III-V semiconductor stack 150 is provided.

[0161] The semiconductor stack 150 comprises a sacrificial layer 151 on top of a native substrate 103, an iron-doped layer 152 on top of the sacrificial layer 151, an n-doped layer 153 on top of the iron-doped layer 152, an optically active (multiple quantum well) layer 154 on top of the n-doped layer 153, a p-doped layer 155 on top of the optically active layer 154, and a p+ doped layer 156 on top of the p-doped layer 155.

[0162] The native substrate 103 may be an indium phosphide (InP) substrate, the sacrificial layer 151 may be an indium gallium arsenide (InGaAs) sacrificial layer, the iron-doped layer 152 may be an InP layer, the n-doped layer 153 may be an n-doped indium phosphide (N-lnP) layer, the optically active layer 154 may be an aluminium indium gallium arsenide (AllnGaAs) multiple quantum well layer, the p-doped layer 155 may be a p-doped indium phosphide (P-InP) layer, and the p+ doped layer 156 may be a p-doped indium gallium arsenide (P-InGaAs) layer, for example.

[0163] An isolation trench 115 (shown in FIG. 2b) is etched, using standard patterning and etching techniques, to the iron-doped layer 152. Specifically, the isolation trench 115 is etched such that the isolation trench 115 terminates in the iron-doped layer 152, and does not extend to the sacrificial layer 151.

[0164] The isolation trench 115 laterally separates and isolates a waveguide region 110 from a bond pad 111 (as shown in FIG. 2b). The waveguide region 110 is a region of the optoelectronic device 102 in which an optical mode propagates, and is formed by a p-doped region 112 (of the p-doped layer 155), the optically active layer 154, and an n-doped region 114 (of the n-doped layer 153).

[0165] The isolation trench 115 extends vertically from a top-surface of the optoelectronic device 2 to the iron-doped layer 152 such that the isolation trench 115 and the non-conductive iron-doped layer 152 together separate and thus isolate the bond pad 111 from the waveguide region 110.

[0166] Next, a BCB fill is provided in the isolation trench 115, which retains the separation and thus isolation of the bond pad 111 from waveguide region 110, but mechanically strengthens the optoelectronic device 102.

[0167] The sacrificial layer 151 is etched away from underneath the iron-doped layer 152 to vertically space the optoelectronic device 102 from the native substrate 103. Standard etching techniques (e.g. a wet etch using HF) are used to etch away the sacrificial layer 151, leaving an undercut region 104, and tethers 105 mechanically connecting the optoelectronic device 102 and the substrate 103.

[0168] Also, a portion of the semiconductor stack 150 is etched (using standard patterning and etching techniques) to the n-doped layer 153, and an n-contact 118 is electrically connected to the n-doped layer 153. A p-contact 119 is electrically connected to the p+ doped layer 156 in the waveguide region 110 and the bond pad 111.

[0169] In the manufactured transfer die 100 (see e.g. FIG. 2b), the optoelectronic device 102 is spaced from the native substrate 103 by the undercut region 104, but is mechanically connected to the substrate 103 by the tethers 105.

[0170] The isolation trench 115 and the iron-doped region 152 together separate and thus isolate the waveguide region 110 and the bond pad 111.

[0171] FIG. 3 illustrates a variant transfer die 200 according to an embodiment of the invention. Transfer die 200 comprises similar features to transfer die 100 shown in FIG. 2b, with like features having corresponding reference numerals (e.g. iron-doped layer 252 corresponds to iron-doped layer 152).

[0172] Specifically, transfer die 200 is similar to transfer die 100 except that rather than providing a BCB fill in isolation trench 215, an iron-doped material is epitaxially grown from the iron-doped layer 252 in the isolation trench 215, such that the isolation trench 215 contains an iron-doped material fill 260. The iron-doped material fill 260 mechanically strengthens the optoelectronic device 202, whilst retaining the isolation of the bond pad 211 from the waveguide region 210.

[0173] FIG. 4 illustrates a further variant transfer die 300. Transfer die 300 comprises similar features to transfer die 200 shown in FIG. 3, with like features having corresponding reference numerals (e.g. iron-doped layer 352 corresponds to iron-doped layer 252).

[0174] Transfer die 300 is similar to transfer die 200 except that the bond pad is an iron-doped bond pad 311 comprising an iron-doped material. In a method of manufacturing transfer die 300, a portion of the semiconductor stack on the lateral side of the isolation trench 215 opposite to the waveguide region 310 is removed, and iron-doped material is epitaxially grown from the iron-doped layer 352 to form an iron-doped bond pad 311. The iron-doped bond pad 311 is isolated from the waveguide region 310 because the iron-doped bond pad 311 is non-conductive.

[0175] FIGS. 5a-5c illustrate an alternative method of manufacturing a transfer die 400 according to another embodiment of the invention. The manufactured transfer die 400 is shown in FIG. 5c.

[0176] In a first step of the method, illustrated in FIG. 5a, a III-V semiconductor stack 450 is provided atop substrate 403.

[0177] The semiconductor stack 450 comprises a sacrificial layer 451 on top of the native substrate 403, an n-doped layer 453 on top of the sacrificial layer 451, an optically active (multiple quantum well) layer 454 on top of the n-doped layer 453, and an un-doped layer 470 on top of the optically active layer 454.

[0178] The native substrate 403 may be an indium phosphide (InP) substrate, the sacrificial layer 451 may be an indium gallium arsenide (InGaAs) sacrificial layer, the n-doped layer 453 may be an n-doped indium phosphide (N-lnP) layer, the optically active layer 454 may be an aluminium indium gallium arsenide (AllnGaAs) multiple quantum well layer, and the un-doped layer 470 may be an un-doped indium phosphide (InP) layer, for example.

[0179] Next, as shown in FIG. 5b, a p-doped region 471 is created in a portion of the un-doped layer 470 by localised diffusion of a p-dopant or by implantation using ions that result in p-doping, for example zinc. The p-doped region 471 extends downwards into the semiconductor stack 450 towards the optically active layer 454.

[0180] A p+ doped region 472 is then created in the p-doped region 471 by further localised diffusion of a p-dopant.

[0181] Next, as illustrated in FIG. 5c, an isolation trench 415 is etched into the semiconductor stack 450 from an upper surface thereof to the n-doped layer 453. The isolation trench 415 laterally separates and thus isolates a waveguide region 410 comprising the p-doped region 471 and the p+ doped region 472 from an un-doped bond pad 411. Standard patterning and etching techniques are used.

[0182] Next, a BCB fill is provided in the isolation trench 415, which retains the isolation of the un-doped bond pad 411 from waveguide region 410, but mechanically strengthens the optoelectronic device 402.

[0183] The sacrificial layer 451 is etched away from underneath the n-doped layer 453 to vertically space the optoelectronic device 402 from the native substrate 403. Standard etching techniques are used to etch away the sacrificial layer 451, leaving an undercut region 404, and tethers 405 mechanically connecting the optoelectronic device 402 and the substrate 403.

[0184] Also, a portion of the semiconductor stack 450 is etched (using standard patterning and etching techniques) to the n-doped layer 453, and an n-contact 418 is electrically connected to the n-doped layer 453. A p-contact 419 is electrically connected to the p+ doped layer 472 in the waveguide region 410 and the un-doped bond pad 411.

[0185] In the manufactured transfer die 400 (see e.g. FIG. 5c), the optoelectronic device 502 is spaced from the native substrate 403 by the undercut region 404, but is mechanically connected to the substrate 403 by the tethers 405.

[0186] The p-doped region 471 and the p+ doped region 472 are confined to the waveguide region 410.

[0187] As the bond pad 411 is un-doped, and laterally separated from the waveguide region 410 by the isolation trench 415, parasitic capacitance in the un-doped bond pad 411 is reduced.

[0188] FIG. 6 shows a hybrid III-V/Si optoelectronic device 1000 according to an embodiment of the invention. The hybrid III-V/Si optoelectronic device comprises a III-V optoelectronic device 1002 bonded to a silicon-based platform 1003. The hybrid III-V/Si optoelectronic device is formed by a MTP process. In the MTP process, the III-V optoelectronic device of a transfer die (such as transfer die 1, 100, 200, 300, 400 shown in FIGS. 1-5 respectively), is transferred using an elastomer stamp from a native substrate to the silicon-based platform 1003 to form hybrid III-V/Si optoelectronic device 1000.

[0189] Optoelectronic device 1002 may be similar to any of optoelectronic devices 2, 102, 202, 302, 402 described above. In the example shown in FIG. 6, optoelectronic device 1002 is similar to optoelectronic device 102 shown in FIG. 2b. Alike reference numerals are provided for similar features.

[0190] Specifically, optoelectronic device 1002 comprises an iron-doped layer 1052, an n-doped region 1053 on top of the iron-doped layer 1052, an optically active (multiple quantum well) layer 1054 on top of the n-doped region 1053, a p-doped region 1055 on top of the optically active layer 1054, and a p+ doped region 1056 on top of the p-doped region 1055.

[0191] An isolation trench 1015 extends from an upper surface of p-doped region 1055 into the iron-doped layer 1052. The isolation trench 1015 laterally separates a waveguide region 1010 from a bond pad 1011. The waveguide region 1010 comprises the p-doped region 1055, the optically active layer 1054 and the n-doped region 1053. The isolation trench 1015 and the iron-doped layer 1052 together separate and thus isolate the bond pad 1011 from the waveguide region 1010.

[0192] A metal n-contact 1018 is electrically connected to the n-doped region 1053 and a metal p-contact 1019 is electrically connected to the p+ doped region 1056 and the bond pad 1011.

[0193] As shown in FIG. 6, a trench 1080 is formed in the silicon-based platform 1003 beneath the bond pad 1011. The trench 1080 may be etched using standard patterning and etching techniques before the optoelectronic device 1002 is positioned on and bonded to the platform 1003. The trench 1080 increases the distance between the bond pad 1011 and the silicon-based platform 1003, such that parasitic coupling between the silicon-based platform 1003 and the bond pad 1011 is reduced.

[0194] Another view of a manufactured hybrid III-V/Si optoelectronic device 1100 according to an embodiment of the invention is shown in FIG. 7. Similarly to hybrid III-V/Si optoelectronic device 1000, hybrid III-V/Si optoelectronic device 1100 comprises a III-V optoelectronic device 1102 bonded to a silicon-based platform 1103. The III-V/Si optoelectronic device 1102 comprises a waveguide region 1100 in which an optical mode propagates, and a bond pad 1111.

[0195] A trench 1180 is formed in the silicon-based platform 1003 beneath the bond pad 1111 in order to increase the distance between the bond pad 1111 and the silicon-based platform 1003, to thereby reduce the capacitance of the bond pad 1111.

[0196] While the invention has been described in conjunction with the exemplary embodiments described above, many equivalent modifications and variations will be apparent to those skilled in the art when given this disclosure. Accordingly, the exemplary embodiments of the invention set forth above are considered to be illustrative and not limiting. Various changes to the described embodiments may be made without departing from the spirit and scope of the invention.