STABLE CONTROL SYSTEMS EMPLOYING ONE-WAY RECTIFICATION AND INTERLEAVED BOOSTER

Abstract

A stable control system for a three-phase rectification controller circuit is provided. The stable control system filters voltage harmonics and performs attenuation feedback compensation on current harmonics to enable a rectification circuit to achieve high stability and low THDi, while performing filtering on a direct current bus voltage in the case of an unbalanced load, so as to filter out voltage harmonics and enable the circuit to support the unbalanced load. A stable control system for an interleaved direct current booster circuit is also provided. The stable control system equalizes inter-leg currents such that a battery has good dynamic effects and good current equalization performance.

Claims

1. A stable control system for an interleaved direct current booster circuit comprising: a first leg and a second leg connected in parallel to each other, the first leg being a direct current boost first leg and the second leg being a direct current boost second leg, the first leg and second leg each being provided with an inductor; and an inductive current difference loop controller, for respectively: acquiring inductive currents of the first leg and the second leg of the interleaved direct current booster, calculating an inductive current difference loop control parameter based on a preset transfer function and a difference between the inductive current of the direct current boost first leg and the inductive current of the direct current boost second leg, and calculating a difference loop duty cycle value according to the inductive current difference loop control parameter so as to use the difference loop duty cycle value for current equalization control of a current between battery legs, wherein the difference loop duty cycle value is used to calculate a current difference between the first leg and the second leg of the direct current booster, so as to determine, according to the current difference, whether current equalization is obtained between the first leg and the second leg of the direct current booster.

2. The system according to claim 1, further comprising: a direct current boost bus transient voltage controller, for: acquiring a direct current boost bus voltage set value, a direct current boost bus average voltage error compensation value, and a direct current boost bus voltage feedback positive terminal value and negative terminal value, calculating a direct current boost bus transient voltage control parameter based on a preset transfer function and a difference between a sum of the direct current boost bus voltage set value and the direct current boost bus average voltage error compensation value and the direct current boost bus voltage feedback positive terminal value and negative terminal value, and calculating a direct current boost voltage duty cycle value according to the direct current boost bus transient voltage control parameter; and a direct current boost leg duty cycle module, for respectively acquiring a direct current boost first leg duty cycle value and a direct current boost second leg duty cycle value according to the direct current boost voltage duty cycle value output by the direct current boost bus transient voltage controller and the difference loop duty cycle value output by the inductive current difference loop controller and according to a preset duty cycle calculation rule, wherein the direct current boost first leg duty cycle value and the direct current boost second leg duty cycle value are used to calculate a direct current boost bus feedback positive terminal value and negative terminal value.

3. The system according to claim 2, wherein the inductive current difference loop controller is a proportional hysteresis controller, and a preset transfer function thereof is: $D_{i_{dff}} (s) = K_{dff} \frac{s + a}{s + b},$ where K.sub.diff is a proportional feedforward gain, a is a hysteresis loop zero-point, b is a hysteresis loop pole, and s is a control function operator.

4. The system according to claim 3, wherein the preset duty cycle calculation rule includes: acquiring the direct current boost first leg duty cycle value according to a difference between the direct current boost voltage duty cycle value output by the direct current boost bus transient voltage controller and the difference loop duty cycle value output by the inductive current difference loop controller; and acquiring the direct current boost second leg duty cycle value according to a sum of the direct current boost voltage duty cycle value output by the direct current boost bus transient voltage controller and the difference loop duty cycle value output by the inductive current difference loop controller.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Embodiments of the present inventive concept are further described below with reference to the accompanying drawings:

[0027] FIG. 1 is a schematic structural diagram of a three-phase rectifier type I NPC topology;

[0028] FIG. 2 is a schematic structural diagram of a DC-DC boost/buck topology;

[0029] FIG. 3 is a schematic structural diagram of a rectification and boost topology of a dual-use direct current conversion module according to the prior art;

[0030] FIGS. 4(A) and 4(B) are schematic operation logic diagrams of an interleaved boost circuit of a dual-use direct current conversion module according to the prior art;

[0031] FIG. 5 is a schematic diagram of a topology of an interleaved boost circuit of a dual-use direct current conversion module according to the prior art;

[0032] FIG. 6 is a schematic diagram of pulse width modulation of an interleaved boost circuit of a dual-use direct current conversion module according to the prior art;

[0033] FIG. 7 is a schematic diagram of a rectification control subsystem according to an embodiment of the present inventive concept;

[0034] FIG. 8 is a bode plot of a transfer function of a rectification voltage loop unbalanced load filter according to an embodiment of the present inventive concept;

[0035] FIG. 9 is a voltage open loop bode plot of a transfer function of a current loop open loop system according to an embodiment of the present inventive concept;

[0036] FIG. 10 is a bode plot of a third harmonic feedback compensator according to an embodiment of the present inventive concept;

[0037] FIG. 11 is a current open loop bode plot of a transfer function of a current loop open loop system according to an embodiment of the present inventive concept;

[0038] FIG. 12 is a schematic diagram of an interleaved boost control subsystem according to an embodiment of the present inventive concept;

[0039] FIG. 13 is a simplified inter-leg current sharing open loop bode plot according to an embodiment of the present inventive concept;

[0040] FIG. 14 is a simplified alternating current boost open loop bode plot according to an embodiment of the present inventive concept;

[0041] FIG. 15 is a schematic diagram of a simulation result regarding simulation of a rectification circuit in a full load steady state according to an embodiment of the present inventive concept;

[0042] FIG. 16 is a schematic diagram of current harmonic data regarding simulation of a rectification circuit in a full load steady state according to an embodiment of the present inventive concept;

[0043] FIG. 17 is a schematic diagram of a simulation result regarding simulation of an interleaved boost full load steady state according to an embodiment of the present inventive concept;

[0044] FIG. 18 shows data regarding simulation of interleaved leg shared currents having a phase shift of 180 in an interleaved boost full load steady state according to an embodiment of the present inventive concept;

[0045] FIG. 19 is a schematic diagram of an emulation experiment result regarding a mains mode according to an embodiment of the present inventive concept;

[0046] FIG. 20 is a harmonic table corresponding to the emulation result of FIG. 19 according to an embodiment of the present inventive concept; and

[0047] FIG. 21 is a schematic diagram of an emulation experiment result regarding a battery mode according to an embodiment of the present inventive concept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0048] The present inventive concept is described in further detail below via specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain, rather than to limit, the present inventive concept.

[0049] As described in the background, in order to reduce hardware costs of UPS, a hardware topology scheme employing one-way rectification and an interleaved booster and used for a dual-use module, in which S-phase and T-phase rectifiers have a secondary use as a leg of a parallel direct current booster is provided. The dual-use module can be switched between a one-way rectification mode and an interleaved direct current boost mode. In order to better apply the hardware topology scheme to achieve a UPS system having high performance and low costs, the present inventive concept provides a novel stable control system for this novel hardware topology scheme, so as to solve problems faced thereby in an application process.

[0050] The present inventive concept provides for performing current equalization control on the current when the phases are interleaved so as to enable the two legs to operate without affecting the voltage. The present inventive concept further provides for seamless switching (i.e., reducing the transition time) between the mains mode and the battery mode when the S-phase and T-phase rectifiers are reused as the battery direct current boost leg (the leg B) so as implement full UPS functions. Thus, the present inventive concept provides stable control systems and methods for employing one-way rectification and an interleaved booster.

[0051] According to an embodiment of the present inventive concept, a stable control system for a three-phase rectifier circuit, configured to filter voltage harmonics and perform attenuation feedback compensation on current harmonics, and a stable control system for an interleaved direct current booster circuit, configured to equalize inter-leg currents so as to provide a battery having good dynamic effects and good current equalization performance are provided.

[0052] The present inventive concept is described below in detail with reference to the accompanying drawings and embodiments.

[0053] As previously described, rectification control schemes of three-phase rectifiers are known in the art, and in the rectification control schemes, a rectifier needs to acquire a current direct current value according to direct current bus voltage feedback, and then performs rectification control. However, in the prior art, for an unbalanced load, the direct current bus voltage includes first harmonics, i.e., power frequency ripples. If a particular compensator is absent, the first harmonics will be transmitted to the input current of the rectifier, causing the input current to be non-equalized. In order to solve this problem, a compensator is added to the rectifier control system in the present invention to perform optimization compensation on the direct current bus voltage so as to filter out power frequency ripples to acquire a current direct current effective value free of the power frequency ripples.

[0054] According to an embodiment of the present inventive concept, as shown in FIG. 7, a stable control system for a three-phase rectifier circuit includes: a rectification voltage loop controller D(s), for acquiring a rectification input direct current bus voltage set value V.sub.ref_bus and a direct current bus voltage feedback positive terminal value and negative terminal value V.sub.busp/n, and calculating a current effective reference value according to a difference between V.sub.ref_bus and V.sub.busp/n, wherein calculation of the current effective reference value is known to those skilled in the art, and details thereof will not be described; and a rectification voltage loop unbalanced load optimization compensator G.sub.opt(s), for calculating a rectification voltage loop unbalanced load optimization compensation parameter according to a preset transfer function and the current effective reference value, and performing feedback compensation on the current effective reference value on the basis of the rectification voltage loop unbalanced load optimization compensation parameter so as to acquire a current direct current effective value, wherein the current direct current effective value is acquired by filtering out voltage harmonics from the current effective reference value by means of the rectification voltage loop unbalanced load optimization compensation parameter. The technique of processing, on the basis of a transfer function of a certain controller, data input into the controller is known to those skilled in the art, and details thereof will not be described in the present invention. In subsequent embodiments relating to specific implementations of the transfer function of the controller, only the transfer function itself is described, and how the controller uses the transfer function to process the input data to acquire an output will not be described in detail.

[0055] According to an embodiment of the present invention, the transfer function of G.sub.opt(s) is

[00007] $G_{opt} (s) = \frac{s^{2} + 2_{i} s +_{o}^{2}}{s^{2} + 2_{i} K_{opt} s +_{o}^{2}},$ where .sub.i is an angular frequency deviation value (i.e., a deviation of an actually used frequency from a standard frequency) (which may be set to 1 hz*2), .sub.o is an angular frequency of power frequency ripples, e.g., 50 hz*2, and K.sub.opt is a compensation attenuation gain coefficient. As described in the background, when the hardware topology of the dual-use model operates in the mains mode, the current from the alternating current power grid is converted into the direct current. For an unbalanced load, the direct current bus voltage includes first harmonics, i.e., power frequency ripples. If a particular compensator is absent, the first harmonics will be transmitted to the input current of the rectifier, causing the input current to be non-equalized. In order to achieve current equalization, the rectification voltage loop unbalanced load optimization compensator is employed in the present inventive concept to perform optimization compensation on the voltage harmonics so as to achieve current equalization. When the load is a stable load, the current effective reference value does not include power frequency ripples, and after processing of G.sub.opt(s), a current direct current effective value consistent with the current effective reference value is acquired. When the load is an unbalanced load, the current effective reference value includes power frequency ripples, and the power frequency ripples are filtered out by means of G.sub.opt(s), so as to acquire a current direct current effective value free of the power frequency ripples.

[0056] According to an embodiment of the present inventive concept, the control period of the current loop is typically different from the control period of the voltage loop, and typically, the control period of the voltage loop is 5-10 times the control period of the current loop, so that in the discrete period, a filter G.sub.fil(z)=FIR(z) may be added for optimization, where FIR(z) is a finite impulse filter, and z is a discrete domain operator, and the rectification unbalanced load is fully optimized on the basis of the filter:

[00008] $G_{opt} (s) = G_{ubl} (s) G_{fil} (z)$ [0057] wherein G.sub.ubl(s) is a rectification voltage loop unbalanced load notch filter, and has functions similar to those of the rectification voltage loop unbalanced load optimization compensation controller without a filter added in the foregoing embodiment, and is used to acquire an optimization compensation parameter, and a transfer function thereof is

[00009] $G_{ubl} (s) = \frac{s^{2} +_{1} s +_{o}^{2}}{s^{2} +_{2} s +_{o}^{2}}$

[0058] .sub.1 being a zero point damping coefficient, .sub.2 being a pole damping coefficient, .sub.0 being an angular frequency of a compensation point, and s being a transfer function operator.

[0059] Referring to the bode plot of a transfer function of a rectification voltage loop unbalanced load filter shown in FIG. 8 and the voltage open loop bode plot of a transfer function of a current loop open loop system shown in FIG. 9, a loop cross-over frequency is 19.4 Hz, a phase margin Pm=45.4 deg, and a gain margin Gm=18.8 dB. It is typically required in the field of UPS that Gm>6 and Pm>30. Therefore, it can be seen that the design of the rectification voltage loop unbalanced load optimization compensation controller can meet performance requirements.

[0060] According to an embodiment of the present inventive concept, with continued reference to FIG. 7, the system further includes: a rectification current feedback compensator G.sub.atm(s), for acquiring a rectification input three-phase current feedback value i.sub.abc, calculating a feedback compensation parameter by means of a preset transfer function and according to i.sub.abc, and performing harmonic gain amplification on harmonics in i.sub.abc on the basis of the feedback compensation parameter to acquire a harmonic current value having undergone gain amplification, wherein the harmonic current value having undergone gain amplification is used for rectification input current feedback compensation control so as to attenuate harmonics in a rectification input current. Specifically, the harmonic current value having undergone gain amplification is subjected to subtraction with respect to a rectification current loop three-phase current set value i.sub.ref_abc including harmonics, that is, the harmonic current value having undergone gain amplification is subtracted from i.sub.ref_abc, so as to reduce the impact of harmonics. As mentioned for a three-phase inversion output load, an input current of the rectifier includes obvious third harmonics. Especially in the positive and negative independent dual alternating current rectification boost topology of the one-way rectifier, the third current harmonic component is even larger, thereby worsening total harmonic distortion (THDi) and resulting in overspecification. In order to solve this problem, the present inventive concept uses the rectification current feedback compensator to perform feedback compensation control on the rectification input current so as to attenuate harmonics in the rectification input current. According to an embodiment of the present inventive concept, the rectification current feedback compensator is:

[00010] $G_{atn} (s) = H_{1 th} (s) + .Math. H_{2 n + 1} (s)$ [0061] where H.sub.1th(s) is a rectification current first harmonic feedback compensator, and H.sub.2n+1(s) is a rectification current odd harmonic feedback compensator. In a preferred embodiment of the present invention, the rectification current feedback compensator employs the attenuation design of G.sub.atn_prj(s)=H.sub.1th(s)+H.sub.3th(s), wherein H.sub.3th(s) is a rectification current third harmonic feedback compensator. The function of the harmonic feedback compensator is to amplify a harmonic gain. For those skilled in the art, how to amplify a harmonic gain is a known technique, and details thereof will not be described.

[0062] Referring to the bode plot of a third harmonic feedback compensator shown in FIG. 10 and the current open loop bode plot of a transfer function of a current loop open loop system shown in FIG. 11, a loop cross-over frequency is 1.12e+03 Hz, a phase margin Pm=49.1 deg, and a gain margin Gm=8.33 dB. It is typically required in the field of UPS that Gm>6 and Pm>30. Therefore, it can be seen that the design of the rectification current feedback compensation controller can meet performance requirements.

[0063] According to an embodiment of the present inventive concept, with continued reference to FIG. 7, the system further includes: a rectification current loop controller D(s), for acquiring a rectification current loop three-phase current set value i.sub.ref_abc and an output of the rectification current feedback compensator such as G.sub.atn(s), and calculating a rectification current loop control parameter by means of a preset transfer function and according to a difference between i.sub.ref_abc and the output of G.sub.atn(s), so as to acquire a rectification current loop control output duty cycle d.sub.iloop on the basis of the rectification current loop control parameter, wherein i.sub.ref_abc is acquired by performing multiplication of the current direct current effective value output by the rectification voltage loop unbalanced load optimization compensator G.sub.opt(s) and a rectification current loop weight sine reference function (V.sub.ac(t): V.sub.sin(t)); and the rectification current loop control output duty cycle d.sub.iloop is used to calculate the rectification input three-phase current feedback value and a rectification bus voltage feedback positive terminal value and negative terminal value. A rectification input three-phase current duty cycle d.sub.abc is acquired on the basis of a difference between a rectification voltage feedforward duty cycle value d.sub.vff and d.sub.iloop. The rectification input three-phase current duty cycle d.sub.abc is used to acquire the rectification input three-phase current feedback value i.sub.abc via a current loop controlled object transfer function G.sub.id(s), and d.sub.abc is used to acquire the rectification bus voltage feedback positive terminal value and negative terminal value v.sub.busp/n via the current loop controlled object transfer function G.sub.id(s) and a voltage loop controlled object transfer function G.sub.vi_Sum(s). The current loop controlled object transfer function G.sub.id(s) and the voltage loop controlled object transfer function G.sub.vi_Sum(s) are techniques known by those skilled in the art, and details thereof will not be described in the present invention.

[0064] As described in the foregoing embodiment, after the current effective reference value is processed using the optimization compensation parameter of G.sub.opt(s), the impact of power frequency ripples is filtered out, so as to acquire the current direct current effective value. The current direct current effective value is multiplied by (V.sub.ac(t): V.sub.sin(t)) to acquire the rectification current loop three-phase current set value i.sub.ref_abc. For an unbalanced load, i.sub.ref_abc includes a harmonic current. The rectification current feedback compensator G.sub.atn(s) performs gain amplification on harmonics on the basis of the rectification input three-phase current feedback value i.sub.abc (in the case of a stable load, harmonics are not present, that is, the harmonic current is 0, so that gain amplification is equivalent to amplification performed on 0; in the case of an unstable load, harmonics are present, and after a harmonic gain is amplified and the harmonic current having undergone gain amplification is subtracted from i.sub.ref_abc, harmonics in i.sub.ref_abc can be reduced), and then the impact of the harmonics can be reduced after the harmonics having undergone harmonic feedback compensation gain amplification is subtracted from the rectification current loop three-phase current set value i.sub.ref_abc. After the subtraction, the rectification current loop control output duty cycle d.sub.iloop is acquired via processing performed by means of D.sub.i(s). Then, a rectification input three-phase current duty cycle d.sub.abc is acquired on the basis of a difference between d.sub.vff and d.sub.iloop, the rectification input three-phase current feedback value i.sub.abc is acquired according to d.sub.abc via the current loop controlled object transfer function Gd(s), and the rectification bus voltage feedback positive terminal value and negative terminal value v.sub.busp/n is acquired by using d.sub.abc in the current loop controlled object transfer function G.sub.id(s) and the voltage loop controlled object transfer function G.sub.vi_sum(s). This process is repeated until the harmonics are filtered out. Hence, the harmonic gain amplification is performed continuously on harmonics in the current according to the rectification input three-phase current feedback value so as to use the same for feedback compensation, and the harmonic gain is amplified continuously, and is subtracted from i.sub.ref_abc, so as to continuously reduce harmonics in i.sub.ref_abc.

[0065] It should be noted that, in order to achieve a sufficient phase margin and gain margin, D.sub.i(s) is herein selected to be PI+Lead (PI plus a lead compensation loop) to ensure that the control system has a small net difference and a sufficient phase margin. According to an embodiment of the present invention,

[00011] $D_{i} (s) = K_{p} (1 + \frac{1}{T_{i} s}) (\frac{{aT}_{lead} s + 1}{T_{lead} s + 1}),$

where K.sub.p is a proportion coefficient, T.sub.i is an integration constant,

[00012] $\frac{{aT}_{lead} s + 1}{T_{lead} s + 1}$

is lead compensation, a is a coefficient for controlling a lead phase, and T.sub.lead is approximately a lead bandwidth time constant. Meanwhile, a load change is addressed via a magnetic variable inductor and an inductance gain compensator in the hardware topology.

[0066] According to an embodiment of the present inventive concept, as shown in FIG. 12, a stable control system for controlling an interleaved direct current boost circuit of the present inventive concept includes: an inductive current difference loop controller D.sub.i_dff(s), for respectively acquiring inductive currents i.sub.Lb of the first leg i.sub.La and the second leg of the interleaved direct current booster, calculating an inductive current difference loop control parameter by means of a preset transfer function and according to a difference between the inductive current of the direct current boost first leg and the inductive current of the direct current boost second leg, and calculating a difference loop duty cycle value d according to the inductive current difference loop control parameter and the inductive currents of the first leg and the second leg of the direct current booster so as to use the same for current equalization control of a current between battery legs, wherein the difference loop duty cycle value d is used to calculate a current difference i between the first leg and the second leg of the direct current booster, so as to determine, according to the current difference, whether current equalization is achieved between the first leg and the second leg of the direct current booster. When current equalization is achieved between the two legs, i=0. When current equalization is not achieved between the two legs, i is not equal to 0. Specifically, d is used to acquire the current difference i between the two legs of the battery via a direct current boost inter-leg current difference loop controlled object function G.sub.id_diff(s). Those skilled in the art would know that G.sub.id_diff(s) is a common transfer function for a circuit control system, so that details thereof will not be described. The present inventive concept employs the inductive current difference loop controller D.sub.i_dff(s) to make the used boost loop control system compatible with the interleaved boost control system, and a current sharing loop is added to the duty cycle portion so as to achieve inter-leg current equalization.

[0067] Referring to the simplified inter-leg current sharing open loop bode plot shown in FIG. 13, a loop cross-over frequency is 1.22e+03 Hz, a phase margin Pm=67.6 deg, and a gain margin Gm=17 dB. It is typically required in the field of UPS that Gm>6 and Pm>30. Therefore, it can be seen that the design of the inductive current difference loop controller can meet performance requirements. Regarding on/off of a multi-leg topology, only on or off of D.sub.i_dff(s) needs to be configured, so that a multi-leg hardware topology including two or more legs, such as an n-leg topology (n>2), an ish-loop topology, etc., can be more easily achieved. In the n-leg topology, a difference loop duty cycle of an n-th leg is d.sub.nth=(i.sub.Lavgi.sub.Lnth)D.sub.i_dff(s), wherein i.sub.Lavg is an inductive current average value of the n-th leg in the direct current boost, and i.sub.Lnth is an inductive current value of the n-th leg in the direct current boost.

[0068] According to an embodiment of the present inventive concept, the inductive current difference loop controller is a proportional hysteresis controller, and a transfer function thereof is:

[00013] $D_{i_{dff}} (s) = K_{dff} \frac{s + a}{s + b},$ where K.sub.dff is a proportional feedforward gain, a is a hysteresis loop zero point, b is a hysteresis loop pole, and s is a control function operator.

[0069] According to an embodiment of the present invention, with continued reference to FIG. 12, the system further includes: a direct current boost bus transient voltage controller D.sub.v(s), for acquiring a direct current boost bus voltage set value v.sub.ref_bus, a direct current boost bus average voltage error compensation value V.sub.avg, and a direct current boost bus voltage feedback positive terminal value and negative terminal value v.sub.busp/n, calculating a direct current boost bus transient voltage control parameter by means of a preset transfer function and according to v.sub.ref_bus+V.sub.avgv.sub.busp/n, and calculating a direct current boost voltage duty cycle value d.sub.v according to v.sub.ref_bus+V.sub.avgv.sub.bus/n and the direct current boost bus transient voltage control parameter; and a direct current boost leg duty cycle module d.sub.a/b, for respectively acquiring a direct current boost first leg duty cycle value d.sub.a and a direct current boost second leg duty cycle value d.sub.b according to d.sub.v output by the direct current boost bus transient voltage controller and d output by the inductive current difference loop controller and according to a preset duty cycle calculation rule, wherein d.sub.a and d.sub.b are used to calculate a direct current boost bus feedback positive terminal value and negative terminal value. Specifically, d.sub.a and d.sub.b are used to acquire the direct current boost bus feedback positive terminal value and negative terminal value v.sub.bus/n by means of a direct current boost voltage loop controlled object transfer function G.sub.vd(s). Those skilled in the art would know that G.sub.vd(s) is a common transfer function for a circuit control system, so that details thereof will not be described in the present invention.

[0070] According to an embodiment of the present inventive concept, a preset duty cycle calculation rule of the direct current boost leg duty cycle module d.sub.a/b is as follows:

[00014] $d_{a / b} = f (d_{v}, d)$ $d_{a} = d_{v} - d$ $d_{b} = d_{v} + d$

[0071] As described in the foregoing embodiment, the inductive current difference loop controller D.sub.idff(s) acquires the difference loop duty cycle according to the current between the two legs. The difference loop duty cycle indicates the status of current non-equalization between the two legs. If the current between the two legs is equalized, then i.sub.La=i.sub.Lb, d=0, i=0, and d.sub.a=d.sub.b. If the current between the two legs is not equalized, i.sub.La is not equal to i.sub.Lb, d is greater than 0 or less than 0, and i is also greater than 0 or less than 0. If d is greater than 0, i is also greater than 0, indicating that i.sub.La is greater than i.sub.Lb. In order to achieve current equalization, the duty cycle of the first leg needs to be decreased, and the duty cycle of the second leg needs to be increased. The duty cycle of the first leg can be decreased by d.sub.a=d.sub.vd, and the duty cycle of the second leg can to be increased by d.sub.b=d.sub.v+d, and vice versa. Thus, current equalization between two legs in an interleaved direct current boost circuit can be achieved on the basis of the inductive current difference loop controller D.sub.i_dff(s) and the direct current boost leg duty cycle module d.sub.a/b of the present invention.

[0072] When a plurality of legs are present, the direct current boost voltage duty cycle d.sub.nth of the nth leg is: d.sub.nth=d.sub.v+d.sub.nth.

[0073] Referring to the simplified alternating current boost open loop bode plot shown in FIG. 14, a loop cross-over frequency is 51.2 Hz, a phase margin Pm=76.76 deg, and a gain margin Gm=32.7 dB. It is typically required in the field of UPS that Gm>6 and Pm>30. Therefore, it can be seen that the design of the direct current boost leg duty cycle module can meet performance requirements. On the basis of the design, in a topology employing a dual-use leg module, only a shared loop of operation of two legs needs to be configured, and the boosted voltage loop is not affected, thereby achieving high compatibility.

[0074] On the basis of the above control system, seamless switching between one-way rectification and an interleaved booster by means of a dual-use leg module can be achieved. As shown in FIG. 4(a), in the mains mode (that is, mains power is supplied normally), the R-phase, S-phase, and T-phase rectifiers are in operation. When the mains power is lost, it is necessary to switch from the mains mode to the battery mode to use the battery to supply power. In this case, the boost mode of the battery leg A is enabled so as to ensure that one leg supplies power during switching, and power supply of the UPS is not interrupted. The dual-use module is configured to switch from the ST phase rectifier mode to the battery boost leg B mode so as to enter the battery mode. Before mode switching is completed, the duration of operation of the battery leg A is at the scale of ms. Then, the leg leg A and the leg B are both in operation, entering the battery boost mode to perform battery dual boost discharging. Conversely, as shown in FIG. 4(b), in the battery mode, both of the battery boost leg leg A and leg B are in operation, and when the mains power resumes, it is necessary to switch from the battery mode to the mains mode to resume power supplied by the mains power. In this case, the boost leg A is configured to continue to operate, and the dual-use module is configured to change from the boost leg B to the S-phase and T-phase rectifiers. The continuous operation of the battery leg A ensures that one leg supplies power during switching, and before the mode switching is completed, the duration of operation of the battery leg A is at the scale of ms. Then, the R-phase, S-phase, and T-phase rectifiers are enabled, thereby entering the mains mode, and achieving switching from battery direct current power supply to power grid alternating current power supply. Then, the battery leg A switches to a buck mode to charge the battery. It can be seen that in the dual-use module, the S-phase and T-phase rectifiers have a secondary use as the battery direct current boost leg B. During line-battery mode switching, there is only a short duration in which only the battery leg A operates to supply power to the load, which serves as an excess of the S-phase and T-phase rectifiers and the battery direct current boost leg B. In addition, rectification input is silicon controlled, thereby shortening a switching time and achieving seamless switching.

[0075] In order to better illustrate the effect of the present inventive concept, the present inventive concept is described below with reference to simulation and emulation experiment data.

[0076] Referring to FIG. 15 and FIG. 16, FIG. 15 shows, in sequence from top to bottom, dynamic changes of a rectification bus voltage feedback positive terminal value and negative terminal value, a rectification three-phase voltage input value, a rectification input three-phase current feedback value, and a sorted input three-phase current value regarding simulation of a full load steady state, and FIG. 16 shows current harmonic data regarding simulation of rectification in a full load steady state. The current total harmonic distortion THDi=1.5%, meeting dynamic performance requirements on products.

[0077] Referring to FIG. 17 and FIG. 18, FIG. 17 shows, in sequence from top to bottom, a direct current bus voltage feedback positive terminal value and negative terminal value, a current positive value of direct current boost legs A and B, a current negative value of direct current boost legs A and B, a battery voltage positive terminal value and negative terminal value, and a shared current loop current value regarding simulation of a full load steady state, and FIG. 18 shows data regarding simulation of interleaved leg shared currents having a phase shift of 180, which meets stability requirements on products.

[0078] Reference is made to FIG. 19, FIG. 20, and FIG. 21. FIG. 19 shows an emulation experiment result regarding switching from the mains mode to the battery mode in a full load steady state. It can be seen that the mains power is lost, the rectification mode is disabled, and the boost mode is enabled (the direct current input I.sub.in decreases to 0, and the battery current I.sub.bat increases). FIG. 20 is a harmonic table of rectification, and the current total harmonic distortion THDi=2.5%. FIG. 21 shows switching from the battery mode to the mains mode in a full load steady state. It can be seen that the mains power resumes, the rectification mode is on, the boost leg leg A continues to operate, and the battery current I.sub.bat drops to 0. It can be seen that seamless switching between the mains mode and the battery mode can be achieved on the basis of the novel control system.

[0079] It can be seen from the above embodiments, simulation, and emulation that the present inventive concept provides optimized rectification control on the basis of the novel rectification topology, thereby achieving high stability and low THDi and supporting an unbalanced load. In addition, on the basis of the novel interleaved boost topology, provided is a novel interleaved boost control system, employing interleaved boost and compatible with a boost two-volt loop control system, and employing a novel boost leg current equalization loop, thereby achieving a good dynamic response and good current equalization performance. Rectification_ST has a secondary use as the battery boost leg_leg B, and a novel switching logic is achieved on the basis of the novel control system, thereby allowing for use in the mains and battery modes, and achieving an objective of using hardware to construct a novel UPS system having high performance and low costs.

[0080] It should be noted that although the steps are described above in a specific order, it is not indicated that the steps have to be performed in the specific order described above. In fact, some of these steps may be performed concurrently or even in a different order, so long as the desired function can be implemented.

[0081] The present inventive concept may be a system, a method, and a computer program product. The computer program product may include a computer readable storage medium having computer readable program instructions carried thereon for causing a processor to implement various aspects of the present invention.

[0082] The computer readable storage medium may be a tangible device that holds and stores instructions used by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples of the computer readable storage medium (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read only memory (ROM), an erasable programmable read only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical coding device, such as a punch card with instructions stored thereon or a structure of bumps within recessions, and any suitable combination thereof.

[0083] The embodiments of the present inventive concept have been described above. The foregoing description is illustrative rather than limiting, and is not limited to the disclosed embodiments. Many modifications and variations would be apparent to those ordinarily skilled in the art without departing from the scope and spirit of the illustrated embodiments. The selection of terms used herein aims to best explain the principles or practical applications of the embodiments, or the technical improvements thereof to the market, or to enable other ordinarily skilled in the art to understand the embodiments disclosed herein.

STABLE CONTROL SYSTEMS EMPLOYING ONE-WAY RECTIFICATION AND INTERLEAVED BOOSTER

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H02M1/0009

ELECTRICITY

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H02M7/487

ELECTRICITY

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H02M7/2173

ELECTRICITY

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H02J9/061

ELECTRICITY

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H02J7/50

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H02M7/219

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H02M1/10

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H02J2207/20

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H02M7/217

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H02M1/00

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Abstract

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