SEMICONDUCTOR TEST DEVICE AND MANUFACTURING METHOD THEREOF

Abstract

The present invention relates to a semiconductor test device and a manufacturing method thereof. The semiconductor test device according to an embodiment of the present invention is a semiconductor test device which is interposed between semiconductor memories, or between a semiconductor memory and an interposer, to perform a test of an electrical connection, and may include: a membrane portion comprising a plurality of aperture patterns in a thickness direction; and a holder portion having a hollow region and connected to an edge of the membrane portion, wherein neighboring aperture patterns are insulated from each other and an electrical connection path is formed from a top to a bottom of each aperture pattern.

Claims

1. A semiconductor test device, which is interposed between a semiconductor memory and an interposer, to perform a test of an electrical connection, comprising: a membrane portion comprising a plurality of aperture patterns in a thickness direction; and a holder portion having a hollow region and connected to an edge of the membrane portion, wherein the membrane portion comprises a metal thin film portion having the plurality of aperture patterns and an insulating layer portion with an insulating material coated on a surface of the metal thin film portion, wherein a conductive thin film layer is formed on side surfaces of each of the aperture patterns to provide an electrical connection path from a top to a bottom of each of the aperture patterns.

2. The semiconductor test device of claim 1, wherein the conductive thin film layer comprises at least one of Cu, Ag, Au, Pt or Sn.

3. The semiconductor test device of claim 1, wherein the conductive thin film layer is further formed in a horizontal direction at a top of the side surfaces of each of the aperture patterns, or is further formed in the horizontal direction at a bottom of the side surfaces of each of the aperture patterns.

4. The semiconductor test device of claim 1, wherein the hollow region of the holder portion serves as a space for accommodating the semiconductor memory and each of the aperture patterns corresponds to each of a plurality of micro bumps formed on a lower portion of the semiconductor memory.

5. The semiconductor test device of claim 4, wherein each of the aperture patterns has a shape with a width decreasing from the top to the bottom thereof, or a shape with the narrowest width at a center thereof, and a plurality of micro bumps formed on a lower portion of the semiconductor memory are guided into the aperture patterns at least along side surfaces of the aperture patterns and make contact with the conductive thin film layer.

6. A semiconductor test device, which is interposed between a semiconductor memory and an interposer, to perform a test of an electrical connection, comprising: a membrane portion comprising a plurality of aperture patterns in a thickness direction; and a holder portion having a hollow region and connected to an edge of the membrane portion, wherein a conductive thin film layer is formed on side surfaces of each of the aperture patterns, wherein an area of the semiconductor memory corresponds to a size of one cell, a size of a plurality of cells, or a size of a silicon wafer, and a horizontal area of the hollow region of the holder portion is larger than that of the semiconductor memory.

7. The semiconductor test device of claim 6, wherein the metal thin film portion is made of at least one of Invar, Super Invar, nickel-iron alloy, nickel-cobalt alloy or nickel-iron-cobalt alloy.

8. The semiconductor test device of claim 1, wherein a width of the aperture pattern is 5 m to 100 m.

9. A semiconductor test device, which is interposed between a semiconductor memory and an interposer, to perform a test of an electrical connection, comprising: a membrane portion comprising a plurality of aperture patterns in a thickness direction; and a holder portion having a hollow region and connected to an edge of the membrane portion, wherein a conductive thin film layer is formed on side surfaces of each of the aperture patterns, and wherein the conductive thin film layer further comprises a conductive cantilever portion that protrudes at least inward from the aperture pattern.

10. The semiconductor test device of claim 9, wherein the conductive cantilever portion is bent upward or downward by a magnetic force applied from an outside, allowing it to make contact with a plurality of micro bumps formed on a lower portion of the semiconductor memory.

11. The semiconductor test device of claim 1, wherein the membrane portion comprises the metal thin film portion having a first thickness and the insulating layer portion with an insulating material coated on the surface of the metal thin film portion, the holder portion has a second thickness thicker than the first thickness and is integrally connected to the edge of the membrane portion, and the metal thin film portion and the holder portion are made of a same metal material.

12. The semiconductor test device of claim 11, wherein a ground electrode is connected to the metal film portion or the holder portion.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG. 1 illustrates a schematic diagram showing a semiconductor chip structure according to an embodiment.

[0036] FIG. 2 illustrates a schematic cross-sectional view showing a semiconductor chip structure according to an embodiment.

[0037] FIG. 3 illustrates a schematic diagram showing a semiconductor test device according to a first embodiment of the present invention.

[0038] FIGS. 4 to 5 illustrate schematic diagrams showing how to test an electrical connection between a stacked semiconductor memory and an interposer by applying a semiconductor test device according to an embodiment of the present invention.

[0039] FIGS. 6 to 7 illustrate schematic diagrams showing a manufacturing process of a semiconductor test device according to an embodiment of the present invention.

[0040] FIGS. 8 to 9 illustrate schematic diagrams showing a manufacturing process of a semiconductor test device according to another embodiment of the present invention.

[0041] FIG. 10 illustrates a schematic diagram showing a semiconductor test device according to a second embodiment of the present invention.

[0042] FIGS. 11 to 12 illustrate schematic diagrams showing a manufacturing process of a semiconductor test device according to still another embodiment of the present invention.

[0043] FIG. 13 illustrates a schematic diagram showing a semiconductor test device according to a third embodiment of the present invention.

[0044] FIGS. 14 to 15 illustrate schematic diagrams showing a manufacturing process of the semiconductor test device according to the third embodiment of the present invention.

[0045] FIGS. 16 to 17 illustrate schematic diagrams showing the forms of semiconductor test devices according to fourth to sixth embodiments of the present invention.

[0046] FIG. 18 illustrates a schematic diagram showing a semiconductor test device according to a seventh embodiment of the present invention.

[0047] FIG. 19 illustrates a schematic diagram showing a semiconductor test device according to an eighth embodiment of the present invention.

[0048] FIGS. 20 and 21 illustrate schematic side cross-sectional views showing the forms of aperture patterns and conductive thin film layers according to various embodiments of the present invention.

[0049] FIG. 22 illustrates a schematic plan view showing contact forms between aperture patterns and micro bumps according to various embodiments of the present invention.

[0050] FIG. 23 illustrates schematic diagrams showing a manufacturing process of the semiconductor test device according to the seventh embodiment of the present invention.

[0051] FIG. 24 illustrates (a) a schematic cross-sectional side view and (b) a schematic plan view showing a conductive cantilever portion protruding inward from an aperture pattern according to an embodiment of the present invention.

[0052] FIG. 25 illustrates a schematic diagram showing a form of controlling a conductive cantilever portion by applying an external magnetic force, according to an embodiment of the present invention.

[0053] FIGS. 26 to 33 illustrate schematic diagrams showing a manufacturing process of a semiconductor test device according to the eighth embodiment of the present invention.

[0054] FIGS. 34 to 37 illustrate schematic diagrams showing a manufacturing process of a semiconductor test device according to a ninth embodiment of the present invention.

[0055] FIG. 38 is a cross-sectional microscopic photograph of a metal film formed by electroforming according to a comparative example.

[0056] FIG. 39 is a cross-sectional microscopic photograph of a metal thin film portion formed by electroforming according to an embodiment of the present invention.

[0057] FIG. 40 illustrates a schematic side cross-sectional view showing a metal film formed by electroforming according to the comparative example.

[0058] FIG. 41 illustrates schematic side cross-sectional views showing a metal thin film portion formed by electroforming according to an embodiment of the present invention.

[0059] FIG. 42 is a cross-sectional microscopic photograph of a metal thin film portion formed on a support by electroforming according to an embodiment of the present invention.

[0060] FIG. 43 is a planar microscopic photograph of the metal thin film portion after a planarization process according to an embodiment of the present invention.

[0061] FIGS. 44 and 45 illustrate the line data and composition in the depth direction of the metal thin film portion formed on a support by electroforming, according to an embodiment of the present invention.

[0062] FIG. 46 is an enlarged schematic side cross-sectional view of area I in (b) of FIG. 41, showing the crystal shape of the metal thin film portion before and after the planarization process according to an embodiment of the present invention.

[0063] FIG. 47 is a planar microscopic photograph of the metal thin film portion after a planarization process according to an embodiment of the present invention.

[0064] Throughout the drawings and the detailed description, unless otherwise described, the same drawing reference numerals will be understood to refer to the same elements, features, and structures. The relative size and depiction of these elements may be exaggerated for clarity, illustration, and convenience.

DETAILED DESCRIPTION

[0065] The following detailed descriptions of the invention will be made with reference to the accompanying drawings illustrating specific embodiments of the invention by way of example. These embodiments will be described in detail such that the invention can be carried out by one of ordinary skill in the art. It should be understood that various embodiments of the invention are different, but are not necessarily mutually exclusive. For example, a specific shape, structure, and characteristic of an embodiment described herein may be implemented in another embodiment without departing from the scope of the invention. In addition, it should be understood that a position or placement of each component in each disclosed embodiment may be changed without departing from the scope of the invention. Accordingly, there is no intent to limit the invention to the following detailed descriptions. The scope of the invention is defined by the appended claims and encompasses all equivalents that fall within the scope of the appended claims. In the drawings, like reference numerals denote like functions, and the dimensions such as lengths, areas, and thicknesses of elements may be exaggerated for clarity.

[0066] Hereinafter, to allow one of ordinary skill in the art to easily carry out the invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0067] FIG. 1 illustrates a schematic diagram showing a semiconductor chip structure according to an embodiment. FIG. 2 illustrates a schematic cross-sectional view showing a semiconductor chip structure according to an embodiment.

[0068] Referring to FIGS. 1 and 2, a semiconductor device 10 according to an embodiment may include a base substrate 11, a package substrate 12, an interposer 13, a first semiconductor package 14, and a second semiconductor package 15. The semiconductor device 10 may be implemented as a system-in-package in which heterogeneous semiconductor chips are assembled into a single package. Each of the semiconductor chips assembled into a single package in the semiconductor device 10 may correspond to a semiconductor package. For example, the semiconductor device 10 may be provided as a semiconductor package in which AI semiconductor chips are combined.

[0069] The base substrate 11 and the package substrate 12 may be provided as printed circuit boards (PCBs) with circuit patterns. For example, the base substrate 11 may be provided as the base of a graphics card. The base substrate 11 may be equipped with a PCI Express, a display connector, and the like. Bumps B1 may be interposed between the base substrate 11 and the package substrate 12 to transmit electrical signals.

[0070] The interposer 13 may be provided to accommodate a plurality of semiconductor packages 14 and 15. For example, a plurality of upper pads (not shown) may be formed on the silicon interposer 13, and the first semiconductor package 14 and the second semiconductor package 15 may be electrically connected through these upper pads. The first semiconductor package 14 and the second semiconductor package 15 may be stacked on the package substrate 12 via the interposer 13.

[0071] The first semiconductor package 14 may be provided as a processor. The first semiconductor package 14 may be stacked on the interposer 13. For example, the first semiconductor package 14, which is a graphics processing unit (GPU), may be electrically connected to the interposer 13 through the coupling of the micro bumps MB1 of the first semiconductor package 14 and the upper pads (not shown) of the interposer 13.

[0072] The second semiconductor package 15 may be provided as a memory package. For example, the second semiconductor package 15 may be provided as a high-bandwidth memory (HBM), which is a stacked semiconductor memory. The second semiconductor package 15 may include multiple stacked memory dies 16 and a controller die 17. The multiple memory dies 16 and the controller die 17 may transmit electrical signals through through-silicon vias (TSV) EL. The second semiconductor package 15 may be coupled to an upper pad (not shown) of the interposer 13 via micro bumps MB2 on a lower portion of the second semiconductor package 15, and the second semiconductor package 15 may be electrically connected to the interposer 13.

[0073] A stacked semiconductor memory (HBM) may be manufactured and tested in the form of stacked wafers, then diced into individual dies or individual semiconductor chips. Traditionally, a test is performed on the wafer in its stacked form before dicing. After dicing, it becomes difficult to make contact with individual dies or semiconductor chips using probes. Conventional probes are equipped with pins approximately 100 m in size. However, the lower micro bumps of increasingly integrated stacked semiconductor memory (HBM) have a size and pitch ranging from a few to several tens of micrometers, making it difficult to make contact with conventional probes. Components that are difficult to make contact with probes may undergo testing after being assembled into a single package, which may lead to a problem where even properly functioning components must be discarded due to a few defective components.

[0074] In addition, in the case of micro bumps MB2 located on the lower portion of individual stacked semiconductor memory, their small size and susceptibility to deformation under pressure may be problematic. When a stacked semiconductor memory is individually tested, some micro bumps may be damaged, deformed, or misaligned during the process of pressing the stacked semiconductor memory for testing, leading to product defects. Therefore, there is a need for a semiconductor test device that can prevent damage to micro bumps.

[0075] Meanwhile, in addition to individual stacked semiconductor memory, there is also a possibility that some micro bumps may be damaged when testing is performed on wafers in a stacked state. Therefore, there is a need for a semiconductor test device that can perform a test by contacting the micro bumps in a way that prevents damage to them while ensuring accurate and precise alignment with the micro bumps.

[0076] The present invention is characterized by providing a semiconductor test device that can prevent damage to micro bumps and perform a test by contacting the micro bumps, and a manufacturing method thereof.

[0077] FIG. 3 illustrates a schematic diagram showing a semiconductor test device according to a first embodiment of the present invention. FIGS. 4 to 5 illustrate schematic diagrams showing how to test an electrical connection between a stacked semiconductor memory and an interposer by applying a semiconductor test device according to an embodiment of the present invention.

[0078] Referring to FIGS. 3 to 5, a semiconductor test device 100 (100-1) according to an embodiment of the present invention may be interposed between a stacked semiconductor memory 15 and an interposer 13 and be used to perform a test of an electrical connection. Hereinafter, the above-mentioned second semiconductor package 15 will be described under the assumption that it is a stacked semiconductor memory (HBM). Meanwhile, in FIGS. 3 to 5, three electrical path portions 130 are shown for the sake of convenience in explanation, but it should be noted that the electrical path portions 130 may be formed to correspond to the number of lower micro bumps MB (MB2) of the stacked semiconductor memory.

[0079] Meanwhile, in the present invention, the semiconductor test device 100 is illustrated as being used between the stacked semiconductor memory 15 and the interposer 13 for convenience of explanation, but it is not necessarily limited to HBM, and may also be applied to other semiconductor memories, such as DRAM, if the semiconductor memory requires testing of electrical connection. Additionally, the semiconductor test device 100 may be interposed between the semiconductor memory and the interposer 13 or between semiconductor memories to test the electrical connection. Furthermore, the interposer 13 may be understood as a concept that includes a support substrate arranged to face the semiconductor memory and establish electrical connection therewith.

[0080] The semiconductor test device 100 (100-1) according to the first embodiment may include a membrane portion 110 (110-1) and a holder portion 150. The membrane portion 110 may include a plurality of aperture patterns P, and an electrical connection path may be provided from the top to the bottom of each aperture pattern P. This electrical connection path may be provided through an electrical path portion 130 that includes a conductive material.

[0081] According to an embodiment, the membrane portion 110 may be made of an insulating material. The aperture patterns P formed on the membrane portion 110 may be in contact, in one-to-one correspondence, with the micro bumps MB (MB2) on the lower portion of the stacked semiconductor memory 15. Therefore, the membrane portion 110 should be able to accommodate the formation of a plurality of aperture patterns P at a level of several to several tens of micrometers. Additionally, since the temperature may rise due to electrical contact during testing, the membrane portion 110 may use a material with low thermal expansion and low thermal contraction due to temperature changes, that is, a material with a low coefficient of thermal expansion (CTE). Moreover, the membrane portion 110 may be made of a material that is durable, resistant to deformation in the X and Y directions, and flexible to reduce the risk of damaging the micro bumps MB (MB2). Considering these factors, the membrane portion 110 may use an insulating material such as polyimide, rubber, resin, Teflon, polymer, curable photoresist, inorganic insulator, or organic insulator.

[0082] The membrane portion 110 may have a plurality of aperture patterns P formed along the thickness direction. The plurality of aperture patterns P may be formed at regular pitches along the horizontal direction (XY plane direction). For example, the pitch between the aperture patterns P may range from several tens of micrometers, for example, approximately 10 to 150 m, and the width W1 of the aperture pattern P may be less than this, and may be approximately 5 to 100 m. Approximately tens of thousands of micro bumps MB2 are arranged on the lower portion of one stacked semiconductor memory 15, and the aperture patterns P may be formed to correspond to these micro bumps MB2. The area where approximately tens of thousands of aperture patterns P are clustered along the XY plane direction is referred to as a cell portion C. To form such aperture patterns P of a fine width W1 and at a fine pitch, the overall thickness of the membrane portion 110 must also be thin. For example, the membrane portion 110 may be provided in a thin film form with a thickness T1 of approximately 5 to 50 m.

[0083] The holder portion 150 may be connected to the membrane portion 110 to securely support the membrane portion 110. The membrane portion 110 and the holder portion 150 may be connected to each other using adhesive means or through welding or the like. The holder portion 150 may have a frame-like shape with a hollow region R inside. The hollow region R may serve as a space to accommodate the stacked semiconductor memory 15 to be tested. Accordingly, the hollow region R has preferably a rectangular shape corresponding to the shape of the stacked semiconductor memory 15, but it is not limited thereto. For example, the size (horizontal area) of the hollow region R may correspond to the size of the stacked semiconductor memory 15, which is several millimeters to several tens of millimeters in width and height. In another example, the size of the hollow region R may correspond to the size of a stacked semiconductor memory including a plurality of cells/a plurality of dies, or the size of a silicon wafer, and it may be provided in a size larger than that. The area of the cell portion C may also correspond to the area of the aforementioned hollow region R.

[0084] The holder portion 150 may be made of a material with a low CTE to prevent thermal deformation. The holder portion 150 may use a material such as Invar, Super Invar, nickel-iron alloy, nickel-cobalt alloy, nickel-iron-cobalt alloy, quartz, or glass.

[0085] The membrane portion 110 may provide an electrical connection path from the top to the bottom of each aperture pattern P, and this electrical connection path may be formed through the electrical path portion 130 that includes a conductive material.

[0086] For example, the electrical path portion 130 may include a conductive material such as conductive rubber, metal powder composite, conductive metal, graphene, carbon nanotubes (CNT), quantum dot, or multilayer ceramic capacitor (MLCC).

[0087] The electrical path portion 130 may be filled in the aperture pattern P. To ensure smooth contact with the micro bump MB2 of the stacked semiconductor memory 15 and to prevent excessive stress on the micro bump MB2, the path portion 130 may include an elastic matrix made of an elastic material. The elastic matrix may be made of a material such as polyimide, rubber, resin, or polymer.

[0088] Additionally, the electrical path portion 130 must include a conductive material to provide an electrical connection path while maintaining elasticity. For example, the electrical path portion 130 may include a plurality of conductive particles, a plurality of conductive rods, a plurality of conductive wires, a plurality of conductive balls, or a plurality of conductive flakes dispersed within the elastic matrix. These particles, rods, wires, balls, or flakes may have a size on the scale of nanometers to micrometers, and they may be interconnected within the elastic matrix to form an electrical connection path from the top to the bottom of the electrical path portion 130.

[0089] Since each of the electrical path portions 130 is filled within its respective aperture pattern P so that they are spaced apart from each other, the electrical path portions 130 do not short-circuit each other. The electrical path portions 130 may be filled within the aperture patterns P to the same thickness as the membrane portion 110. Alternatively, the electrical path portion 130 may be filled thicker than the membrane portion 110, so that they protrude beyond the top/bottom surfaces of the membrane portion 110. In this case, if the electrical path portions 130 protrude excessively beyond the top/bottom surfaces of the membrane portion 110, the contact stability may decrease during the process of pressing against the micro bumps MB2. Therefore, the thickness of the electrical path portions 130 is preferably formed to be no more than 150% of the thickness T1 of the membrane portion 110. This allows the micro bumps MB2 on the lower portion of the stacked semiconductor memory 15 to make stable contact only with the electrical path portions 130.

[0090] As shown in (a) of FIG. 4, the stacked semiconductor memory 15 that needs to be tested may be provided. The stacked semiconductor memory (15) may have a plurality of micro bumps MB (MB2) formed on its lower portion. Subsequently, the stacked semiconductor memory 15 may be accommodated in the hollow region R provided by the holder portion 150 of the semiconductor test device 100 (100-1). The micro bumps MB may be respectively in contact with the electrical path portions 130 of the semiconductor testing device 100.

[0091] Next, as shown in (b) of FIG. 4, a test interposer 13 may be prepared. The test interposer 13 may have connection electrodes CE, such as bumps and internal circuits, formed in the same way as in the interposer 13. When the semiconductor test device 100 accommodating the stacked semiconductor memory 15 is placed on the test interposer 13, a bottom of the electrical path portion 130 may make contact with the connection electrode CE.

[0092] Then, as shown in FIG. 5, the stacked semiconductor memory 15 may be pressed from above using a sponge pad 18 and a chuck 19. When the stacked semiconductor memory 15 applies stress to a lower portion, the elastic matrix of the electrical path portion 130 may be compressed, allowing electrical connection to the micro bump MB. As the electrical path portions 130 are slightly compressed due to their elasticity, all the electrical path portions 130 and all the micro bumps MB can make stable contact. When the electrical path portions 130 are compressed, the conductivity increases as the plurality of particles, rods, wires, balls, or flakes with conductivity within the electrical path portions 130 form new conductive paths, enabling the transmission of electrical signals from the top to the bottom of the electrical path portions 130. In this case, because the electrical path portions 130 possess elasticity, the stress applied to the micro bumps MB is minimized and thus damage to the micro bumps MB may be prevented. Since electrical connections can be made from the micro bumps MB through the electrical path portions 130 to the test interposer 13, it is possible to test the stacked semiconductor memory 15. Additionally, a test package substrate 12 may be further connected to a lower portion of the test interposer 13 to perform the test.

[0093] When the stress compressing the stacked semiconductor memory 15 is released, the elastic matrix of the electrical path portion 130 restores to its original shape, reducing conductivity and allowing the electrical connection to the micro bump MB to be disconnected. Here, the disconnection of the electrical connection may include terminating the test by releasing the contact between some electrical path portions 130 and some micro bumps MB.

[0094] FIGS. 6 to 7 illustrate schematic diagrams showing a manufacturing process of a semiconductor test device according to an embodiment of the present invention.

[0095] Referring to (a) of FIG. 6, a support substrate 210 may be provided. The support substrate 210 may be made of a material such as glass, wafers, or quartz in a plate shape. Subsequently, a membrane portion 110 may be formed on the support substrate 210. Then, to form aperture patterns P in the membrane portion 110, a patterned etch-resistant pattern 220 may be formed on the membrane portion 110. For example, the etch-resistant pattern 220 may be made of photoresist, oxide, nitride, or the like.

[0096] Next, referring to (b) of FIG. 6, the membrane portion 110 may be etched to form the aperture patterns P. Wet etching, dry etching, or scribing may be used. After forming the aperture patterns P, the etch-resistant pattern 220 may be removed, and cleaning may be performed.

[0097] Next, referring to (c) of FIG. 6, an electrical path portion 130 may be formed within the aperture pattern P. The electrical path portion 130 may be formed using various methods such as printing, deposition, sputtering, plating, or spraying without limitation. The electrical path portion 130 may be formed to be the same thickness as or thicker than the membrane portion 110.

[0098] Next, referring to (d) of FIG. 7, a holder portion 150 may be connected to the membrane portion 110. The holder portion 150 may be connected to an edge portion of the membrane portion 110, where the aperture pattern P is not formed, using adhesive means or by welding.

[0099] Next, referring to (e) of FIG. 7, the membrane portion 110 may be separated from the support substrate 210. Separation may be performed by applying heat, chemical treatment, ultrasound, or light irradiation to the interface between the membrane portion 110 and the support substrate 210. After the separation of the membrane portion 110 from the support substrate 210, the membrane portion 110 may be connected to the holder portion 150, and the manufacturing of a semiconductor test device 100 with the electrical path portion 130 formed in each aperture pattern P may be completed.

[0100] FIGS. 8 to 9 illustrate schematic diagrams showing a manufacturing process of a semiconductor test device according to another embodiment of the present invention.

[0101] Referring to (a) of FIG. 8, a support substrate 210 having a trench TR formed thereon may be provided. A position at which the trench TR is formed may correspond to the position where an aperture pattern P or an electrical path portion 130 is to be formed. The depth of the trench TR may correspond to the height at which the electrical path portion 130 will protrude above the membrane portion 110.

[0102] Next, referring to (b) of FIG. 8, a membrane portion 110 may be formed on the support substrate 210. A part of the membrane portion 110 may be formed within the trench TR of the support substrate 210

[0103] Next, referring to (c) of FIG. 8, to form the aperture patterns P in the membrane portion 110, a patterned etch-resistant pattern (not shown) (see 220 in FIG. 6) may be formed on the membrane portion 110. Subsequently, the membrane portion 110 may be etched to form the aperture patterns P. Wet etching, dry etching, or scribing may be used. Alternatively, the aperture patterns P may also be formed in the membrane portion 110 by imprinting, where the membrane portion 110 is pressed with a mold, without the need to form an etch-resistant pattern.

[0104] Next, referring to (d) of FIG. 9, an electrical path portion 130 may be formed within the aperture pattern P. The electrical path portion 130 may be formed using various methods such as printing, deposition, sputtering, plating, or spraying without limitation. As the electrical path portion 130 is formed not only in the aperture pattern P but also in the trench TR, the electrical path portion 130 may be formed to be thicker than the membrane portion 110.

[0105] Subsequently, the holder portion 150 may be connected to the membrane portion 110. The connection of the holder portion 150 may also be performed before the formation of the electrical path portion 130.

[0106] Next, referring to (e) of FIG. 9, the membrane portion 110 may be separated from the support substrate 210, completing the manufacturing of the semiconductor test device 100.

[0107] FIG. 10 illustrates a schematic diagram showing a semiconductor test device according to a second embodiment of the present invention. Hereinafter, the description of components that are the same as those in the semiconductor test device of the first embodiment described above with reference to FIGS. 3 to 5 will be omitted, and only the differences will be described.

[0108] Referring to FIG. 10, a semiconductor test device 100 (100-2) according to the second embodiment may include a membrane portion 110 (110-2) and a holder portion 150. The membrane portion 110 may include a plurality of aperture patterns P, and an electrical connection path may be provided from the top to the bottom of each aperture pattern P. This electrical connection path may be provided through an electrical path portion 130 that includes a conductive material.

[0109] According to an embodiment, the membrane portion 110 (110-2) may include a metal thin film portion 111 and an insulating layer portion 115. Each of the aperture patterns P formed in the metal thin film portion 111 may be in contact, in one-to-one correspondence, with micro bumps MB (MB2) on a lower portion of a stacked semiconductor memory 15.

[0110] The membrane portion 110 should be able to accommodate the formation of a plurality of aperture patterns P at a level of several to several tens of micrometers. Additionally, the membrane portion 110 may use a material with low thermal expansion and low thermal contraction due to temperature changes, that is, a material with a low CTE. Furthermore, the membrane portion 110 may be made of a material that is durable and resistant to deformation, especially in the X and Y directions. Considering these factors, the metal thin film portion 111 of the membrane portion 110 may be made of a material such as Invar, Super Invar, nickel-iron alloy, nickel-cobalt alloy, or nickel-iron-cobalt alloy.

[0111] The thickness T2 of the membrane portion 110, the pitch and width W3 of the aperture patterns P, and the like may be formed to the same sizes as described above with reference to FIG. 3. However, the thickness of the insulating layer portion 115 formed on the surface of the metal thin film portion 111 may be further considered. The insulating layer portion 115 may be formed to have a thickness less than approximately 5 m. Considering this factor, the thickness T2 of the membrane portion 110 is derived by taking into account the thickness T3 of the metal thin film portion 111 and the thickness T4 of the insulating layer portion 115. Additionally, the width W2 of the aperture pattern P of the membrane portion 110 may be derived by taking into consideration the width W3 of the aperture pattern of the metal thin film portion and the width W4 of the insulating layer portion 115.

[0112] Since the metal thin film portion 111 is made of a conductive material, there is a risk of short circuits when it comes into contact with the micro bump MB. Therefore, the surface of the metal thin film portion 111 may be coated with the insulating layer portion 115 to ensure that the surface of the membrane portion 110 exhibits insulating properties.

[0113] The formation process and materials of the electrical path portion 130 and the holder portion 150 are the same as those described above with reference to FIG. 3.

[0114] The semiconductor test device 100 (100-2) according to the second embodiment of the present invention has the advantage of a simplified manufacturing process since the basic frame of the membrane portion 110 can be composed of the metal thin film portion 111. It is easy to form the metal thin film portion 111 having fine aperture patterns P by applying processes such as photolithography and electroforming, and the process of coating the insulating layer portion 115 may also be performed easily.

[0115] Additionally, when the holder portion 150 is made from the same material as the metal thin film portion 111 or from a metal material, it has the advantage of higher adhesion, making it easier to connect each other, and it also facilitates welding.

[0116] In addition, since the membrane portion 110 (110-2) includes the metal thin film portion 111, there is an advantage in that the membrane portion 110 can be controlled by applying a magnetic force from the outside. For example, in the process of aligning the micro bumps MB of the stacked semiconductor memory 15 with the electrical path portions 130, as shown in FIG. 4, the membrane portion 110 (or the electrical path portions 130) may be controlled to make close contact with the micro bumps MB by applying a magnetic force without the need to apply physical stress, providing a unique effect. Alternatively, in the process of aligning the micro bumps MB of the stacked semiconductor memory 15 with the electrical path portions 130, a magnetic force may be applied at the same time as applying relatively less physical stress, minimizing damage to the micro bumps MB and enabling close contact with the membrane portion 110 (or the electrical path portions 130).

[0117] Meanwhile, when the holder portion 150 is made of a conductive material, connecting the holder portion 150 to a ground electrode may allow the metal thin film portion 111 to be grounded through the holder portion 150. This may prevent unintended current from passing through the metal thin film portion 111 and adversely affecting the testing of the stacked semiconductor memory 15.

[0118] FIGS. 11 to 12 illustrate schematic diagrams showing a manufacturing process of a semiconductor test device according to still another embodiment of the present invention.

[0119] Referring to (a) of FIG. 11, a support substrate 210 may be prepared. The support substrate 210 may be made of a material such as glass, wafers, or quartz in a plate shape. Next, a temporary adhering portion 230 may be formed on the support substrate 210. The temporary adhering portion 230 may be made of a material that provides temporary adhesion and may be removed and cleaned afterward, such as dry film resist or liquid wax. Subsequently, a metal sheet may be adhered onto the temporary adhering portion 230. Afterward, a patterned etch-resistant pattern 240 may be formed on the metal sheet, and etching may be performed through a pattern of the etch-resistant pattern 240. Aperture patterns P1 may be formed on the metal sheet through etching, thereby fabricating the metal thin film portion 111.

[0120] Next, referring to (b) of FIG. 11, a holder portion 150 of the metal thin film portion 111 may be connected. The holder portion 150 may be connected to an edge portion of the membrane portion 110, where the aperture pattern P is not formed, using adhesive means or by welding. If welding is performed, a weld bead WB is formed, and the metal thin film portion 111 and the holder portion 150 may be integrally connected.

[0121] Next, referring to (c) of FIG. 11, the metal thin film portion 111 may be separated from the support substrate 210. Separation may be performed by applying heat, chemical treatment, ultrasound, or light irradiation to the temporary adhering portion 230 between the membrane portion 110 and the support substrate 210.

[0122] Next, referring to (d) of FIG. 12, an insulating layer portion 115 may be coated on the surface of the connected structure of the metal thin film portion 111 and the holder portion 150. The insulating layer portion 115 may be made of an insulating material such as polyimide, rubber, resin, Teflon, polymer, curable photoresist, inorganic insulator, or organic insulator, which is used to form the membrane portion 110 described above with reference to FIG. 3. The insulating layer portion 115 is not necessarily coated on the entire surface of the holder portion 150 as long as it is coated on the surface of the metal thin film portion 111.

[0123] The insulating layer portion 115 may be coated on the aperture patterns P1 of the metal thin film portion 111, thereby finalizing the aperture patterns P (P2) of the membrane portion 110 (110-2).

[0124] Next, referring to (e) of FIG. 12, an electrical path portion 130 may be formed within the aperture pattern P (P2). The electrical path portion 130 may be formed using various methods such as printing, deposition, sputtering, plating, or spraying without limitation. The electrical path portion 130 may be formed to be the same thickness as or thicker than the membrane portion 110. Through this process, the manufacturing of the semiconductor test device 100 (100-2), in which the membrane portion 110 (110-2) with the insulating layer portion 115 coated on the surface of the metal thin film portion 111 is connected to the holder portion 150 and the electrical path portions 130 are formed in the aperture patterns P, may be completed.

[0125] FIG. 13 illustrates a schematic diagram showing a semiconductor test device according to a third embodiment of the present invention. Hereinafter, the description of components that are the same as those in the semiconductor test devices 100-1 and 100-2 of the first and second embodiments described above with reference to FIGS. 3 to 5 and FIG. 10 will be omitted, and only the differences will be described.

[0126] Referring to FIG. 13, a semiconductor test device 100 (100-3) according to the third embodiment may include a membrane portion 110 (110-3) and a holder portion 150. The membrane portion 110 may include a plurality of aperture patterns P, and an electrical connection path may be provided from the top to the bottom of each aperture pattern P. This electrical connection path may be provided through an electrical path portion 130 that includes a conductive material.

[0127] According to an embodiment, the membrane portion 110 (110-3) may include a metal thin film portion 111 and an insulating layer portion 115a. Each of the aperture patterns P formed in the metal thin film portion 111 may be in contact, in one-to-one correspondence, with micro bumps MB (MB2) on a lower portion of a stacked semiconductor memory 15.

[0128] The membrane portion 110 should be able to accommodate the formation of a plurality of aperture patterns P at a level of several to several tens of micrometers. Additionally, the membrane portion 110 may use a material with low thermal expansion and low thermal contraction due to temperature changes, that is, a material with a low CTE. Furthermore, the membrane portion 110 may be made of a material that is durable and resistant to deformation, especially in the X and Y directions. Considering these factors, the metal thin film portion 111 of the membrane portion 110 may be made of a material such as Invar, Super Invar, nickel-iron alloy, nickel-cobalt alloy, or nickel-iron-cobalt alloy.

[0129] The thickness T2 of the membrane portion 110, the pitch and width W3 of the aperture patterns P, and the like may be formed to the same sizes as described above with reference to FIG. 10. The thickness T2 of the membrane portion 115 is derived by taking into account the thickness T3 of the metal thin film portion 110 and the thickness T4 of the insulating layer portion 111. Additionally, the width W2 of the aperture pattern P of the membrane portion 110 may be derived by taking into consideration the width W3 of the aperture pattern of the metal thin film portion and the width W4 of the insulating layer portion 115.

[0130] Since the metal thin film portion 111 is made of a conductive material, there is a risk of short circuits when it comes into contact with the micro bump MB. Therefore, the surface of the metal thin film portion 111 may be coated with the insulating layer portion 115 (115a) to ensure that the surface of the membrane portion 110 exhibits insulating properties. The insulating layer portion 115 (115b) may also be formed on the surface of the holder portion 150, but it is not necessarily formed on the surface of the holder portion 150 if the purpose is to insulate the holder portion 150 without making contact with the micro bumps MB. In this specification, it is assumed that the insulating layer portion 115 (115b) is formed at least on the lower surface of the holder portion 150 to enhance insulation from a lower interposer 13 (see FIG. 5).

[0131] The formation process and material of the electrical path portion 130 are the same as those described above with reference to FIG. 3.

[0132] The semiconductor test device 100 (100-3) according to the third embodiment is characterized by the holder portion 150 being integrally connected to the metal thin film portion 111. Here, integrally connected means that the metal thin film portion 111 and the holder portion 150 are not connected through adhesive means but are understood to be connected as a single body made from the same material. The metal thin film portion 111 and the holder portion 150 can be understood as specific portions of the metal sheet 105, which will be described below with reference to FIG. 13, where a certain part is removed, with one part being referred to as the metal thin film portion 111 and the remaining part as the holder portion 150.

[0133] Since the metal thin film portion 111 and the holder portion 150 are derived from the same raw material, they may be made of the same metal material. The metal thin film portion 111 and the holder portion 150 may be made from a material with a low CTE to prevent thermal deformation, such as Invar, Super Invar, nickel-iron alloy, nickel-cobalt alloy, nickel-iron-cobalt alloy or nickel.

[0134] For example, the thickness T5 of the holder portion 150 may correspond to the thickness of the raw material, the metal sheet 210, ranging from 150 m to 1,000 m. The membrane portion 110 (110-3) may be derived by subtracting the thickness of a hollow region R from the holder portion 150. For example, the thickness T2 of the membrane portion 110 may be approximately 5 to 50 m.

[0135] The semiconductor test device 100 (100-3) according to the third embodiment of the present invention has the advantage of a simplified manufacturing process since the basic frame of the membrane portion 110 can be composed of the metal thin film portion 111. Moreover, because the metal thin film portion 111 and the holder portion 150 can be simultaneously formed from a single raw material through a simple process without the need for a separate process for connecting them, the manufacturing process becomes even simpler. It is easy to form the holder portion 150 having the hollow region R and the metal thin film portion 111 having fine aperture patterns P by applying processes such as photolithography and electroforming, and the process of coating the insulating layer portion 115 may also be performed easily.

[0136] Additionally, since the metal thin film portion 111 and the holder portion 150 are integrally formed from the same metal material, there is a significant advantage in that the likelihood of the metal thin film portion 111 and the holder portion 150 misaligning or deforming is extremely low.

[0137] Furthermore, as the membrane portion 110 (110-3) includes the metal thin film portion 111, it has the same advantage described above with reference to FIG. 10, where the membrane portion 110 can be controlled by applying a magnetic force from the outside.

[0138] Meanwhile, since the holder portion 150 is made of a conductive material, the metal thin film portion 111 may be grounded through the holder portion 150 by connecting the holder portion 150 to a ground electrode. The metal thin film portion 111 may be directly connected to a ground electrode for grounding. This may prevent unintended current from passing through the metal thin film portion 111 and adversely affecting the testing of the stacked semiconductor memory 15. It also minimizes the impact on adjacent micro bumps MB due to induced current, leakage current, or crosstalk in the metal thin film portion 111. Of course, the insulating layer portion 115 may be coated over all surfaces of the metal thin film portion 111 and the holder portion 150 to implement insulation in areas other than the electrical path portion 130.

[0139] FIGS. 14 to 15 illustrate schematic diagrams showing a manufacturing process of the semiconductor test device according to the third embodiment of the present invention. Hereinafter, the description of components that are the same as those in the semiconductor test device of the second embodiment described above with reference to FIGS. 11 to 12 will be omitted, and only the differences will be described.

[0140] Referring to (a) of FIG. 14, a support substrate 210 may be prepared. Next, a temporary adhering portion 230 may be formed on the support substrate 210. Subsequently, a metal sheet 105 may be adhered onto the temporary adhering portion 230.

[0141] Next, referring to (b) of FIG. 14, the thickness of the upper surface of the metal sheet 105 may be reduced. Methods such as touch polishing, dry etching, wet etching, and the like may be used without limitation for the thickness reduction. For example, an etch-resistant pattern 235 may be formed on the upper surface of the metal sheet 105 except for the portion where a cell portion C will be formed, and then etching may be performed on an exposed part of the metal sheet 105 to reduce its thickness. As a result of the thickness reduction in the central part of the metal sheet 105 where the cell portion C will be formed, a hollow region R may be created.

[0142] Next, referring to (c) of FIG. 14, a patterned etch-resistant pattern 240 may be formed on the hollow region R of the metal sheet 105, and etching may be performed through a pattern of the etch-resistant pattern 240. Aperture patterns P3 may be formed by etching the exposed portions of the metal sheet 105 between the patterns of the etch-resistant pattern 240, thereby fabricating the metal thin film portion 111.

[0143] The thin portion with the aperture patterns P3 formed may be provided as the metal thin film portion 111, while the thicker portion that is integrally connected to the edge of the metal thin film portion 111 may be provided as the holder portion 150.

[0144] Next, referring to (d) of FIG. 15, the metal thin film portion 111 and the holder portion 150 may be separated from the support substrate 210. Separation may be performed by applying heat, chemical treatment, ultrasound, or light irradiation to the temporary adhering portion 230 between the membrane portion 110 and the support substrate 210. Cleaning of the etch-resistant patterns 235 and 240 may also be performed.

[0145] Since the thickness T5 of the holder portion 150 is thicker than the thickness T3 of the metal thin film portion 111, the holder portion 150 has higher rigidity and may support the metal thin film portion 111 in both the vertical and lateral directions. In addition, the metal thin film portion 111 is connected to the holder portion 150 along its entire perimeter. As a result, tensile force may be uniformly transmitted to the entire perimeter of the metal thin film portion 111 without the need to apply tensile force outward along the entire edge of the holder portion 150. In other words, even if tensile force is applied to specific points of the holder portion 150, the tensile force does not act solely at those specific points on the metal thin film portion 111 but is instead uniformly distributed along the perimeter of the metal thin film portion 111 surrounding those points. Ultimately, this provides the advantage of allowing the metal thin film portion 111 to be evenly stretched taut by controlling only the holder portion 150 to achieve a uniform and fine distribution of tensile force along the perimeter of the metal thin film portion 111.

[0146] Next, referring to (e) of FIG. 15, the insulating layer portion 115 (115a and 115b) may be coated on the surface of the connected structure of the metal thin film portion 111 and the holder portion 150. The insulating layer portion 115 may be made of an insulating material such as polyimide, rubber, resin, Teflon, polymer, curable photoresist, inorganic insulator, or organic insulator, which is used to form the membrane portion 110 described above with reference to FIG. 3. The insulating layer portion 115 is not necessarily coated on the entire surface of the holder portion 150 as long as it is coated on the surface of the metal thin film portion 111.

[0147] Meanwhile, the dotted-line area on the right side of (e) of FIG. 15 delineates a membrane portion 110 (110-4) according to another embodiment. Referring to the dotted-line area, the membrane portion 110 (110-4) may be configured with a metal thin film portion 111-2 and an insulating layer 115a on the lower portion of the holder portion 150-2, rather than the side of the holder portion 150. The holder portion 150-2 may be integrally connected to the membrane portion 110-4, and the insulating layer 115a may be coated on the surface of the metal thin film portion 111-2.

[0148] The insulating layer portion 115 may be coated on the aperture patterns P3 of the metal thin film portion 111, thereby finalizing the aperture patterns P (P4) of the membrane portion 110 (110-3).

[0149] Next, referring to (f) of FIG. 15, an electrical path portion 130 may be formed within the aperture pattern P (P4). Through this process, the manufacturing of the semiconductor test device 100 (100-3), in which the metal thin film part (111) and the holder portion (150) are integrally connected as a single body made from the same material, may be completed.

[0150] FIGS. 16 to 17 illustrate schematic diagrams showing the forms of semiconductor test devices 100 (100-4 to 100-6) according to fourth to sixth embodiments of the present invention.

[0151] Referring to (a) of FIG. 16, a semiconductor test device 100 (100-4) may provide a plurality of hollow regions R (R-a, R-b, and R-c) (or a plurality cell portions C1, C2, and C3). The plurality of hollow regions R may be arranged in the X-axis and Y-axis directions on the horizontal plane.

[0152] The size (horizontal area) of each hollow region R (R-a, R-b, and R-c) may correspond to the size of a single stacked semiconductor memory 15, which is several millimeters to several tens of millimeters in width and height. In addition to a holder portion 150 being disposed at the edge of the semiconductor test device 100 (100-4) to partition each hollow region R, grid portions 155 with a thickness corresponding to the holder portion 150 may be formed in the central part of the semiconductor test device 100 (100-4), dividing the hollow region R into multiple sections. As a result, the semiconductor test device 100 (100-4) may test multiple stacked semiconductor memories 15 simultaneously.

[0153] In another example, referring to (b) of FIG. 16, cutting SP may be performed on the semiconductor test device 100 (100-4) shown in (a) of FIG. 16. Through this cutting SP, the semiconductor test device 100 (100-4) may be divided into multiple semiconductor test devices 100 (100-5a, 100-5b, and 100-5c). Each of the semiconductor test devices 100*100-5a, 100-5b, and 100-5c) may be used to test a stacked semiconductor memory 15. Therefore, the present invention has the advantage of enabling the mass production of multiple semiconductor test devices 100 (100-5a, 100-5b, and 100-5c).

[0154] In another example, referring to FIG. 17, the size (horizontal area) of a hollow region R (R-L) of a semiconductor test device 100 (100-6) may have an area corresponding to a stacked semiconductor memory 15-L that includes a plurality of cells/a plurality of dies. Alternatively, the size of the hollow region R (R-L) may correspond to the size of a silicon wafer or be larger than that. Therefore, the present invention has the advantage of providing a semiconductor testing device 100 (100-6) capable of performing tests for stacked semiconductor memories of various sizes.

[0155] FIG. 18 illustrates a schematic diagram showing a semiconductor test device according to a seventh embodiment of the present invention. FIG. 19 illustrates a schematic diagram showing a semiconductor test device according to an eighth embodiment of the present invention. Hereinafter, the description of components that are the same as those in the semiconductor test devices 100-1, 100-2, and 100-3 of the first, second, and third embodiments described above with reference to FIGS. 3 to 5, FIG. 10, and FIG. 13 will be omitted, and only the differences will be described.

[0156] Referring to FIG. 18, a semiconductor test device 100 (100-7) according to the seventh embodiment may include a membrane portion 110 (110-2) and a holder portion 150. The membrane portion 110 may include a plurality of aperture patterns P, and an electrical connection path may be provided from the top to the bottom of each aperture pattern P. This electrical connection path may be provided through a conductive thin film layer 140 formed on the side surfaces of the aperture pattern P.

[0157] According to an embodiment, the membrane portion 110 (110-2) may include a metal thin film portion 111 and an insulating layer portion 115. Each of the aperture patterns P formed in the metal thin film portion 111 may correspond one-to-one to micro bumps MB (MB2) on the lower portion of the stacked semiconductor memory 15. The conductive thin film layer 140 formed on the insulating layer portion 115 within the aperture pattern P (or on the side of the aperture pattern P) may make contact with the micro bump MB. The material, size, and the like of the membrane portion 110 may be the same as those of the membrane portion 110 described above with reference to FIG. 10.

[0158] The semiconductor test device 100 (100-7) according to the seventh embodiment is characterized by including the conductive thin film layer 140 formed on the side surfaces of the aperture pattern P, instead of the electrical path portion 130 filled in the aperture pattern P. The conductive thin film layer 140 may be formed entirely along the side of the aperture pattern P and may provide electrical connection from the top to the bottom of the aperture pattern P.

[0159] The conductive thin film layer 140 may include a conductive material. Preferably, the conductive thin film layer 140 may include a material with excellent conductivity, such as Cu, Ag, Au, Pt, Sn or Pd. The conductive thin film layer 140 is formed by deposition, sputtering, or similar processes, and is preferably formed as a thin film of approximately 1 nm to 1 m thick, so as not to affect the width of the aperture pattern P.

[0160] Referring to FIG. 19, a semiconductor test device 100 (100-8) according to the eighth embodiment may include a membrane portion 110 (110-3) and a holder portion 150. The membrane portion 110 may include a plurality of aperture patterns P, and an electrical connection path may be provided from the top to the bottom of each aperture pattern P. This electrical connection path may be provided through a conductive thin film layer 140 formed on the side surfaces of the aperture pattern P.

[0161] According to an embodiment, the membrane portion 110 (110-3) may include a metal thin film portion 111 and an insulating layer portion 115a.

[0162] The semiconductor test device 100 (100-8) according to the eighth embodiment may have the holder portion 150 integrally connected to the metal thin film portion 111. Here, integrally connected means that the metal thin film portion 111 and the holder portion 150 are not connected through adhesive means but are understood to be connected as a single body made from the same material.

[0163] Additionally, similar to the seventh embodiment, the semiconductor test device 100 (100-8) according to the eighth embodiment is characterized by including a conductive thin film layer 140 formed on the side surfaces of the aperture pattern P instead of the electrical path portion 130 filled in the aperture pattern P. The conductive thin film layer 140 may be formed entirely along the side of the aperture pattern P and may provide electrical connection from the top to the bottom of the aperture pattern P.

[0164] Meanwhile, similar to the first embodiment described above with reference to FIG. 3, an embodiment may also be provided in which a membrane portion 110 (110-1) and a holder portion 150 are included and a conductive thin film layer 140 is formed on the side surface of each aperture pattern P formed in the insulating membrane portion 110 (110-1).

[0165] FIGS. 20 and 21 illustrate schematic side cross-sectional views showing the forms of aperture patterns and conductive thin film layers according to various embodiments of the present invention.

[0166] Referring to FIGS. 20 and 21, various forms of aperture patterns P (Pa to Pe) and conductive thin film layers 140a to 140f that can contact micro bumps MB (MB2) on the lower portion of a stacked semiconductor memory 15 may be proposed.

[0167] Referring to (a) of FIG. 20, a vertical aperture pattern Pa and a conductive thin film layer 140a formed on its side may be provided. Since the conductive thin film layer 140a may also be formed in a vertical direction, the width of the aperture pattern Pa extending from an upper edge CP1 to a lower edge CP2 may remain constant. The micro bump MB (MB2) may be in contact with the upper edge CP1.

[0168] Referring to (b) and (c) of FIG. 20, overall reverse taper-shaped aperture patterns Pb and Pc and conductive thin film layers 140b and 140c formed on their sides may be provided. In (c) of FIG. 20, for example, as a result of isotropic etching such as wet etching, the side of the aperture pattern Pc may exhibit a concave curvature. The conductive thin film layers 140b and 140c are formed such that the width of the aperture patterns Pb and Pc decreases from the upper edge CP1 to the lower edge CP2. The micro bump MB may be in contact with the upper edge CP1. In this process, at least portion of the approximately spherical-shaped micro bumps MB may be accommodated within the reverse taper-shaped aperture patterns Pb and Pc. The micro bumps MB may be guided along the side of the aperture patterns Pb and Pc and come into contact with the conductive thin film layers 140b and 140c. As a result, there is an effect of providing stable contact with a plurality of micro bumps MB. In addition, regardless of the diameter of the micro bumps MB, a portion may be accommodated within the aperture patterns Pb and Pc, guiding contact with the conductive thin film layers 140b and 140c.

[0169] Referring to (a) of FIG. 21, the width of the aperture pattern Pd decreases from the upper edge CP1 to a middle edge CP3 and then increases from the middle edge CP3 to the lower edge CP2. (a) of FIG. 21 may be the result of, for example, performing wet etching on each of the upper and lower surfaces, allowing an upper pattern P1 and a lower pattern P2 to communicate with each other to form the aperture pattern Pd. The micro bump MB may be guided along a side reverse tapered from the upper edge CP1 to the middle edge CP3 of the aperture pattern Pd and make contact with the conductive thin film layer 140d. Additionally, there is the advantage that the connection electrode CE of the test interposer 13 (see (b) of FIG. 4) or other elements may be guided from the lower part of the aperture pattern Pd along the tapered side from the lower edge CP2 to the middle edge CP3 and make contact with the conductive thin film layer 140d.

[0170] Referring to (b) of FIG. 21, an aperture pattern Pe with an overall reverse-taper shape is provided, wherein the aperture pattern Pe has a two-step concave curvature shape from the upper edge CP1 to the middle edge CP3, and from the middle edge CP3 to the lower edge CP2. (b) of FIG. 21 may be the result of, for example, performing a first wet etching on the upper surface to form an upper pattern P3, followed by a second wet etching on the same upper surface to form a lower pattern (P4), which then communicates with the upper pattern P3 to form the aperture pattern Pe. Similar to (b) and (c) of FIG. 20, at least part of the approximately spherical-shaped micro bump MB may be accommodated within the reverse-tapered aperture pattern Pe, allowing stable contact with a conductive thin film layer 140e.

[0171] Referring to (c) of FIG. 21, in addition to the formation of a conductive thin film layer 140f on the side of the aperture pattern Pa, additional conductive thin film layers 141 and 142 may be further formed around the upper and lower parts of the aperture pattern Pa. Specifically, the conductive thin film layers 141 and 142 may be formed horizontally on the upper surface of the membrane portion 110 from the upper edge CP1 of the aperture pattern Pa and on the lower surface of the membrane portion 110 from the lower edge CP2. The width WP of the conductive thin film layers 141 and 142 formed in the horizontal direction is preferably within a range that does not affect neighboring aperture patterns Pa. For example, the width WP of the conductive thin film layers 141 and 142 formed in the horizontal direction may be 50% or less (greater than 0) of the width of the aperture pattern Pa.

[0172] Since not only the conductive thin film layer 140f formed on the side surfaces of the aperture pattern Pa but also the additional conductive thin film layers 141 and 142 formed horizontally on the upper and lower surfaces of the membrane 110 are included, the contact stability with the micro bump MB can be improved. This is particularly effective in enhancing the contact stability with various types of micro bumps MB, in addition to spherical-shaped micro bumps MB.

[0173] FIG. 22 illustrates a schematic plan view showing contact forms between aperture patterns and micro bumps according to various embodiments of the present invention.

[0174] When viewed from a planar direction (upper surface direction), the shape of an aperture pattern P may be rectangular, hexagonal, polygonal, or other shapes. Taking a spherical-shaped micro bump MB as an example, in a rectangular aperture pattern P as shown in (a) of FIG. 22, there are approximately four contact points CP, and in a hexagonal aperture pattern P as shown in (b) of FIG. 22, there are approximately six contact points CP. Because a conductive thin film layer 140 is formed along the edge of the aperture pattern P, an electrical connection path may be established to the bottom of the aperture pattern P along the contact points CP. Even if slight misalignment occurs, as long as a contact point CP is formed at least at one location, an electrical connection can be made, which is advantageous for forming a stable electrical connection path.

[0175] FIG. 23 illustrates schematic diagrams showing a manufacturing process of the semiconductor test device according to the seventh embodiment of the present invention. The description of components that are the same as those in the semiconductor test device of the second embodiment described above with reference to FIGS. 11 to 12 will be omitted, and only the differences will be described.

[0176] By performing the same processes as described in (a) to (c) of FIG. 11, a connected structure of a metal thin film portion 111 and a holder portion 150 may be prepared. Next, referring to (d) of FIG. 23, an insulating layer portion 115 may be coated on the surface of the connected structure of the metal thin film portion 111 and the holder portion 150. The insulating layer portion 115 may be coated on the aperture patterns P1 of the metal thin film portion 111, thereby finalizing the aperture patterns P (P2) of the membrane portion 110 (110-2).

[0177] Next, referring to (e) of FIG. 23, a conductive thin film layer 140 may be formed on the side surfaces of the aperture pattern P (P2). The conductive thin film layer 140 may include a material with excellent conductivity, such as Cu, Ag, Au, Pt, Sn or Pd. For example, a conductive thin film layer 140 made of Cu or Sn may be formed through sputtering, while a conductive thin film layer 140 made of Ag, Au, Pt, Sn or Pd may be formed through thermal evaporation. Additionally, methods such as printing, plating, or spraying may also be used. The thickness of the conductive thin film layer 140 can be formed to be approximately 1 m or less. The formation of the conductive thin film layer 140 has little to no effect on the width of the aperture pattern P.

[0178] Through this process, the manufacturing of the semiconductor test device 100 (100-7), in which the membrane portion 110 (110-2) with the insulating layer portion 115 coated on the surface of the metal thin film portion 111 is connected to the holder portion 150 and the conductive thin film layer 140 is formed in the aperture pattern P, may be completed.

[0179] Meanwhile, the semiconductor test device 100 (100-8) according to the eighth embodiment shown in FIG. 19 may also be manufactured by performing the processes described in (a) of FIG. 14 to (e) of FIG. 15 and then additionally forming the conductive thin film layer 140 on the side surfaces of the aperture pattern P.

[0180] FIG. 24 illustrates (a) a schematic cross-sectional side view and (b) a schematic plan view showing a conductive cantilever portion protruding inward from an aperture pattern according to an embodiment of the present invention.

[0181] Referring to FIG. 24, a conductive thin film layer 140g may further include a conductive cantilever portion CT protruding inward from an aperture pattern P (Pf). The conductive cantilever portion CT may protrude in a cantilever shape. The conductive cantilever portion CT may be integrally formed at the same time as the conductive thin film layer 140g or through an additional process. The conductive cantilever portion CT may be thinner than the thickness of the membrane portion and protrude from the aperture pattern P, allowing for elastic contact with a micro bump MB. For example, as shown in (b) of FIG. 24, the conductive cantilever portion CT may provide a rounded shape to the aperture pattern P (Pf), allowing the surface of the micro bump MB to naturally rest on the conductive cantilever portion CT.

[0182] FIG. 25 illustrates a schematic diagram showing a form of controlling a conductive cantilever portion by applying an external magnetic force, according to an embodiment of the present invention.

[0183] Referring to the left view in FIG. 25, an alignment error or height difference error of a specific micro bump MB among a plurality of micro bumps MB may result in it failing to make contact with the conductive thin film layer 140g. In this case, the shape of the cantilever portion CT may be controlled by applying an external magnetic force M.

[0184] Referring to the right view in FIG. 25, when a magnetic force M is applied from the outside, a force IF that attracts the cantilever portion CT may be applied. Accordingly, the cantilever portion CT may make contact with the micro bump MB, forming an electrical connection. Additionally, the contact force may be adjusted by bending the cantilever portion CT upward or downward depending on the application of the magnetic force M. For example, if a gap is created due to a height difference between neighboring micro bumps, the cantilever portion CT may be controlled to bend upward, while if the micro bump deforms by approximately 10 to 15% upon contact, the cantilever portion CT may be controlled to bend downward.

[0185] FIGS. 26 to 33 illustrate schematic diagrams showing a manufacturing process of a semiconductor test device according to the eighth embodiment of the present invention.

[0186] The metal thin film portion 111 may be formed using a thin film formation method, such as rolling process or electroforming process. In the following description, with reference to FIGS. 26 to 33, a method for forming the metal thin film portion 111 of the membrane portion 110 (110-8) using electroforming will be described. Meanwhile, although FIGS. 26 to 33 illustrate a semiconductor test device 100 (100-8) that includes a plurality of cell portions C, it should be noted that the same manufacturing process may be used to produce a device that includes a single cell portion C.

[0187] Referring to FIG. 26, a support 30 is prepared. The support 30 may be made of a conductive material to enable electroforming. To achieve both conductivity and low resistance, the support 30 (or a conductive substrate 30) may be highly doped at a concentration higher than or equal to 1019 cm-3. The doping may be performed over the entire support 30 or on only the surface of the support 30. According to one embodiment, the surface resistance of the support 30 may be 510-4 to 110-2 ohm cm. The support 30 may be used as a cathode electrode during electroforming.

[0188] Unlike metals with a metal oxide on the surface and polycrystalline silicon with grain boundaries, doped monocrystalline silicon, being free of defects, allows for the uniform formation of an electric field across the entire surface during electroforming, which results in a uniform plated film (or a metal thin film portion 111). As the metal thin film portion 111 prepared with the uniform plated film does not require additional processes a process to remove or address defects, costs for process is reduced and the productivity is improved.

[0189] Then, a patterned insulating portion M1 may be formed on one surface of the support 30. The insulating portion M1 is a part formed to protrude (embossed) from one surface of the support 30, and may have insulation properties to prevent the formation of the plated film (or the metal thin film portion 111). Accordingly, the insulating portion M1 may be made of at least one of a photoresist material, a silicon oxide material, or a silicon nitride material. The insulating portion M1 may be formed by forming a silicon oxide or a silicon nitride on the support 30 using deposition or the like, and thermal oxidation or thermal nitridation methods may be used employing the support 30 as a base. A photoresist may be formed using a printing method or the like.

[0190] The width md of the insulating portion M1 may corresponding to the upper width of the aperture pattern P. The upper width of the aperture pattern P may correspond to the minimum width required for the micro bump MB or the connection electrode CE to make contact. The width md of the insulating portion M1 may be formed at a level of several to several tens of micrometers to correspond to the width of the aperture pattern P. Meanwhile, as will be described below, since a trench portion TR is formed in the support 30, the insulating portion M1 may be formed with a thin thickness within the range required to form the trench portion TR. Considering that the trench portion TR corresponds to the thickness of the metal thin film portion 111 (approximately 5 to 50 m), the insulating portion M1 can be formed to be as thin as approximately 0.5 to 5 m. Therefore, there is an advantage in that the insulating portion M1 is easy to form and material usage can be reduced.

[0191] Then, the support 30 may be subjected to etching EC1. The etching EC1 may be performed on a first surface (or upper surface) of the support 30 exposed between patterns of the insulating portion M1. Dry etching or wet etching may be used for etching EC1. Wet etching has isotropic etching characteristics, while dry etching has isotropic etching characteristics and allows precise etching to a desired width. Alternatively, laser etching using femtosecond laser, picosecond laser, or the like may be used for precise etching. In the case of laser etching, the process of forming the insulating portion M1 may be omitted.

[0192] A trench portion TR recessed into the first surface (or upper surface) of the support 30 may be formed by etching EC1. A depth h of the trench portion TR may approximately correspond to the thickness of the metal thin film portion 111 to be formed. For example, the depth h of the trench portion TR may be approximately 5 to 50 m.

[0193] A plurality of trench portions TR may be formed by patterning. On the support 30 corresponding to the cell portion C, the trench portion TR may be formed to inversely correspond to the aperture pattern P. In other words, the area where the trench portion TR is not formed in the cell portion C may later become the aperture pattern P.

[0194] The trench portion TR may include a bottom surface BS and side surfaces SS. The side surfaces SS may be formed to be inclined either vertically or at a predetermined angle. When using wet etching EC1, which has isotropic etching characteristics, the side surfaces SS may be formed to be inclined at a predetermined angle. In other words, the side surfaces SS of the trench portion TR may be tapered. By taking into account the crystal orientation of the monocrystalline silicon material of the support 30 during etching, it is possible to implement the taper angle of the trench portion TR to correspond to the etching direction.

[0195] Then, referring to FIG. 27, a metal thin film portion 111 (111a) may be formed by performing electroforming on the support 30. The support 30 is used as a cathode body and an anode body (not shown) facing the support 30 is prepared. The anode body may be immersed in a plating solution (not shown), and the support 30 may be partially or entirely immersed in the plating solution. As the insulating portion M1 has the insulating properties, a plated film may not be formed in a region that corresponds to the insulating portion M1. In particular, the plated film may be formed in the trench portion TR to create the metal thin film portion 111. The thickness of the metal thin film portion 111 may be controlled to fill the trench portion TR without exceeding the height of the insulating portion M1. In other words, the electroforming may be performed such that an upper end of the metal thin film portion 111 is positioned higher than the first surface (or upper surface) of the support 30 and lower than an upper end of the insulating portion M1.

[0196] Meanwhile, the composition may be controlled to allow the metal thin film portion 111 to have a CTE similar to that of the silicon material of the support 30. After the manufacturing process, the support 30 may be provided as a holder portion 150 made of silicon material, and the metal thin film portion 111 needs to have a CTE similar to that of the holder portion 150 (30) to prevent sagging on the holder portion 150 (30). Additionally, this minimizes variations in alignment errors of the cell portions C and the aperture patterns P on the holder portion 150 (30).

[0197] Taking this into account, the composition of the metal thin film portion 111 may be controlled such that the CTE of the support 30 made of silicon material and the CTE of the metal thin film portion 111 after heat treatment H, which will be described below, become approximately (3.51)10-6/ C. Even when the metal thin film portion 111 is made of Invar material, varying the composition ratios of Fe and Ni during electroforming may enable precise control of the CTE to closely match that of the support 30 made of silicon material. Alternatively, the CTE of the metal thin film portion 111 may be controlled to be smaller or greater than that of the support 30 so that the metal thin film portion 111 can be tightly connected onto the support 30 depending on process temperature conditions.

[0198] Also, the metal thin film portion 111 formed by electroforming needs to be well adhered to the support 30 without peeling off during the subsequent processes, such as heat treatment H, etching EC2, and the like, which will be described below. To this end, various approaches may be considered.

[0199] In one approach, a native oxide of the support 30 on which electroforming is to be performed may be controlled. An oxide may be formed on the surface of the support 30 made of a silicon wafer material. On the surface with such an oxide, a uniform electric field may not be generated, and hence the plated film (metal thin film portion 111) may not be uniformly produced, and the adhesion between the produced plated film (metal thin film portion 111) and the support 30 may be low. Therefore, a process of removing native oxide is preferably followed by an electroforming process.

[0200] In another approach, another film may be further formed to mediate adhesion between the plated film (metal thin film portion) and the support 30. In addition to a barrier film, which will be described below, a film or a combination of films providing adhesion to both surfaces of the film may be used.

[0201] In still another approach, the surface of the support 30 may be pre-treated before electroforming. Through physical treatment or chemical treatment, the plated film (metal thin film portion 111) produced in the electroforming process may be formed on the support 30 with stronger adhesion. In addition, by controlling the plating method in the electroforming process, the plated film (metal thin film portion 111) may be formed on the support 30 with stronger adhesion.

[0202] Meanwhile, referring to FIG. 28, the metal thin film portion 111 (111b) may be configured as a laminate with two or more plated layers such that the metal thin film portion 111b has a CTE similar to that of the silicon material of the support 30. In this case, a first metal thin film portion 111-1 may be formed of a metal material capable of forming silicide with the support 30. The first metal thin film portion 111-1 may be formed of a material, such as Ni, Co, Ti, Cr, W, Mo, or the like, which exhibits high adhesion to the support 30 when produced by electroforming. A second metal thin film portion 111-2 may be made of a material, such as Invar, Super Invar, or the like, which exhibits a low CTE when produced by electroforming. As the first and second metal thin film portions 111-1 and 111-2 have different CTEs, the CTE of the metal thin film portion 111 may be controlled by adjusting the thickness ratio of the first and second mask metal thin film portions 111-1 and 111-2. The thickness ratio of the first and second metal thin film portions 111-1 and 111-2 may be controlled by adjusting the electroforming duration.

[0203] Additionally, during electroforming, the current density may be adjusted such that the metal thin film portion 111 (111b) is composed of two or more layers with different compositions. For instance, the metal thin film portion 111b may include a first metal thin film portion 111-1, which is either a pure Ni layer or a Ni-rich alloy layer, and a second metal thin film portion 111-2, which is an Invar alloy layer. First, by applying a first current density, the first metal thin film portion 111-1, which is a pure Ni layer or an alloy layer with Ni content greater than 60 wt %, may be formed on at least a portion of the bottom surface BS and side surfaces SS of the trench portion TR. Subsequently, by applying a second current density different from the first current density, the second metal thin film portion 111-2, which is a FeNi alloy layer (Invar layer) with Ni content of 36 wt % to 42 wt % may be formed on the first metal thin film portion 111-1. The second current density may be a value less than the first current density. For example, when the first current density is applied in an electroforming solution environment capable of forming FeNi alloy, a Ni-rich layer may be plated, and changing to the second current density may result in the deposition of a layer with an increased proportion of Fe.

[0204] However, the first metal thin film portion 111-1 needs to have a thinner thickness than the second metal thin film portion 111-2. In order to match the low CTE of the second metal thin film portion 111-2, it is preferable to form the first metal thin film portion 111-1 only to the extent necessary to ensure adhesion to the support 30. Taking this into consideration, the thickness of the first metal thin film portion 111-1 is preferably 2% to 20% of the thickness of the second metal thin film portion 111-2.

[0205] The Ni in the first metal thin film portion 111-1 is advantageous for forming silicide through heat treatment at relatively low temperatures compared to Invar. Additionally, since the adhesion between Ni in the first metal thin film portion 111-1 and Invar is good, the first metal thin film portion 111-1 may mediate adhesion between the support 30 of silicon material and the second metal thin film portion 111-2. Utilizing a Ni-rich first metal thin film portion 111-1 allows the formation of a connection portion 40 through heat treatment H (see FIG. 29) at temperatures below 400 C.

[0206] For another example, the metal thin film portion 111b may be configured with pure Ni layers or Ni-rich alloy layers included in the lower and upper layers, while incorporating an Invar alloy layer as an intermediate layer. In this case, during the electroforming process, an alloy layer with pure Ni or Ni content greater than 60 wt % may be formed as a lower layer (the first metal thin film portion) on at least a portion of the bottom surface BS and side surfaces SS of the trench portion TR by applying the first current density. Subsequently, by applying the second current density different from the first current density, a FeNi alloy layer (Invar layer) with Ni content of 36 wt % to 42 wt % may be formed as an intermediate layer (the second metal thin film portion). Then, by applying the first current density (or third current density) that is different from the second current density, an alloy layer with pure Ni or Ni content greater than 60 wt % may be formed as an upper layer (third metal thin film portion). The second current density may be a value less than the first current density (or the third current density). The thickness of the third metal thin film portion may correspond to the thickness of the first metal thin film portion.

[0207] In this case, the upper layer, which is an alloy layer with pure Ni or Ni content greater than 60 wt %, contains more Ni than the FeNi alloy layer (Invar layer) containing Fe, and thus can reduce the degree of oxidation during the subsequent heat treatment H process. Additionally, there is an advantage in protecting the intermediate layer as the upper layer is removed first during the subsequent planarization PS process.

[0208] Meanwhile, before electroforming of the metal thin film portion 111 (111a and 111b) shown in FIGS. 27 and 28, an auxiliary connection portion (not shown) may be further formed on at least a portion of the trench portion TR. For example, when the support 30 is a silicon wafer, the adhesion is higher when the metal thin film portion 111, made of a material such as Invar or Super Invar, is adhered to the support 30 through the auxiliary connection portion made of Ni, Cu, or the like, compared to direct adhesion of the metal thin film portion 111 to the support 30. Taking this into account, the auxiliary connection portion may include at least one of Ni, Cu, Ti, Au, Ag, Al, Sn, In, Bi, Zn, Sb, Ge, or Cd. If the material of the auxiliary connection portion makes electroforming difficult, it may be formed using methods such as sputtering or brazing. The auxiliary connection portion may be formed of a material such as Ni, Cu, Ti, Au, Ag, or Al that exhibit high adhesion to the support 30 when produced through electroforming. Alternatively, when formed by sputtering or brazing, the auxiliary connection portion may be composed of a material such as Sn, In, Bi, Zn, Sb, Ge, Cd, or the like that exhibit high adhesion to the support 30. The auxiliary connection portion may be thinly formed to have a thickness of 0.01 m to 0.2 m.

[0209] Then, referring to FIG. 29, heat treatment H may be performed on the metal thin film portion 111 and the support 30. A process of removing the insulating portion M1 may be performed before and/or after heat treatment H. The heat treatment may be performed at a temperature of 100 C. to 800 C. For example, when the metal thin film portion 111 is directly formed on the support 30, as shown in FIG. 27, heat treatment may be carried out at temperatures ranging from 300 C. to 800 C. For another example, when the first metal thin film portion 111-1 is formed between the second metal thin film portion 111-2 and the support 30, as shown in FIG. 28, heat treatment H may be performed at temperatures ranging from approximately 100 C. to 800 C., preferably in the low-temperature range of approximately 100 C. to 400 C. During the heat treatment H process, a predetermined pressure may be applied to perform the heat treatment with less heat.

[0210] Generally, compared to an Invar thin plate produced by rolling, the Invar thin plate produced by electroforming has a higher CTE. Therefore, performing heat treatment on the Invar thin plate may reduce the CTE. However, there may be slight deformation in the Invar thin plate during this heat treatment process. If heat treatment is performed only on the metal thin film portion 111 that exists separately, slight deformation may occur in the aperture patterns P. Therefore, performing heat treatment H while the support 30 and the metal thin film portion 111 are adhered to each other has the advantage of preventing the shape of the aperture pattern P from being slightly deformed due to the heat treatment.

[0211] In addition, the present invention involves the form in which the metal thin film portion 111 is precisely accommodated in the recessed trench portion TR of the support 30. When heat treatment H is performed in this state, a unique effect is achieved in which the side surfaces SS and the bottom surface BS of the trench portion TR can prevent the metal thin film portion 111 from deforming in the horizontal direction. Also, in the present invention, since the metal thin film portion 111 is accommodated in the trench portion TR, the contact area between the support 30 and the metal thin film portion 111 is further increased, which provides an advantage in facilitating the formation of the connection portion 40 through heat treatment H.

[0212] On the other hand, the Invar thin plate, produced by electroforming, and the silicon wafer have almost the same CTEs, approximately 3 to 4 ppi. Thus, even with the heat treatment H, the metal thin film portion 111 and the support 30 have the same or similar degree of thermal expansion, preventing misalignment due to thermal expansion and avoiding subtle deformations in the aperture patterns P.

[0213] Moreover, the present invention is characterized by the connection of the metal thin film portion 111 and the support 30 through the heat treatment H. During the heat treatment H process, the connection portion 40 may be formed between the metal thin film portion 111 and the support 30. The connection portion 40 may be provided as an intermetallic compound resulting from the combination of the components of the metal thin film portion 111 and the support 30. As the Fe and Ni components of the metal thin film portion 111 and the Si component of the support 30 are combined, the connection portion 40 may be provided as a silicide containing Ni and Si, containing Fe, Ni, and Si, or containing Fe, Ni and other components. The bonding strength of the intermetallic compound allows the metal thin film portion 111 and the support 30 to be connected to each other through the connection portion 40.

[0214] Additionally, according to an embodiment, the heat treatment H process may be carried out in multiple steps. As a 2-step heat treatment, Ni2Si may be formed in the low-temperature range (approximately 250 C. to 350 C.), adhering the metal thin film portion 111 to the support 30, followed by gradually raising the temperature to the high-temperature range (approximately 450 C. to 650 C.) to perform the heat treatment. In the case of an Invar metal thin film portion produced by electroforming, due to its microcrystalline and/or amorphous structure, a rapid increase in temperature during heat treatment may lead to the detachment or separation of the Invar metal thin film portion from the silicon wafer support 30 due to volume contraction. Therefore, it is preferable to perform heat treatment by gradually raising the temperature to high temperature after attaching the Invar metal thin film portion to the silicon wafer support 30 at low temperature.

[0215] In addition, according to an embodiment, a reducing atmosphere should be maintained during the heat treatment H. The reducing atmosphere may be formed as H2, Ar, or N2 atmosphere, and may preferably use a dry N2 gas to prevent oxidation of the Invar metal thin film portion. In order to prevent oxidation of the Invar metal thin film portion, it is necessary to manage the O2 concentration to be less than 100 ppm. Alternatively, a vacuum atmosphere of <10-2 torr may be formed. The heat treatment H may be performed for 30 minutes to 2 hours.

[0216] As the connection portion 40 (adhesive layer), such as Ni silicide, (Ni, Fe)Si silicide, etc., is formed on the interface of the electroformed metal thin film portion 111 on the silicon wafer support 30, the mask 20 and the support 30 may be connected to each other with the connection portion 40 interposed therebetween.

[0217] Meanwhile, to control the reaction of Ni and FeNi with Si during the heat treatment H, a barrier film (not shown) may be formed on the support 30 before electroforming the metal thin film portion 111 on the support 30. The barrier film may prevent the components (e.g., Ni and FeNi) of the metal thin film portion 111 from permeating uncontrollably into the silicon support 30. Also, the barrier film preferably has conductivity to allow electroforming to take place on the surface. Taking this into account, the barrier film may include a material, such as titanium nitride (TiN), titanium/titanium nitride (Ti/TiN), tungsten carbide (WC), titanium tungsten (WTi), graphene, or the like. A thin film formation process such as deposition of barrier film may be used without limitations. The barrier film may control the reaction of Fe and Ni with Si to ensure the formation of a uniform silicide and allow the metal thin film portion 111 and the connection portion 40 to be attached to each other with appropriate adherence strength. In addition, the barrier film may be configured as a film or a combination of films capable of providing predetermined adhesion or adherence so that the metal thin film portion 111 is not separated from the support 30 in a state in which the metal thin film portion 111 is electroformed on the support 30.

[0218] The thickness (silicide thickness) of the connection portion 40 may be controlled to 10 to 300 nm by adjusting temperature and time, facilitating the connection between the support 30 and the metal thin film portion 111.

[0219] On the other hand, when the above-described auxiliary connection portion is further interposed, a phase change occurs where the auxiliary connection portion between the metal thin film portion 111 and the support 30 is melted by the heat treatment and then solidifies again during the heat treatment H process. Through this phase change, the auxiliary connection portion may mediate the connection between the metal thin film portion 111 and the support 30. The auxiliary connection portion may act as an adhesion layer or a glue layer. From another perspective, the connection may be achieved by altering the interfacial state between the metal thin film portion 111, the support 30, and the auxiliary connection portion in a manner that metal components of the auxiliary connection portion diffuse into the metal thin film portion 111 and the support 30, or conversely, the components of the metal thin film portion 111 and the support 30 diffuse into the auxiliary connection portion, or in a manner that the components of the metal thin film portion 111, the support 30, and the auxiliary connection portion diffuse mutually into each other.

[0220] Meanwhile, although FIGS. 29 to 33 illustrate the state in which the connection portion 40 is formed after the heat treatment H, the heat treatment H process may be omitted, considering the connection strength between the metal thin film portion 111 and the support 30.

[0221] Then, referring to FIG. 30, planarization PS may be performed on the metal thin film portion 111. Here, planarization PS refers to flattening one surface (upper surface) of the metal thin film portion 111 while simultaneously partially removing the upper part of the metal thin film portion 111 to reduce the thickness (111->111). Planarization PS may be performed using methods such as lapping, polishing, buffing, etc.

[0222] After the planarization PS, the metal thin film portion 111 and the support 30 may share at least the same upper surface. As the planarization PS is performed while the metal thin film portion 111 is accommodated in the trench portion TR of the support 30, the metal thin film portion 111 can share the same upper surface with the support 30.

[0223] On the other hand, the heat treatment H of FIG. 29 and the planarization PS of FIG. 30 may also be applied in the reverse order. Planarization PS may be first performed on the metal thin film portion 111 to reduce the thickness (111->111), and then, through the heat treatment H, the connection portion 40 may be formed.

[0224] Then, referring to FIG. 31, the support 30 may be subjected to etching EC2. The etching EC2 may be performed on a second surface (lower surface) opposite to the first surface (upper surface) of the support 30 to which the metal thin film portion 111 is connected. The etching EC2 may be performed on a region of the support 30 corresponding to the cell portion C of the metal thin film portion 111. Optionally, before etching EC2 of the support 30, a thickness reduction process may be performed on the entire lower surface (second surface) or the central part of the support 30.

[0225] Once the etching EC2 is completed, the support 30 may take the form of providing a hollow region R with only the edge portion remaining. The support 30 may be provided as a holder portion 150. Since the support 30 is a silicon wafer, there is an advantage in that etching EC2 may be performed by utilizing existing semiconductor-related technologies and Micro-Electro Mechanical System (MEMS)-related technologies.

[0226] In order to impart etch resistance, an insulating portion M2 may be formed on the lower surface of the support 30 excluding the portions corresponding to the cell portions C. The insulating portion M2 may be formed of photoresist using a printing method or the like, and may be formed of silicon oxide or silicon nitride serving as a hard mask by a method such as thermal oxidation or thermal nitridation. Meanwhile, a metal may be used as a mask for etching. The exposed portion of the lower surface of the support 30, not covered by the insulating layer M2, may be subjected to etching EC2.

[0227] Additionally, the present invention has the effect of providing the connection portion 40 formed between the support 30 and the metal thin film portion 111 as a stopper during the etching EC2 process. As the etching EC2 progresses from the second surface of the support 30 toward the first surface, when it reaches the connection portion 40, the etching EC2 may not proceed any further. Consequently, damage to the metal thin film portion 111 or aperture patterns P may be prevented during the etching EC2 process.

[0228] The trench portion TR accommodates the metal thin film portion 111, allowing the metal thin film portion 111 to maintain its shape during the etching EC2 process. The portions between neighboring trench portions TR on the support 30 are removed after the etching EC2 process. This vacant space may be provided as the aperture pattern P of the metal thin film portion 111. If the side surface SS of the trench portion TR has an inclined or tapered shape, the side surfaces of the aperture pattern P may also have the corresponding inclined or tapered shape.

[0229] As the central portion of the support 30 is etched to provide the hollow region R, a connected structure in which the metal thin film portion 111 and the holder portion 150 (30) are integrally connected may be provided.

[0230] Next, referring to FIG. 32, the insulating portion M2 may be removed, and an insulating layer portion 115 may be coated on the surface of the connected structure of the metal thin film portion 111 and the holder portion 150 (30). The insulating layer portion 115) is coated on the aperture pattern P of the metal thin film portion 111, thereby finalizing the aperture pattern P of a membrane portion 110 (110-8). The process of forming the insulating layer portion 115 is the same as described above with reference to FIG. 12.

[0231] Next, referring to FIG. 33, a conductive thin film layer 140 may be formed on the side surfaces of the aperture pattern P. The process of forming the conductive thin film layer 140 is the same as described above with reference to FIG. 23. Through this process, the manufacturing of a semiconductor test device 100 (100-8), in which the membrane portion 110 (110-8) with the insulating layer portion 115 coated on the surface of the metal thin film portion 111 is connected to the holder portion 150 and the conductive thin film layer 140 is formed in the aperture pattern P, may be completed.

[0232] FIGS. 34 to 37 illustrate schematic diagrams showing a manufacturing process of a semiconductor test device 100 (100-9) according to a ninth embodiment of the present invention. FIGS. 34 to 37 illustrate an example in which a plurality of aperture patterns P are formed in a single cell portion C.

[0233] Referring to (a) of FIG. 34, a support 30 is prepared. Subsequently, after forming a patterned first insulating portion M1 on one surface of the support 30, etching EC may be performed on an exposed surface of the support 30 between the patterns of the first insulating portion M1.

[0234] Next, referring to (b) of FIG. 34, a trench portion TR recessed into the surface of the support 30 may be formed by etching EC. Subsequently, a patterned second insulating portion M2 may be formed on the upper surface of the support 30, except for the area where the trench portion TR is formed. The second insulating portion M2 may have a narrower width than the first insulating portion M1. The width of the second insulating portion M2 may correspond to the width of the aperture pattern P.

[0235] Next, referring to (c) of FIG. 34, electroforming may be performed on the support 30 to form a metal thin film portion 111 (111-1 and 111-2). A first metal thin film portion 111-1 may fill the trench portion TR, and a second metal thin film portion 111-2 may be formed further on top of the first metal thin film portion 111-1. The second metal thin film portion 111-2 may not be formed in the area where the second insulating portion M2 is disposed, and the area where the second insulating portion M2 is positioned may be provided as the aperture pattern P. The first and second metal thin film portions 111-1 and 111-2 may be formed simultaneously through the same process or individually through two separate processes.

[0236] The second metal thin film portion 111-2 may be electroformed with a wider width along both sides of the second insulating portion M2 than the first metal thin film portion 111-1. When considering only the metal thin film portion 111, the second metal thin film portion 111-2 has a shape where both sides protrude further. These protruding parts may be provided as cantilever portions CT, similar to the conductive cantilever portion CT described above with reference to FIGS. 24 to 25. In other words, based on the first metal thin film portion 111-1 with a first width corresponding to the width of the aperture pattern P and the second metal thin film portion 111-2 with a second width narrower than the first width, the portion of the second metal thin film portion 111-2 that protrudes further in the lateral direction than the first metal thin film portion 111-1 may be provided as the cantilever portion CT.

[0237] Meanwhile, the first and second metal thin film portions 111-1 and 111-2 may be formed using a method different from the steps shown in (c) to (c) of FIG. 34. Referring to (a) of FIG. 35, a first trench portion TR1 and a second trench portion TR2 may be formed on the support 30. The width of the second trench portion TR2 may be formed wider than that of the first trench portion TR1.

[0238] Next, referring to (b) of FIG. 35, electroforming may be performed on the support 30 to form a metal thin film portion 111 (111-1 and 111-2). A first metal thin film portion 111-1 may fill the first trench portion TR1, and a second metal thin film portion 111-2 may be formed while filling the second trench portion TR2 on the first metal thin film portion 111-1.

[0239] Meanwhile, after forming the metal thin film portion 111 shown in FIGS. 34 and 35, the heat treatment H process described above with reference to FIG. 29 and the planarization PS process described above with reference to FIG. 30 may be applied. Although the following description omits the connection portion 40 for convenience of explanation, if the heat treatment H process is performed, the connection portion 40 may be formed between the metal thin film portion 111 and the support 30.

[0240] Next, referring to FIG. 36, the support 30 may be subjected to etching EC2. The etching EC2 may be performed on a second surface (lower surface) opposite to the first surface (upper surface) of the support 30 to which the metal thin film portion 111 is connected. Once the etching EC2 of the support 30 exposed between the patterns of a third insulating portion M3 is completed, the support 30 may take the form of providing a hollow region R with only the edge portion remaining. As the central portion of the support 30 is etched to provide the hollow region R, a connected structure in which the metal thin film portion 111 and the holder portion 150 (30) are integrally connected may be provided.

[0241] Next, referring to FIG. 37, the insulating portion M3 may be removed, and an insulating layer portion 115 may be coated on the surface of the connected structure of the metal thin film portion 111 and the holder portion 150 (30). Subsequently, a conductive thin film layer 140 may be formed on the side surfaces of the aperture pattern P. Through this process, the manufacturing of a semiconductor test device 100 (100-8), in which the membrane portion 110 (110-9) with the insulating layer portion 115 coated on the surface of the metal thin film portion 111 is connected to the holder portion 150 and the conductive thin film layer 140 is formed in the aperture pattern P, may be completed.

[0242] Meanwhile, in the semiconductor test devices 100 (100-8 and 100-9) shown in FIGS. 33 and 37, instead of the conductive thin film layer 140, an electrical path portion 130 may be filled in the aperture pattern P to form an electrical connection path.

[0243] On the other hand, instead of forming a trench portion TR on the support 30, a patterned insulation portion (not shown) may be formed, and then electroforming may be performed on the support 30 to form the metal thin film portion 111 that includes a plurality of aperture patterns P. Subsequently, the support 30 may be etched to form a holder portion 150, and a conductive thin film layer 140 may be further formed on the insulating layer portion 115 and the side surfaces of the aperture patterns P to manufacture the semiconductor test device 100.

[0244] FIG. 38 is a cross-sectional microscopic photograph of a metal film formed by electroforming according to a comparative example. FIG. 39 is a cross-sectional microscopic photograph of a metal thin film portion formed by electroforming according to an embodiment of the present invention.

[0245] A comparative example in FIG. 38 shows a metal thin film formed on a conductive substrate by electroforming. It can be observed that the crystals of a plated film appear in a vertical direction or in a shape such as a column. From another perspective, it can also be seen that changes in composition of the plated film during the electroforming process occur along the vertical direction. This may be the result of a metal thin film forming crystals in a vertical direction from the surface of a conductive substrate when electroforming a thin film without an insulating portion such as PR. Alternatively, even with an insulating portion such as PR, this may be the result of the metal thin film forming crystals only in the vertical direction from the surface of the conductive substrate.

[0246] The embodiment of the present invention shown in FIG. 39 shows a metal thin film portion 111 formed by electroforming on a support 30 where a trench portion TR is formed through processes as shown in FIGS. 26 to 29 described above. Particularly, FIG. 39 shows an image of a body portion of the metal thin film portion 111 between adjacent aperture patterns P. Unlike the comparative example shown in FIG. 38, it can be observed that, in the present invention, the crystals of the metal thin film appear tilted at a predetermined angle to the vertical direction, rather than forming a vertical shape or a column-like shape. From another perspective, this may also be viewed as a change in composition of the metal thin film portion 111 (or the plated film) occurring through a combination of vertical and horizontal directions during the electroforming process.

[0247] Further comparisons will be described with reference to FIGS. 40 and 41 as follows.

[0248] FIG. 40 illustrates a schematic side cross-sectional view showing a metal film formed by electroforming according to the comparative example. FIG. 41 illustrates schematic side cross-sectional views showing a metal thin film portion formed by electroforming according to an embodiment of the present invention.

[0249] Referring to FIG. 40, the electroforming process according to the comparative example involves forming an insulating portion MP such as PR on a conductive substrate CP, and then forming a metal thin film MS (MS1 to MS3) through the spaces between the patterns of this insulating portion MP by electroforming. The metal thin film MS may be formed to a height slightly above the height of the insulating portion MP (e.g., MS1), to a height lower than the height of the insulating portion MP (e.g., MS2), or to a height exceeding the height of the insulating portion MP and covering the insulating portion MP (e.g., MS3).

[0250] What is common in the above three cases is that the mask metal film MS is electroformed, forming crystals in the vertical direction from the surface Sa of the conductive substrate CP exposed between the insulating portion MP patterns. Since the side surface Sb of the insulating portion MP is an insulator, it cannot serve as a starting point for electroforming. Ultimately, electroforming is performed only in the vertical direction from the exposed horizontal surface Sa of the conductive substrate CP that has conductive properties, and crystals may be formed.

[0251] Referring to (a) of FIG. 41, in the electroforming process according to the present invention, the surface of the support 30 is not formed only in the horizontal direction during electroforming, but due to the trench portion TR, not only the lower surface S1 but also the side surfaces S2 of the trench portion TR of the support 30 may serve as starting points for electroforming. Consequently, crystals may form through a combination of electroforming performed in the vertical (normal) direction from the lower surface S1 of the trench portion TR of the conductive substrate CP having conductive properties and electroforming performed in the vertical (normal) direction from the side surfaces S2 of the trench portion TR. In other words, the crystals may form while being influenced by forces in both the vertical and horizontal directions.

[0252] FIG. 42 is a cross-sectional microscopic photograph of a metal thin film portion formed on a support by electroforming according to an embodiment of the present invention. FIG. 42 corresponds to the cross-sectional microscopic photograph of (a) of FIG. 41.

[0253] Referring further to (a) of FIG. 41 and FIG. 42, the composition and crystal form may vary across different regions Z1, Z2, and Z3 of a metal thin film portion 111. As described above with reference to FIG. 28, the metal thin film portion 111 may be plated to form two layers with different compositions by adjusting a current density. In addition to this method, in the present invention, the composition and crystal form may vary across different regions Z1, Z2, and Z3 due to the structural factors involved in forming the trench portion TR.

[0254] The first region Z1 corresponds to a first surface S1, which is the lower surface of the metal thin film portion 111 (or the lower surface of the trench portion TR). The first region Z1 may be significantly influenced by the characteristics of electroforming that starts from the first surface S1. The crystal shape in this region may be more influenced by a force in the vertical direction than in the horizontal direction.

[0255] The second region Z2 may be influenced by the characteristics of electroforming that starts from both the first surface S1 and the second surfaces S2, which are the side surfaces of the aperture pattern P (or the side surfaces of the trench portion TR). As a result, the crystal shape in this region may be influenced by a combination of forces in both the vertical and horizontal directions.

[0256] The third region Z3 corresponds to the upper surface of the metal thin film portion 111 where the insulating portion M1 may be disposed. The third region Z3 cannot serve as a starting point for electroforming due to the insulating portion M1 (such as silicon oxide, PR, etc.). Accordingly, crystals may be formed by a combination of forces in the vertical and horizontal directions, continuing from the electroforming process in the second region Z2, but due to a greater distance from the starting point of the electroforming than the second region Z2, the form of the forces may be different.

[0257] Ultimately, the compositions of the first surface S1, which is the lower surface of the metal thin film portion 111, and the second surface S2, which is the side surface of the aperture pattern P, may differ from the composition of a third surface S3, which is the upper surface of the metal thin film portion 111.

[0258] Meanwhile, referring to (b) of FIG. 41, the metal thin film portion 111 may be provided by performing planarization PS after heat treatment H of the metal thin film portion 111, or by performing heat treatment of the metal thin film portion 111 after planarization PS (see FIGS. 29 and 30). Subsequently, the third surface S3 may become the upper surface of the aperture pattern P (or the upper surface of the metal thin film portion 111) through etching EC2 of the support 30 (see FIG. 31).

[0259] FIG. 43 is a planar microscopic photograph of the metal thin film portion after a planarization process according to an embodiment of the present invention. FIG. 42 shows the plane of the metal thin film portion after performing planarization PS in FIG. 42.

[0260] In the heat treatment H process, a magnetic domain may be formed as crystals within the metal thin film portion 111 grow. Referring to FIGS. 42 and 43, it can be observed that irregular shapes in dark gray/light gray appear on the metal thin film portion 111. These dark gray/light gray shapes may correspond to the magnetic domains.

[0261] FIGS. 44 and 45 illustrate the line data and composition in the depth direction of the metal thin film portion formed on a support by electroforming, according to an embodiment of the present invention.

[0262] Composition analysis was performed in the direction from the surface of the metal thin film portion to the lower portion, as shown by the line data direction in FIG. 44. In FIG. 45, the X-axis represents the distance moved downward by 4 m from the surface of the mask (starting at 0), and the Y-axis represents the amount of a component. Referring to (c) of FIG. 45, from approximately 2.6 m, the amount of Si increases sharply. Therefore, it can be confirmed that the thickness of the metal thin film portion 111 formed in the trench portion TR is approximately 2.6 m from the upper surface to the lower surface, and beyond 2.6 m, a support 30 of a silicon wafer material appears.

[0263] In addition, referring to (a) of FIG. 45, it can be seen that the amount of Ni increases sharply around 2.6 m. That is, in a part represented by the dotted ellipse in (a) and (b) of FIG. 45, it can be confirmed that the proportion of Ni is relatively higher than in other parts. In other words, this confirms that the composition near the first surface S1, which is the lower surface of the metal thin film portion 111, is Ni-rich compared to the composition near the third surface S3, which is the upper surface of the metal thin film portion 111. Similarly, not only the first surface S1 but also the second surface S2, which is the starting surface of electroforming, may have a Ni-rich composition compared to the third surface S3. The metal thin film MS formed according to the comparative example described with reference to FIG. 40 is Ni-rich only at the lower surface, and is thus distinguishable from the metal thin film portion 111 of the present invention.

[0264] FIG. 46 is an enlarged schematic side cross-sectional view of area I in (b) of FIG. 41, showing the crystal shape of the metal thin film portion before and after the planarization process according to an embodiment of the present invention. FIG. 47 is a planar microscopic photograph of the metal thin film portion after a planarization process according to an embodiment of the present invention. (a) of FIG. 47 shows a Z-axis height difference map (Z-axis step map) observed in AFM mode at 100 to 100 nm, and (b) of FIG. 47 shows a magnetic domain map observed in MFM mode at 10 to 2.5 deg.

[0265] Referring to (a) of FIG. 46, as described above with reference to FIG. 42, magnetic domains GR may be formed as crystals within the metal thin film portion 111 grow during the heat process H. That is, the presence of magnetic domains GR is a result of the heat treatment of the metal thin film portion 111 and may distinguish the metal thin film portion from a plated film formed by ordinary electroforming alone. Additionally, the present invention may perform a planarization PS process after heat treatment H.

[0266] Referring to (b) of FIG. 46, as the upper portion of the metal thin film portion 111 becomes flat due to the planarization PS process, the magnetic domains GR on the upper surface (the third surface S3) of the metal thin film portion 111 may also have a flat upper shape. Specifically, magnetic domains typically have irregular three-dimensional shapes, but as the upper portion becomes flat, they may have a three-dimensional shape that includes at least one horizontal side surface. The surface roughness Ra of the upper portion of the metal thin film portion 111 may also be controlled after the planarization PS process. The surface of the upper portion of the metal thin film portion 111 may have high roughness due to fine irregularities resulting from electroforming and heat treatment. However, after the planarization PS process, such as polishing, the surface roughness Ra may be reduced. Preferably, the surface roughness Ra may be less than 0.1 m, and the surface roughness Rz may be less than 1.0 m.

[0267] Referring to FIG. 47, magnetic domains GR may be observed on the surface of the upper portion of the metal thin film portion 111. The size of the magnetic domains GR is on the scale of several micrometers, preferably around 1 m, and can be observed depending on the grain size and orientation.

[0268] In addition, patterns such as ripples, stripes, and wrinkles may be observed in the magnetic domains GR, which appear to indicate the formation of patterns during the process where crystals with N and S poles are created by electroforming.

[0269] As described above, the present invention may provide a semiconductor test device capable of performing a test by contacting micro bumps of a semiconductor device and a manufacturing method thereof, and has the effect of preventing damage to the micro bumps and enabling precise alignment during connection.

[0270] According to the present invention configured as described above, there is an effect in a test can be performed by contacting micro bumps of a semiconductor device.

[0271] Additionally, according to the present invention, there is an effect of preventing damage to the micro bumps and enabling precise alignment during connection.

[0272] However, the scope of the present invention is not limited by the above effects.

[0273] While the present invention has been particularly shown and described with reference to embodiments thereof, it will be understood by one of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the present invention as defined by the following claims.

REFERENCE NUMERALS

[0274] 10: SEMICONDUCTOR DEVICE [0275] 13: INTERPOSER [0276] 15: SECOND SEMICONDUCTOR PACKAGE, STACKED SEMICONDUCTOR MEMORY [0277] 30: SUPPORT, CONDUCTIVE SUBSTRATE [0278] 40: CONNECTION PORTION [0279] 100: SEMICONDUCTOR TEST DEVICE [0280] 110: MEMBRANE PORTION [0281] 111: METAL THIN FILM PORTION [0282] 115: INSULATING LAYER PORTION [0283] 130: ELECTRICAL PATH PORTION [0284] 140: CONDUCTIVE THIN FILM LAYER [0285] 150: HOLDER PORTION [0286] CT: CANTILEVER PORTION [0287] MB, MB2: MICRO BUMP [0288] P: APERTURE PATTERN [0289] R: HOLLOW REGION [0290] TR: TRENCH PORTION