RESISTANCE NETWORK HAVING FOUR CONTACTS PER MEMORY CELL

Abstract

A resistor network and an integrated circuit at least part of the resistor network may have at least two memory cells for storing in each case one resistance characteristic value. Each memory cell may have a first contact pair configured to provide an electrical resistance corresponding to the stored resistance characteristic value in at least one operating mode. First contacts of the respective first contact pair of the two memory cells are directly connected to one another and second contacts of the respective first contact pair of the two memory cells are electrically independent of one another. The memory cells may each have a second contact pair which is electrically independent of the first contact pair and which is arranged in such a way that the stored electrical resistance characteristic value of the respective memory cell can be reversibly changed by suitable electrical signals via this second contact pair.

Claims

1-12 (canceled)

13. A resistor network having at least two memory cells for storing in each case one resistance characteristic value, which each have a first contact pair which is configured to provide an electrical resistance corresponding to the stored resistance characteristic value in at least one operating mode, wherein first contacts of the respective first contact pair of the two memory cells are directly connected to one another and second contacts of the respective first contact pair of the two memory cells are electrically independent of one another, characterized in that the memory cells each have a second contact pair which is electrically independent of the first contact pair and which is arranged in such a way that the stored electrical resistance characteristic value of the respective memory cell can be reversibly changed by suitable electrical signals via this second contact pair.

14. The resistor network according to claim 13, wherein first contacts of the respective second contact pair of the two memory cells are directly connected to each other and second contacts of the respective second contact pair of the two memory cells are independent of each other.

15. The resistor network according to claim 13, wherein at least one third memory cell for storing a resistance characteristic value, comprising a first contact pair configured to provide an electrical resistance corresponding to the stored resistance characteristic value, wherein a first contact of the first contact pair of the third memory cell is independent of the first contacts of the first contact pair of the two memory cells and wherein a second contact of the first contact pair of the third memory cell is directly connected to the second contact of the first contact pair of one of the two memory cells and is independent of the second contact of the first contact pair of the other of the two memory cells.

16. The resistor network according to claim 13, wherein at least one of the memory cells comprises at least one transistor configured as a ferroelectric field effect transistor.

17. The resistor network according to claim 16, wherein the first contact pair is connected to a source electrode and a drain electrode of the transistor.

18. The resistor network according to claim 16, wherein the second contact pair is connected to a front gate electrode of the transistor and a back gate electrode of the transistor.

19. The resistor network according to claim 13, wherein the memory cells are each configured to either provide or block the electrical resistance corresponding to the stored resistance characteristic value via the first contact pair depending on a voltage applied across the second contact pair.

20. The resistor network according to claim 13, wherein at least the two memory cells are each configured to be switchable between at least three different memory states by suitable electrical signals via the respective second contact pair.

21. The resistor network according to claim 13, wherein a plurality of further memory cells for storing resistance characteristics, each having a first contact pair configured to provide an electrical resistance corresponding to the stored resistance characteristic value in at least one operating mode and being arranged together with the two memory cells in rows and columns of a grid.

22. An integrated circuit, comprising an analog convolutional neural network layer or an analog matrix multiplier, said circuit comprising at least one resistor network according to claim 13.

23. The integrated circuit according to claim 22, wherein a first selection unit respectively connected to the first contacts of the second contact pair of the memory cells (200) and adapted to connect a subset of the first contacts to a first activation contact and to connect a complementary set of the first contacts to a first deactivation contact in response to a specification.

24. The integrated circuit according to claim 22, further comprising at least one temperature sensor configured to monitor a temperature of the resistor network, and at least one actuator configured to adapt stored resistance characteristic values of the memory cells of the resistor network to a changed temperature.

Description

[0056] Examples of embodiments of the invention are shown in the drawings and are explained in more detail below with reference to FIGS. 1 to 8. Shown are:

[0057] FIG. 1 a schematic representation of a section of a resistor network with memory cells;

[0058] FIG. 2 an embodiment of a memory cell of a resistor network;

[0059] FIG. 3 an alternative embodiment of a memory cell of a resistor network;

[0060] FIG. 4a)-c) characteristics of a memory cell of a resistor network;

[0061] FIG. 5 a schematic 3D representation of an implementation of a resistor network;

[0062] FIG. 6 a first sectional view through the resistor network along a sectional plane A in FIG. 5;

[0063] FIG. 7 a second sectional view through the resistor network along a sectional plane B in FIG. 5; and

[0064] FIG. 8 a schematic diagram of an integrated circuit with a resistor network.

[0065] FIG. 1 shows a section of a resistor network 100 having a plurality of memory cells 200. The section includes nine memory cells 200, each for storing a resistance characteristic value. The memory cells 200 each include a first contact pair configured to provide an electrical resistance corresponding to the stored resistance characteristic value in at least one operating mode.

[0066] The memory cells 200 are arranged in a grid. The grid has 32 rows and 32 columns, and alternatively networks of any size are possible. The grid of the shown section has 3 rows and 3 columns.

[0067] First contacts 104a or 104b or 104c of the first contact pair of the memory cells 200a, 200d, 200g, or 200b, 200e, 200h, or 200c, 200f, 200i, respectively, arranged in a same row are connected to each other, respectively. The first contacts 104a, 104b, 104c each form an input contact of an input contact group 105.

[0068] Second contacts 106a or 106b or 106c of the first contact pair of the memory cells 200a, 200d, 200g, or 200b, 200e, 200h, or 200c, 200f, 200i, respectively, arranged in a same row are electrically independent of each other, respectively.

[0069] The memory cells 200 each include a second contact pair that are electrically independent of the first contact pair. The second contact pair is arranged in such a way that the stored electrical resistance characteristic value of the respective memory cell 200 can be reversibly changed via this by means of suitable electrical signals.

[0070] First contacts 108a and 108b and 108c, respectively, of the second contact pair of the memory cells 200a, 200d, 200g, and 200b, 200e, 200h, and 200c, 200f, 200i, respectively, which are arranged in a same row, are connected to each other, respectively. The first contacts 108a, 108b, 108c each form a selection input of a selection input group 110.

[0071] Second contacts 109a or 109b or 109c of the second contact pair of the memory cells 200a, 200d, 200g, or 200b, 200e, 200h, or 200c, 200f, 200i, respectively, which are arranged in a same row, are electrically independent of each other, respectively. The second contacts 109a, 109b, 109c each form a selection output of a selection output group 120.

[0072] First contacts 104a or 104b or 104c of the first contact pair of the memory cells 200a, 200b, 200c, or 200d, 200e, 200f, or 200g, 200h, 200i, respectively, arranged in a same column are electrically independent of each other, respectively. The first contacts 104a, 104b, 104c each form an output contact of an input contact group 105.

[0073] Second contacts 106a or 106b or 106c of the first contact pair of the memory cells 200a, 200b, 200c, or 200d, 200e, 200f, or 200g, 200h, 200i, which are arranged in a same row, are respectively connected to each other. The second contacts 106a, 106b, 106c each form an output contact of an output contact group 107.

[0074] First contacts 108a and 108b and 108c, respectively, of the second contact pair of the memory cells 200a, 200b, 200c, and 200d, 200e, 200f, and 200g, 200h, 200i, respectively, which are arranged in a same column, are electrically independent of each other, respectively.

[0075] Second contacts 109a or 109b or 109c of the second contact pair of the memory cells 200a, 200b, 200c, or 200d, 200e, 200f, or 200g, 200h, 200i, which are arranged in a same row, are respectively connected to each other. The first contacts 109a, 109b, 109c each form a selection input of a selection input group 110.

[0076] The memory cells 200 are each configured to either provide or block the electrical resistance corresponding to the stored resistance characteristic across the first contact pair, depending on a voltage applied across the second contact pair.

[0077] FIG. 2 shows an electrical diagram of the memory cells 200 of the resistor network 100. The memory cells 200 each have a transistor 201 formed as a ferroelectric field effect transistor (FeFET). Recurring elements are provided with identical reference numerals in this Figure and also in the following figures. A back-gate electrode of the transistor 201 forms the first contact 108 of the second contact pair of the memory cell 200. A front gate electrode of the transistor 201 forms the second contact 109 of the second contact pair of the memory cell 200. Source and drain electrodes of transistor 201 form first and second contacts 104, 106 of the first contact pair, respectively. The first contact pair 104 and 106 or 104a and 106a, respectively, is thus connected to a source region or a drain region of the transistor 201, which is part of one of the memory cells 200 and may be a logic transistor or a memory transistor. Accordingly, the second contact pair 108 and 109 or 108a and 109 a is connected to the gate region or the bulk region of this transistor 201. In addition, a resistor or a capacitor, typically a ferroelectric capacitor, may be connected in series, as shown below in FIG. 3. The gate area and the bulk area or the gate line or gateline and the bulk line or bulkline are routed parallel to each other.

[0078] According to an alternative embodiment, the transistor 201 is formed by a charge-trap transistor instead of a ferroelectric field effect transistor. In principle, the transistor 201 may be configured as a non-volatile transistor or non-volatile memory transistor.

[0079] FIG. 3 illustrates an electrical diagram of an alternative embodiment of the memory cells 200. In this case, the memory cell 200 has a transistor 201 configured as a field-effect transistor. Further, the memory cell 200 includes a ferroelectric capacitance 203 electrically arranged or connected between the front-gate electrode of the transistor 201 and the second contact 109 of the second contact pair, or connected in series. A back-gate electrode of the transistor 201 forms the first contact 108 of the second contact pair of the memory cell 200. Source and drain electrodes of transistor 201 form first and second contacts 104, 106 of the first contact pair, respectively. Alternatively, it is also possible that the ferroelectric capacitance is arranged between the back-gate electrode of the transistor 201 and the first contact of the second contact pair.

[0080] In FIG. 4, an upper diagram a) and a middle diagram b) show a set of characteristics of the memory cells 200, which are designed as ferroelectric field-effect transistors. A source-drain current I.sub.d is plotted here as a function of a gate-bulk voltage V.sub.g for different memory states of memory cell 200. The variable resistance parameter here is the electrical polarization of the ferroelectric material. Using suitable electrical signals across the second contact pair, the memory cell 200 can be switched between a plurality of values over a quasi-continuous spectrum. The signals for changing the stored resistance characteristic value are designed as pulses or pulse sequences. How much the resistance characteristic value changes due to a pulse depends in particular on the pulse amplitude, the pulse duration and the pulse frequency. For example, in the bottom diagram c), the source-drain current Id across the memory cell 200 is shown as a function of a number N of pulses performed. Diagrams a) and b) differ in that the pulses have a reversed polarity and thus (with each further pulse) the resistance parameter and thus the characteristic curve changes in a different direction. A signal pulse or signal pulse sequence can be used to change the state of the FeFET stepwise from one extreme state to another. The amplitude of this pulse is greater than the read voltage of the FeFET. Furthermore, there are several possibilities for this pulse sequence. Three exemplary possibilities are the repeated sequence of the same pulses, repeated sequence when the pulse width changes, and repeated sequence when the pulse amplitude changes.

[0081] When using a ferroelectric field effect transistor (FeFET), the activation and deactivation potentials (voltages) in the resistor network can be determined starting from the two extreme states, each of which is characterized by rectified polarization along the gate stack. The activation or read voltage of the sourcelines (difference between the first and second activation potential) should be in the range where the difference of the transfer characteristics of the two states is large (i.e. in the given example of FIG. 4 about 0.5V), but at the same time this voltage should be chosen as low as possible to avoid disturbing the state of this memory cell or other memory cells.

[0082] The deactivation voltage of the bulk or sourcelines should be selected in a range where the current of both transfer characteristics is low or negligible. At the same time, the voltage should be chosen as close as possible to the read voltage to avoid disturbing the states by an increased voltage in areas where both source and bulk lines see the deactivation voltage. Furthermore, it should be noted that in the case of bulk lines, a large part of the voltage does not drop to the transistor. Thus, the deactivation voltage must be selected so that the voltage dropping across the transistor is sufficient for deactivation. If it is not possible to carry such a high voltage across the bulk lines in the selected technology node, this can be compensated for by a bias voltage, which is applied to both the source lines and bulk lines. It should be noted that the bias voltage of the source and bulk lines is different and should be selected so that the voltage that is dropped across the transistor does not change.

[0083] FIG. 5 shows a schematic three-dimensional representation of the topology of an implementation of a resistor network according to the invention on a semiconductor substrate 202. Here, the semiconductor substrate 202 is divided into columns by shallow trenches 231a, 231b and into rows by deep trenches 230a, 230b, 230c. The deep trenches 230a, 230b, 230c are formed as double trenches so that each row is surrounded by its own pair of deep trenches 230a, 230b, 230c. In each cell region corresponding to a row-and-column combination, a memory cell 200a, 200b, 200c, 200d, 200e, 200f is formed in and on the semiconductor substrate 202. The cell areas here each have a size of about 300 nm by 300 nm. In each cell region, a front-gate insulation of ferroelectric dielectric 210a, 210d is deposited on the semiconductor substrate 202 between and partially over two similarly doped source/drain regions 204a, 206a and 204d, 296b of the cell region, respectively (see FIGS. 6 and 7). Since the source and drain of an FET are topologically interchangeable, in this description areas that can function as source or drain areas are referred to as source/drain areas—it is assumed here that an FET has two source/drain areas, and that one of these areas ultimately serves as the source and another as the drain.

[0084] The front gate insulators of the memory cells 200a, 200b, 200c or 200d, 200e, 200f of a same column are each arranged to contact front gate electrodes disposed thereon by means of a first rectilinear conductor path in a first conductor layer plane and vias. The first conductor path, together with the front gate electrode and the vias, respectively form the second contact 109a and 109b of the second contact pair. First source/drain regions 204a of memory cells 200a, 200b, 200c and 200d, 200e, 200f, respectively, arranged in the same column are each contacted by a second rectilinear conductor path and vias per column. The second conductor path is parallel to the first conductor track and in the first conductor layer plane, or alternatively in a further conductor layer plane. Second source/drain regions 206a, 206d of memory cells 200a, 200d, or 200b, 200e, or 200c, 200f, respectively, arranged in a same row are contacted by a third rectilinear conductor path and vias, respectively, per row. The third conductor paths are orthogonally skewed to the first conductor paths in a second conductor layer plane. The third conductor paths are orthogonally skewed to the second conductor paths. The first, second and third conductor paths form a cross-bar array.

[0085] The semiconductor substrate 202 has a basic doping 208a, 208b, 208c between each of the deep trenches 230a, 230b, 230c of a row. The basic doping 208a, 208b, 208c extends across under shallow trenches 231a, 231b. The basic doping 208a, 208b, 208c of a row forms a back-gate contact of the transistor for each memory cell 200a, 200d, or 200b, 200e, or 200c, 200f of the row, respectively. The basic doping 208a, 208b, 208c is interrupted by the deep trenches 230a, 230b, 230c so that the basic dopings 208a, 208b, 208c of the different rows are electrically isolated from each other. The deep trenches 230a, 230b, 230c extend slightly deeper into the semiconductor substrate 202 than the basic doping 208a, 208b, 208c. In addition, the semiconductor substrate 202 is undoped in a region between the deep trenches 230a, 230b, 230c of different rows or, alternatively, doped in the opposite direction to the basic doping 208a, 208b, 208c. Instead of double trenches, it is alternatively possible for the deep trenches to extend significantly further into the substrate than the basic doping 208a, 208b, 208c.

[0086] At one edge of the grid, the basic doping 208a, 208b, 208c of each row is respectively contacted via front-side electrodes with fourth conductor paths guided in the first or alternatively in the second or alternatively the further conductor paths in the conductor layer plane by means of vias. The fourth conductor paths respectively form the first contact 108a, or 108b, or 108c of the second contact pair of the memory cells 200a, 200d, or 200b, 200e, or 200c, 200f.

[0087] As indicated in FIG. 6, a first sectional view of the topology of the resistor network along sectional plane A, the basic doping 208a, 208b, 208c is also separated from the rest of the semiconductor substrate 202 by a deep trench 230a, 230b, 230c at the beginning and end of each row. The basic doping 208a, 208b, 208c is surrounded by the deep trench 230a, 230b, 230c. Further, as indicated in FIG. 6, an additional shallow trench may be provided between a contact surface of the back-gate contact and a contact surface of the first source/drain region 204a. Regardless of the fact that only two memory cells are shown in one row in FIG. 6, any number of memory cells can be provided per row. The basic doping 208a, 208b, 208c extends correspondingly far (to the left) without being interrupted by deep trenches.

[0088] Another sectional view of the topology of the resistor network along the sectional plane B is shown in FIG. 7.

[0089] FIG. 8 shows an integrated circuit 300 according to the invention, in particular an analog convolutional neural network layer or an analog matrix multiplier, with a resistor network 100 according to the invention.

[0090] The integrated circuit 300 includes a first selection unit 310 connected to each of the first contacts 108 of the second contact pair of the memory cells 200, and configured to connect, depending on a specification 342, a subset of the first contacts 108 to a first activation contact and to connect a complementary set of the first contacts 108 to a first deactivation contact.

[0091] The integrated circuit 300 includes a second selection unit 320 connected to each of the second contacts 109 of the second contact pair of the memory cells 200, and configured to connect, depending on the specification 342, a subset of the second contacts 109 to a second activation contact and to connect a complementary set of the second contacts 109 to a second deactivation contact.

[0092] The integrated circuit 300 includes an actuator unit 340 configured to generate specifications 342 for the selection units 310, 320. The actuator 340 is configured to generate electrical signals which are transmitted by means of the selection units 310, 320 to specific ones of the memory cells 200 of the resistor network 100 (i.e., to individual ones or also to all of them) to second contacts 108, 109 of the memory cells 200 in order to change a respective stored resistor characteristic value or memory state of the memory cells 200. The actuator unit 340 is configured to provide different potentials that are directed to the second contact pair of the memory cells 200 by means of the first and second activation and deactivation contacts of the selection units 310, 320.

[0093] For example, each selection input of the resistor network 100 may be connected to the first activation contact to provide an activation potential to the first contacts 108 of the second contact pair, and each selection output of the resistor network 100 may be connected to the second activation contact to provide an activation potential (e.g., a ground potential or a comparison potential (bias)) to the second contacts 109 of the second contact pair such that all memory cells 200 of the resistor network 100 are active. If an input signal 350 (input signal) is now applied via each of the input contacts (bitlines), an output signal 352 can be taken from all output contacts. The states of the memory elements are retained (i.e. are not lost).

[0094] In another operating embodiment, it is possible for the memory cells 200 of selected columns to be deactivated. For example, if only the memory cells 200g, 200h, 200i of the third column are to be deactivated, the associated second contacts 109c of the second contact pair (i.e., the third selection output) are connected to the second deactivation contact and thus to a second deactivation potential by means of the second selection unit 320, while the associated second contacts 109a, 109b of the remaining memory cells 200a, 200b, 200c, and 200d, 200e, 200f are connected to the second activation contact. If an input signal 350 is now applied to each of the input contacts, a third output contact (wordline) remains without a signal regardless of resistance characteristics values stored in memory cells 200 because memory cells 200a, 200b, 200c of the third column are blocked. Similarly, it is possible to deactivate multiple columns of the resistor network 100 by connecting the corresponding associated bulk lines to the second deactivation potential. The states of the memory elements are retained (i.e. are not lost).

[0095] Further, it is possible for memory cells 200 of selected rows to be deactivated. For example, if the memory cells 200c, 200f, 200i of the third row are to be deactivated, the associated first contacts 108c of the respective second contact pair (i.e., the third selection input) are connected to the first deactivation contact and thus to a first deactivation potential by means of the first selection unit 310, while the associated first contacts 108a, 108b of the remaining memory cells 200a, 200d, 200g and 200b, 200e, 200h are connected to the first activation contact. If input signals 350 are now applied to all input contacts, the output signals 352 at the output contacts (regardless of the resistance characteristic values stored in the memory cells 200) remain independent of an input signal 350 at the third input contact because the memory cells 200a, 200d, 200g of the third row are blocked. Similarly, it is possible to deactivate multiple rows of the resistor network 100 by applying the corresponding associated source lines to the first deactivation potential. The states of the memory elements are retained (i.e. are not lost).

[0096] Further, it is possible for multiple rows and or multiple columns to be deactivated simultaneously so that only portions, up to and including individual memory cells 200, of the resistor network 100 are active. In this way, it is possible to read out individual memory cells 200. To control a selected contiguous area in the resistor network, the respective deactivation voltage (deactivation potential) of the source lines or bulk lines can be applied to all lines that are not required. The remaining resistor network can be operated independently of the other lines like a stand-alone network. The states of the memory elements that are switched off are retained, i.e. they are not lost. To read out the state of an individual memory cell, the respective activation voltage is applied to the source or bulk line connected to the memory element. All other lines are connected to the associated deactivation voltages (deactivation potentials). By applying a readout or input signal to the associated bitline of the memory element (memory cell), the output signal can be read out at the connected wordline and compared with the state that can be assigned to it. In the analog case, instead of the activation voltage of the sourceline, the signal for changing the memory state can also be given in the form of a pulse. This makes it possible to change the state of a single memory element without causing interference to the other memory elements.

[0097] The integrated circuit 300 includes a temperature sensor 344 configured to monitor a temperature of the resistor network 100. The actuator 340 is configured to adapt stored resistance characteristic values of the memory cells 200 of the resistor network 100 to a changed temperature.

[0098] The actuator 340 has a cycle counter 346 and a refresh unit 348. Here, the cycle counter 346 monitors how many input signals have been routed through the input contact group 105 and the resistor network 100. The refresh unit 346 is configured to clear the resistor network 100 and reset the stored values of the memory cells 200 (weight values) after a predetermined/presettable number of input signals has been reached.

[0099] The resistor network 100 weights the input signals 350 according to the electrical resistances or weights provided by the memory cells 200, and combines them according to a matrix multiplication to produce output signals 352.

[0100] Weights of the memory cells 200 are set by the actuator 340 based on external specifications 345.

[0101] Further, the integrated circuit 300 includes a digital-to-analog converter 351 configured to convert digital input signals 350 to analog input signals and pass them to the input contact group 105.

[0102] Further, the integrated circuit 300 includes an analog-to-digital converter 353 configured to convert the analog output signals at the contacts of the output contact group 107 into digital output signals 352.

[0103] Depending on the application, converters 351, 353 can also be omitted.

[0104] Read and write accesses are therefore completely separate from each other. The first contact pairs are used for reading, i.e. the analog calculation of the vector-matrix multiplication or convolution operation. The second contact pairs are used for writing the resistance values or the weight values. In addition, the second contact pairs are used for selective deactivation/activation of the respective memory element.

[0105] The project that led to this application was funded by the ECSEL Joint Undertaking (JU) under Grant Agreement No. 826655. JU receives support from the European Union's Horizon 2020 research and innovation program and from Belgium, France, Germany, the Netherlands and Switzerland.