EDGE COMBINERS WITH SYMMETRICAL OPERATION RANGE AT HIGH SPEED

Abstract

Edge combiners with symmetrical operation range at high speed are provided. In certain embodiments, an edge combiner (80) includes a circuit state element (71) having a first input controlled by a first timing signal (SI), and a pulse generator (72) that resets the circuit state element by controlling a second input (R) of the circuit state element based on a second timing signal (S2). The edge combiner further includes a first delay circuit (75), and an output logic gate (77) having a first input connected to a data output (Q) of the circuit state element through a first signal path that bypasses the first delay circuit (75), a second input (QD) connected to the data output through a second signal path that includes the first delay circuit, and an output (OUT) that provides an output signal indicating delay between an edge of the first timing signal and an edge of the second timing signal.

Claims

1-20. (canceled)

21. An edge combiner with symmetrical operation range, the edge combiner comprising: a circuit state element including a first input controlled by a first timing signal, a second input, and a data output; a first pulse generator configured to reset the circuit state element based on a second timing signal; a first delay circuit; and an output logic circuit including a first input connected to the data output of the circuit state element through a first signal path that bypasses the first delay circuit, a second input connected to the data output of the circuit state element through a second signal path that includes the first delay circuit, and an output configured to generate an output signal indicating a delay between an edge of the first timing signal and an edge of the second timing signal.

22. The edge combiner of claim 21, further comprising a second delay circuit including an input that receives the first timing signal and an output that provides a delayed version of the first timing signal to the first input of the circuit state element.

23. The edge combiner of claim 21, wherein the output logic circuit is a two input logic gate.

24. The edge combiner of claim 21, further comprising a feedback path configured to control a pulse width of the first pulse generator based on timing of the output signal.

25. The edge combiner of claim 21, wherein a pulse width of the first pulse generator is based on a time delay from the edge of the second timing signal.

26. The edge combiner of claim 21, wherein the edge of the first timing signal and the edge of the second timing signal are each one of a rising edge or a falling edge.

27. The edge combiner of claim 21, wherein the circuit state element includes a d-type flip-flop.

28. The edge combiner of claim 27, wherein the d-type flip-flop includes a data input connected to a fixed voltage, wherein the first input of the d-type flip-flop corresponds to a clock input and the second input of the d-type flip-flop corresponds to a reset input.

29. The edge combiner of claim 21, wherein the circuit state element includes a set-reset latch.

30. The edge combiner of claim 29, wherein the first input of the set-reset latch corresponds to a set input, and the second input of the set-reset latch corresponds to a reset input.

31. The edge combiner of claim 29, further comprising a second pulse generator configured to control the first input based on the first timing signal.

32. A method of edge combining in an electronic timing system, the method comprising: controlling a first input of a circuit state element based on a first timing signal; resetting the circuit state element by controlling a second input of the circuit state element with a pulse generator that receives a second timing signal; delaying a data output signal from a data output of the circuit state element to generate a delayed data output signal using a first delay circuit; and generating an output signal indicating a delay between an edge of the first timing signal and an edge of the second timing signal using an output logic circuit that receives the data output signal and the delayed data output signal.

33. The method of claim 32, further comprising delaying the first timing signal to the first input of the circuit state element using a second delay circuit.

34. The method of claim 32, wherein generating the output signal includes processing the data output signal and the delayed data output signal using a two input logic gate.

35. The method of claim 32, further comprising controlling a pulse width of the pulse generator based on timing of the output signal.

36. The method of claim 32, further comprising controlling a pulse width of the pulse generator based on a time delay from the edge of the second timing signal.

37. A time of flight system comprising: an edge combiner comprising: a circuit state element including a first input controlled by a first timing signal, a second input, and a data output; a pulse generator configured to reset the circuit state element based on a second timing signal; a first delay circuit; and an output logic circuit including a first input connected to the data output of the circuit state element through a first signal path that bypasses the first delay circuit, a second input connected to the data output of the circuit state element through a second signal path that includes the first delay circuit, and an output configured to generate an output signal indicating a delay between an edge of the first timing signal and an edge of the second timing signal; and a driver circuit configured to control an emission of light from a light emitting element based on the output signal.

38. The time of flight system of claim 37, further comprising a first delay locked loop (DLL) configured to generate the first timing signal and a second DLL configured to generate the second timing signal.

39. The time of flight system of claim 37, wherein the edge combiner further comprises a second delay circuit including an input that receives the first timing signal and an output that provides a delayed version of the first timing signal to the first input of the circuit state element.

40. The time of flight system of claim 37, wherein the circuit state element corresponds to one of a flip-flop or a latch.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1A is a schematic diagram of a time of flight system according to one embodiment.

[0009] FIG. 1B is one example of a timing diagram for the time of flight system of FIG. 1A.

[0010] FIG. 1C is a schematic diagram of a time of flight system according to another embodiment.

[0011] FIG. 1D is one example of a timing diagram for the time of flight system of FIG. 1C.

[0012] FIG. 1E is another example of a timing diagram for the time of flight system of FIG. 1C.

[0013] FIG. 2A is a schematic diagram of an example implementation of an edge combiner.

[0014] FIG. 2B is one example of a timing diagram for the edge combiner of FIG. 2A.

[0015] FIG. 3A is a first example of an operation range timing diagram for the edge combiner of FIG. 2A.

[0016] FIG. 3B is a second example of an operation range timing diagram for the edge combiner of FIG. 2A.

[0017] FIG. 4A is a schematic diagram of one embodiment of an edge combiner.

[0018] FIG. 4B is one example of a timing diagram for the edge combiner of FIG. 4A.

[0019] FIG. 4C is a schematic diagram of another embodiment of an edge combiner.

[0020] FIG. 4D is a schematic diagram of another embodiment of an edge combiner.

[0021] FIG. 5A is a first example of an operation range timing diagram for the edge combiner of FIG. 4A.

[0022] FIG. 5B is a second example of an operation range timing diagram for the edge combiner of FIG. 4A.

[0023] FIG. 6 is a schematic diagram of another embodiment of an edge combiner.

DETAILED DESCRIPTION

[0024] The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways. In this description, reference is made to the drawings where like reference numerals may indicate identical or functionally similar elements. It will be understood that elements illustrated in the figures are not necessarily drawn to scale. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and/or a subset of the elements illustrated in a drawing. Further, some embodiments can incorporate any suitable combination of features from two or more drawings.

[0025] An edge combining function is often necessary in clocking or timing systems. Depending on the application and the nature of the input timing signals, various digital logic circuitry could perform an edge combining function with some limitations.

[0026] To enable edge combining, an edge combiner can include a pulse generator that operates in combination with a circuit state element, such as a flip-flop or latch. Although using a pulse generator helps achieve edge combining functionality, inclusion of the pulse generator can result in one side of the edge combiner's operation range being narrower than the other side.

[0027] To ensure a large enough operation range for the narrower side, the pulse generator's pulse width can be reduced. However, reducing pulse width extends the wider operation range unnecessarily, while also imposing a significant risk of circuit malfunction due to pulses generated for the circuit state element being too narrow. Such malfunction is a particular risk in a very harsh and noisy environment, for instance, a laser diode driver application in which amperes (amps) of current could be switching at high speed and generating significant interference.

[0028] Edge combiners with symmetrical operation range at high speed are provided. In certain embodiments, an edge combiner generates an output signal indicating a delay between an edge of a first timing signal and an edge of a second timing signal. The edge combiner includes a circuit state element (for instance, a flip-flop or latch) having a first input controlled by the first timing signal, and a pulse generator that resets the circuit state element by controlling a second input of the circuit state element based on the second timing signal. The edge combiner further includes a first delay circuit, and an output logic gate having a first input connected to a data output of the circuit state element through a first signal path that bypasses the first delay circuit, a second input connected to the data output of the circuit state element through a second signal path that includes the first delay circuit, and an output that provides the output signal.

[0029] By implementing the edge combiner in this manner, symmetrical operation range at high speed is achieved.

[0030] In certain implementations, the first timing signal is provided to the edge combiner through a second delay element. By implementing the edge combiner in this manner, the second delay element pushes an edge of the output signal later in time. However, by doing this, the pulse width of the circuit state element's output is narrowed and may not reflect a desired target anymore. Accordingly, the first delay element operates in combination with the output logic gate to ensure that a final output pulse width is equal to the input phase difference between the first timing signal and the second timing signal.

[0031] The edge combiners disclosed herein can be used in a wide range of applications.

[0032] In one specific example, edge combiners can be used for combining output signals provided by a pair of DLLs used in a time of flight (ToF) application. Time of flight measurement techniques are attractive for a wide range of emerging 3D imaging applications including, but not limited to, facial recognition, augmented reality, machine vision, industrial automation and/or autonomous driving.

[0033] Although edge combiners can be used in time of flight systems, the teachings herein are applicable to a wide range of electronic systems.

[0034] FIG. 1A is a schematic diagram of a time of flight system 10 according to one embodiment. FIG. 1B is one example of a timing diagram for the time of flight system 10 of FIG. 1A.

[0035] The time of flight system 10 includes a two-chip architecture including an imager chip 1 and a laser driver chip 2 connected by an interface 3 (low-voltage differential signaling or LVDS, in this example). The imager chip 1 serves as a master chip that sends a signal pulse (for instance, an LVDS signal) to the laser driver chip 2.

[0036] The laser driver chip 2 controls emission of light output (using light emitting element 4, in this example) to an object 5, and the reflected light arrives at the receiver of the imager chip 1 sometime later. The light emitting element 4 can correspond to a wide variety of light emitting components including, but not limited to, a laser emitting element such as a vertical-cavity surface-emitting laser (VCSEL).

[0037] The imager chip 1 then calculates the distance to the object 5 by measuring the time or phase difference between the transmitted LVDS signal and the reflected light, with knowledge of the speed of light. The total delay (see FIG. 1B) is the sum of the driver's own propagation delay and the actual time of flight. The driver delay is typically calibrated out for each part at a certain temperature and voltage. However, it is complicated and costly to calibrate its drift over temperature and voltage, reducing its market viability.

[0038] FIG. 1C is a schematic diagram of a time of flight system 30 according to another embodiment. The time of flight system 30 of FIG. 1C includes an imager chip 1 and a laser driver chip 20 connected by an interface 3.

[0039] The time of flight system 30 of FIG. 1C is similar to the time of flight system of 10 of FIG. 1A except that the time of flight system 30 depicts a specific implementation of laser driver circuitry.

[0040] In particular, the laser driver chip 20 of FIG. 1C includes a receiver 11, a pair of DLLs 12, an edge combiner 15, a driver signal chain (pre-driver/driver circuitry) 16, a transimpedance amplifier (TIA) 17, and a replica receiver 18 operating on various feedback options (for instance, gate/drain replica/cathode/TIA). The laser driver chip 20 is coupled to a transmitting light element 19a and to a receiving light element 19b. For the TIA path (corresponding to an optical feedback option), the laser driver chip 20 uses a feedback path utilizing the transmitting light element 19a and the receiving light element 19b. The time of flight from the transmitting light element 19a to the receiving light element 19b is negligible (for instance, T.sub.VCSEL_PD about equal to 0 ns) because they are normally placed very close together in a module.

[0041] In the illustrated embodiment, the pair of DLLs 12 are used to align both the rising and falling edges of the output to the input signal, regardless if the signal itself is single-ended or differential. Additionally, the edge combiner 15 combines the output signals generated by the pair of DLLs 12 to generate an input driver signal for the driver signal chain 16.

[0042] The feedback loop to the DLLs 12 forces the input signal (INP, INN) to be aligned with one of the selected electrical feedback signals (VG, VD, VC) or optical feedback option (VTIA). In certain implementations, the laser driver chip 20 is further implemented with calibration for variation in one or more of the gate/drain replica/cathode/TIA nodes.

[0043] The pair of DLLs 12 and the edge combiner 15 operate as part of a dual DLL timing alignment system for controlling timing of the emission of light from the time of flight system 30.

[0044] In certain implementations, a dual DLL timing alignment system supports one or more of the following performance specifications: (1) alignment of both the output rising and falling edges to the input signal; (2) support of wide range frequency and multiple feedback options; (3) low alignment phase error drift over temperature and supply; and/or (4) well controlled bandwidth for fast locking/spread spectrum purposes.

[0045] By implementing a dual DLL timing alignment system with an edge combiner disclosed herein, the dual with edge combining feature ensures that the duty cycle of the light waveform is best regulated automatically without complicated and expected factory calibration. By reducing or avoiding factory calibration, a significant reduction in cost is achieved.

[0046] FIGS. 1D and 1E are examples of a timing diagram for the time of flight system 30 of FIG. 1C. The timing diagrams depict scenarios in which the edge combiner 15 of FIG. 1C could have unsymmetrical duty cycle and thus motivating a need for a design with symmetrical operation range.

[0047] There can be various circuit blocks having unsymmetrical rising and falling edge delay along the signal chain of a time of flight system. Such asymmetry can potentially distort the output light. The dual DLL timing alignment system of FIG. 1C can largely remove the impact of unsymmetrical rising and falling edge delay of these circuit blocks by adjusting the delay of the voltage-controlled delay lines (VCDLs) of the DLLs 12 when the loops are locked.

[0048] As shown in FIGS. 1D and 1E, the input timing signal of the edge combiner signal (VCDL, representing the output of VCDL1 or VCDL2 of the DLLs 12) could have wider of narrower than 50% duty cycle, depending on the delays of all the electrical and/or optical components around the loop. The edge combiner 15 following the VCDLs serves to generate a pulse train with a pulse width equal to a phase difference between a signal edge of a first input timing signal (output of VCDL1) and a signal edge of a second input timing signal (output of VCDL2).

[0049] Certain edge triggered edge combiner circuits can suffer from very unsymmetrical phase operation range input at high speed, which is unacceptable in some applications, including, but not limited to, the dual DLL timing alignment system of FIG. 1C.

[0050] An edge combining function is often desired in clocking or timing systems. Depending on the application and the nature of the input timing signals, various digital logic circuitry could perform this function with some limitations. However, without modification, conventional logic design is incapable of operating with symmetrical input phase range at high speed.

[0051] An edge combiner can include a pulse generator that operates in combination with a circuit state element (for instance, a flip-flop or latch) to provide edge combining. As a result, one side of the operation range is narrower than the other side. To guarantee large enough operation range on the narrower side, the pulse generator's width could be reduced, but this undesirably extends the wider operation range unnecessarily while imposing a significant risk of circuit malfunction due to pulses generated for the flip-flops or latches being too narrow.

[0052] An edge combiner is particularly susceptible to malfunction in a very harsh and noisy environment like a laser diode driver in which amps of current could be switching at high speed and generating significant interference. Thus, conventional designs, even aiming for high speed, could still be insufficient for complex timing systems, for instance, a timing alignment loop of a laser driver for the time of flight system 30 shown in FIG. 1C.

[0053] For example, in the embodiment of FIG. 1C, the edge combiner operates using two VCDL outputs (each associated with a different DLL) and generates a clock signal for driver circuitry. An edge combiner for such a system can be specified to support one or more of the following: (1) two input timing signals operating at the same frequency but over wide frequency range (for instance, tens to hundreds of MHz); (2) support symmetrical operation range (for instance, the input timing signal phase difference being centered around 180 degrees); (3) robust operation with not very well-defined input timing signal duty cycle; and/or (4) the output is only triggered by one edge (for instance, a rising edge or a falling edge) of each input timing signal.

[0054] In certain embodiments herein, an edge combiner is provided that operates robustly to achieve symmetrical operation range with relatively low complexity and engineering cost.

[0055] FIG. 2A is a schematic diagram of an example implementation of an edge combiner 50. As shown in FIG. 2A, the edge combiner 50 includes a d-type flip-flop (DFF) 41 and a pulse generator 42. The DFF 41 is edge sensitive with respect to a clock terminal (CK), but level sensitive with respect to a reset terminal (R). The edge combiner 50 of FIG. 2A is implemented to detect a phase difference between a rising edge of a first input timing signal (S1) and a rising edge of a second input timing signal (S2).

[0056] As shown in FIG. 2A, S1 connects to the CK terminal and S1's rising edge triggers the rising edge of the output signal (OUT). Additionally, S2 controls the R terminal (which is active high, in this example) that resets the DFF 41, thereby triggering the falling edge of OUT.

[0057] Because the R terminal is level sensitive instead of edge sensitive, the pulse generator 42 is included to reinitialize the R terminal (for instance, bring the R terminal back to low before the next rising edge of S1 arrives). The pulse could be either generated by S2 itself or with the feedback information from OUT (as depicted in the example of FIG. 2A). In either case, the width of this pulse should be wide enough to allow proper reset functionality (for instance, a minimum reset pulse width).

[0058] FIG. 2B is one example of a timing diagram for the edge combiner 50 of FIG. 2A. FIG. 3A is a first example of an operation range timing diagram for the edge combiner 50 of FIG. 2A. FIG. 3B is a second example of an operation range timing diagram for the edge combiner 50 of FIG. 2A.

[0059] With respect to FIGS. 2B-3B, T.sub.S is the signal period of S1 and S2. Additionally, T.sub.A is the time difference between an S2 rising edge to the previous S1 rising edge. Furthermore, T.sub.B is the time difference between an S2 rising edge to the next S1 rising edge, with T.sub.A+T.sub.B=T.sub.S. Additionally, T.sub.CK_Q is the DFF's CK to Q rising edge delay (D is tied to high, in this example). Furthermore, T.sub.S2_R is the S2 to R propagation delay through the pulse generator. Additionally, T.sub.R_Q is the DFF's R rising edge to Q falling edge delay. Furthermore, T.sub.W is the reset pulse width, which should be sufficiently long for proper reset function. Additionally, T.sub.OUT is the edge combiner's output pulse width.

[0060] For proper operation, it is desirable for the output signal width, T.sub.OUT, to be a delayed version of T.sub.A. Thus, it is desirable for T.sub.OUT and T.sub.A to be of about equal width.

[0061] One set of expressions for the minimum values of T.sub.A and T.sub.B are set forth below by Equations 1 and 2, respectively.

T.sub.A_MIN=max(T.sub.CK_Q−T.sub.S2_R,T.sub.REMOVAL)  Equation 1

T.sub.B_MIN=T.sub.S2_R+T.sub.PW+T.sub.RECOVERY  Equation 2

[0062] Equations 1 and 2 include two intrinsic properties of a DFF: T.sub.REMOVAL (removal time) and T.sub.RECOVERY (recover time). T.sub.RECOVERY and T.sub.REMOVAL correspond to the minimum amount of time that the R terminal should be inactive before and after the CK rising edge for proper operation, respectively, similar to setup and hold time of the D terminal. For T.sub.A_MIN, the output pulse could fail if S2 lags the previous S1 by either T.sub.CK_Q−T.sub.S2_R or T.sub.REMOVAL, whichever has a bigger value. Note that both terms can have positive or negative values. The timing diagrams of FIGS. 3A and 3B show an example of both terms being positive and T.sub.CK_Q−T.sub.S2_R determining the operation range.

[0063] In practice, T.sub.PW should be long enough to guarantee operation, which results in unsymmetrical operation range, especially at high frequencies. For instance, T.sub.A_MIN could be much larger than T.sub.B_MIN. Thus, the S2 signal rising edge can move very close to the previous S1 edge, but it cannot move much towards the next S1 edge.

[0064] In certain applications (for instance, time of flight systems), an edge combiner should have symmetrical operation range at high speed. The edge combiner 50 of FIG. 2A can be unsuitable for such applications.

[0065] FIG. 4A is a schematic diagram of one embodiment of an edge combiner 80. FIG. 4B is one example of a timing diagram for the edge combiner 80 of FIG. 4A. FIG. 4C is a schematic diagram of another embodiment of an edge combiner 80′. FIG. 4D is a schematic diagram of another embodiment of an edge combiner 80″. FIG. 5A is a first example of an operation range timing diagram for the edge combiner 80 of FIG. 4A. FIG. 5B is a second example of an operation range timing diagram for the edge combiner 80 of FIG. 4A.

[0066] The edge combiner 80 of FIG. 4A includes a circuit state element (a DFF 71, in this example), a pulse generator 72, a first delay element or circuit 75 connected to the data output of the DFF (between Q and QD and having falling edge delay T.sub.Q_QD), a second delay element 76 inserted between S1 and CK terminals (and having rising edge delay T.sub.S1_CK), and an output logic gate (OR gate 77, in this example). Q and QD are the two input signals of the output OR gate 77.

[0067] In the embodiment of FIG. 4A, the pulse generator 72 generates the pulse based on timing of S2 itself. However, other implementations are possible. For example, the edge combiner 80′ of FIG. 4B illustrates a configuration in which feedback information from a signal after the circuit state element 71 (for example, Q, QD, OUT, etc.) is used to control generation of the pulse of the pulse generator 72′.

[0068] Although FIG. 4A shows the technique of improving phase operation symmetry for one example edge combiner architecture, the teachings herein are applicable to other types of edge combiner architectures. For instance, the same methodology can be adopted to other types of edge combiners as well. The SR latch-based edge combiner shown in FIG. 6A and discussed in detail further below is one example of another edge combiner whose operation range can also be shifted to be symmetrical in accordance with the teachings herein.

[0069] In the illustrated embodiment of FIG. 4A, the edge combiner 80 detects a phase difference between a rising edge of S1 and a rising edge of S2, and thus the rising edge delay of T.sub.S1_CK and the falling edge of T.sub.Q_QD are of interest, which greatly simplifies the design process relative to implementation constrained by all combinations of rising and falling edges. By properly configuring the first delay element 75 and the second delay element 76 (which can have controllable delays), the operational range can be effectively shifted as shown in FIG. 4B.

[0070] The edge combiner 80 of FIG. 4A provides a number of advantages, such as relatively low complexity, robust performance (without overstressing design, layout and technology), low engineering cost and risk, and/or high flexibility (for instance, any of the depicted delay circuits and/or the pulse generator can have configurable delays).

[0071] As shown in FIG. 4B, the delay element 76 with delay T.sub.S1_CK pushes the rising edge of the output later in time by T.sub.S1_CK+T.sub.ORR, where T.sub.ORR is the rising edge delay of the OR gate 77. Now the total delay between the rising edge of the S1 and OUT is T.sub.S1_OUT=T.sub.CK_Q+T.sub.S1_CK+T.sub.ORR.

[0072] However, by doing this, the pulse width of the DFF's Q output, T.sub.QW, is narrowed and may not reflect the targeted T.sub.A anymore. Accordingly, in certain embodiments, the delay element 75 is included as shown in FIG. 4A. The delay T.sub.Q_QD of the delay element 75 and the OR gate 77 operate to ensure that the final output pulse width, T.sub.OUT, is equal to the input phase information, T.sub.A.

[0073] In certain implementations, either or both delay elements 75 and 76 have controllable delays. Additionally or alternatively, a pulse width of the pulse generator 72 is controllable. For example, the edge combiner 80″ of FIG. 4D illustrate a configuration in which at least one of the first delay element 75′, the second delay element 76′, or the pulse generator 72″ is controllable in delay. As will be appreciated by persons of ordinary skill in the art, such delay control can be achieved in a wide variety of ways including analog and/or digital techniques.

[0074] The operation range of the edge combiner 80 of FIG. 4A is graphically depicted in the examples of FIGS. 5A and 5B. Additionally, the minimum values of T.sub.A and T.sub.B are expressed below using Equations 3 and 4, respectively.

T.sub.A_MIN=T.sub.S1_CK+max(T.sub.CK_Q−T.sub.S2_R,T.sub.REMOVAL)  Equation 3

T.sub.B_MIN=T.sub.S2_R+T.sub.PW+T.sub.RECOVERY−T.sub.S1_CK  Equation 4

[0075] In comparison to the edge combiner 50 of FIG. 2A, the edge combiner 80 of FIG. 4A has a phase operation range shifted by T.sub.S1_CK. When it is desired to set T.sub.A_MIN=T.sub.B_MIN (for instance, centering the operation range around 180 degrees), the corresponding T.sub.S1_CK is given by Equation 5 below.

T.sub.S1_CK=½×T.sub.PW+½×[T.sub.S2_R+T.sub.RECOVERY−max(T.sub.CK_Q−T.sub.S2_R,T.sub.REMOVAL)]  Equation 5

[0076] With respect to Equation 5, the first term in the right-hand side of the equation is related to the minimum reset pulse width, while the second term relates to intrinsic properties of the pulse generator 72 and the DFF 71. When reset pulse width dominates, T.sub.S1_CK can be approximated by Equation 6 below.

T.sub.S1_CK≈½×T.sub.PW  Equation 6

[0077] In certain implementations, compensation is provided for correcting an offset between T.sub.OUT and T.sub.A due to the additional delay of T.sub.S1_CK. For example, this can be done by equating the delay from S1 to the rising edge of OUT and from S2 to the falling edge of OUT, yielding an expression for T.sub.Q_QD set forth in Equation 7 below.

T.sub.Q_QD=(T.sub.S1_CK−T.sub.S2_R)+(T.sub.CK_Q−T.sub.R_Q)+(T.sub.ORR−T.sub.ORF)  Equation 7

[0078] With respect to the right-hand side of Equation 7, T.sub.S1_CK is deliberately introduced, while other terms relate to properties of the pulse generator 72, the DFF 71, and the output OR gate 77.

[0079] FIG. 6 is a schematic diagram of another embodiment of an edge combiner 90. The edge combiner 90 includes a set-reset (SR) latch 81, a first pulse generator 82, a second pulse generator 83, a first delay element 85, a second delay element 86, and an AND gate 87. The SR latch 71 includes a first NAND gate 88 and a second NAND gate 89, which are cross-coupled. The edge combiner 90 receives a first input timing signal (S1) and a second input timing signal (S2), which are processed to generate an output signal (OUT) indicating a difference between an edge of S1 and an edge of S2.

[0080] As shown in FIG. 6, the delay element 86 pushes an edge of the output later in time. However, by doing this, the pulse width of the SR latch's output is narrowed and may not reflect a desired target anymore. Accordingly, the delay element 85 is included as shown in FIG. 6. The delay element 85 operates in combination with the AND gate 87, in this example, to ensure that the final output pulse width is equal to the input phase difference between S1 and S2.

[0081] The edge combiner 90 of FIG. 6 illustrates another embodiment of an edge combiner implemented in accordance with the teachings herein. In this example, the circuit state element corresponds to an SR latch, and the output logic gate corresponds to a 2-input AND gate. However, the teachings herein can be used to make symmetric the operation range of a wide range of circuits. For example, other types of state elements are possible, different implementations of logic gates can be used, and/or configurations using feedback for pulse generation are possible.

Applications

[0082] Devices employing the above described schemes can be implemented into various electronic devices. Examples of the electronic devices can include, but are not limited to, consumer electronic products, parts of the consumer electronic products, electronic test equipment, communication infrastructure applications, etc. Further, the electronic device can include unfinished products, including those for communication, industrial, medical, automotive, radar, and aerospace applications.

CONCLUSION

[0083] The foregoing description may refer to elements or features as being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematics shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected).

[0084] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments are presented in a given arrangement, alternative embodiments may perform similar functionalities with different components and/or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and/or modified. Each of these elements may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. Accordingly, the scope of the present invention is defined only by reference to the appended claims.

[0085] Although the claims presented here are in single dependency format, it is to be understood that any claim may depend on any preceding claim of the same type except when that is clearly not technically feasible.